Thesis Organization

In our work, the TEOS films that are deposited by atmospheric-pressure plasma technology (APPT) as gate dielectric layers of OTFT and we will use PECVD to do plasma treatment. Then pentacene films are deposited by a thermal evaporation system as active layers in OTFT. Last we will discuss the influence.

In chapter 1, we describe history of OTFT and motivation of our

study. And we introduce to organic semiconductor and structure.

In chapter 2, we will introduce a new process, APPT, which can be operated under low temperature and atmospheric ambient. And APPT will make use of deposit dielectric layer SiO

2

for our experiment. We will treat the dielectric layer by PECVD and fabricate it on OTFT device.

In chapter 3, we compare the various methods of MIM fabrication and we select the best parameter to fabricate OTFT. Last we discuss the results.

In chapter 4, we will describe the conclusions and the future works.

Figure 1-1 Semilogarithmic plot of the highest field-effect mobility(μ) Reported for OTFT fabricated from the most promising polymeric and oligomeric semiconductors versus year from 1986 to 2000[16]

Table 1-1: Highest field-effect mobility(μ) values measured from OTFT as reported in the literature annually from 1986 through 2000[16].

Figure 1-2 The Structure of Pentacene

Oligomer materials Channel Thin film deposition

Mobility (cm

²

/V-s)

Comments

α-6T(α-hexathienylene) p-type Vacuum evaporation

DH-α-6T(dihexyl-α-6T) p-type Vacuum evaporation

Pentacene p-type Vacuum

evaporation

Pentacene p-type 3.2

C

⁶⁰

(fullerene) n-type Vacuum evaporation

NTCDA n-type Vacuum

evaporation

1～3×10

^-3

Substrate at T=25℃

PTCDA n-type Vacuum

evaporation

10

^-5

～10

^-4

F

¹⁶

CuPc n-type Vacuum evaporation

0.03

Table 1-2: Thin film transistor performances for different oligomer active layers

(a)

(b)

Figure 1-3 (a) Cross section view of top contact structure of OTFT; (b) Cross section view of bottom contact structure of OTFT

Chapter 2 Experiment

2.1 Introduction of APPT

2.1.1 Introduction of plasma

Plasma can be described as a partially or wholly ionized gas with a roughly equal number of positively and negatively charged particles.

Some scientists have called plasma the "fourth state of matter" because while plasma is neither gas nor liquid, its properties are like those of both gases and liquids.

High temperature plasma and low temperature plasma are two kind of plasma. The lightning is a good example of naturally occurring high temperature plasma. This type of plasma can be artificially generated using a high voltage, high temperature arc, which is the basis for the corona discharge process and for the plasma torch used to vaporize and redeposit metals. Low temperature plasmas, used in surface modification and organic cleaning, are ionized gases generated at pressures between 0.1 and 2 torr. Working within a vacuum chamber where atmospheric gases have been evacuated typically below 0.1 torr by these types of plasmas. Accelerated electrons and ions are allowed for a relatively long free path by low pressure. Since the ions and neutral particles are at or near ambient temperatures and the long free path of electrons, which are at high temperature or electron volt levels, have relatively few collisions with molecules at this pressure the reaction remains at low temperature.

2.1.2 Applications of APPT

The atmospheric-pressure plasma technology (APPT) is useful for treating and modifying the surface properties of organic and inorganic materials. The APPT apparatus does not require any vacuum systems, produces a high density plasma, and provides treatment of various substrates at low temperatures while operating open to the atmosphere.

The plasma system has used for a wide variety of applications including treatment of polymer films, paper, wood, and foils; plasma grafting and plasma polymerization; ash various materials in the microelectronics industry; barrier layer deposition for the packaging industry; and sterilizing biologically contaminated materials. For polymer films, the technique offers the following advantages:

z Uniform treatment and No backside treatment.

z Improved surface energy with concomitant improved wettability, printability, and adhesion

z No additional vacuum system and low cost

z Continuous fabrication availably and high speed for production z High plasma density

As shown in Figure 2-1 (a), we exhibited the atmospheric-pressure plasma system which was used in our experiment, and also showed the other atmospheric-pressure plasma systems in Figure 2-1 (b).

2.1.3 Surface treatment

The dielectric polarity is modified by the self-assembled monolayer (SAM) on inorganic dielectrics. Inorganic dielectrics with lower surface energy proffer improved device performance; such surfaces reduce many

of interface traps in OTFTs [25,26]. However, it is an extra difficulty to control gate leakage [27]. As well as the increase in capacitance, it is an important factor for the surface polarity (hydrophilic or hydrophobic) of the gate dielectric [28]. However, the inorganic metal oxide dielectric with higher polarizability leads to the higher O-H group density on the interface and oppositely rough surface morphology. The formed O-H groups and the rough surface further affection the unprofitable quality of device performances. By this reason, the polymer-coating manner appears to be absolutely pervasive and thus could be used to any dielectric surface before organic semiconductor deposition [29~31]. In order to successfully integrate with OTFTs technology, there are a few important issues to be addressed, including degradation in channel mobility, charge trapping, and thermal stability.

2.1.4 Surface modification by plasma

Figure 2-2 shows the mechanisms of plasma surface modification, a glow discharge plasma is created by evacuating a reaction chamber and then refilling it with a low-pressure gas. The gas is then energized by one of the following types of energy: radio frequency, microwaves, and alternating or direct current. The energetic species in gas plasma include ions, electrons, radicals, metastables, and photons in the short-wave ultraviolet (UV) range. Surfaces in contact with the gas plasma are bombarded by these energetic species and their energy is transferred from the plasma to the solid. These energy transfers are dissipated within the solid by a variety of chemical and physical processes to result in a unique type of surface modification that reacts with surfaces in depths from

several hundred angstroms to 10µm without changing the bulk properties of the material.

A wide variety of parameters can greatly affect the physical characteristics of plasma and subsequently affect the surface chemistry obtained by plasma modification. Processing parameters, such as gas types, treatment power, treatment time and operating pressure, can be varied by the user; however system parameters, such as electrode location, reactor design, gas inlets and vacuum are set by the design of the plasma equipment. This broad range of parameters offers greater control over the plasma process than that offered by most high-energy radiation processes.

Plasma treatment is aiming for various goals as for example:

•

Improved adhesion

•

Removal of the "water skin"

•

Activation of the substrate surface

•

Modification of the substrate surface

•

Cleaning of substrate surfaces

Since the organic film of OTFT is fabricated on to the dielectric layer under the influence of the physical and chemical interactions between organic and dielectric layer, the OTFT performance strongly depends on the semiconductor/dielectric interface. The purpose of this work is to show the improvement of OTFT performance by controlling the surface treatments of dielectric/polymer interface. The surface properties such as frictional or abrasion, permeability, insulating properties, wettability and chemical reactivity are strongly dependent on a

molecular aggregation state of the surface [32,33]. Therefore, the control of a molecular aggregation state in the film is important to construct a highly functionalized surface. One of the most effective ways of studying surface properties is contact angle measurement. The contact angle is the angle between the tangent to the drop’s profile and the tangent to the surface at the interaction of the vapor, the liquid, and the solid. The contact angle is an index of the wettability of the solid surface. A low contact angle between solid surface water-drop indicates that the surface is hydrophilic and has a high surface energy. On the contrary, a high contact angle means that the surface is hydrophobic and has a low surface energy. The surface free energy was traditionally quantified by contact angle measurements [34,35].

2.2 Operation of organic thin film transistors

Mode (I): When zero bias is applied to three electrodes of OTFT.

The schematic diagram is shown in Figure 2-3 (a), it is called cut-off. If applied a small drain bias, Vd, and the source-current, Ids, will be small and ohmic.

Mode (II): When a positive bias applied, the bend bending will occur in the interface between dielectric layer and semiconductor layer.

Negative charges will locate at interface and form the depletion region.

The schematic diagram is shown in Figure 2-3 (b). The channel resistance is so large that the current will smaller than that of mode (I). Because of the large band gap, inversion layer cannot be observed in the organic thin-film transistor.

Mode (III): When gate bias is negative, the schematic diagram is shown in Figure 2-3 (c), the voltage is dropped over the insulator and over the semiconductor near the interface between dielectric layer and semiconductor layer. More positive charges will be accumulated in the accumulate region. When a small bias is applied to drain, the source-drain current will be larger than that of Mode (I), the schematic diagram is shown in Figure 2-3 (d).

Mode (IV): When drain voltage is negative enough that the voltage difference of gate and drain, Vgd, which is lower than Vth(<0), therefore, the depletion region will form near drain and pitch-off (Figure 2-3(e)). If drain voltage is more negative, the depletion region will grow and approach source. The schematic diagram is shown in Figure 2-3 (f).

2.3 Affect to capacitance of different conditions

2.3.1 Silicon oxide deposited by APPT on the metal insulator metal (MIM) structure and relation with flow of APPT

In this section, we are resolution to deposit silicon oxide dielectric on the bottom contact electrode metal by atmospheric-pressure plasma technology with different flows. But silicon oxide is not deposited on the metal at room temperature. Accordingly, we heat the bottom of n

⁺

-Si substrate and enable TEOS to be deposited on the metal.

First, an n-type bare silicon wafer is cleaned by the standard RCA cleaning process. An insulating layer of silicon dioxide is grown by

thermal oxidation (wet oxidation) 34min at 1000℃ for isolation purpose.

The thickness of silicon dioxide is 3040 Å measured by n&k system. And deposited 300 nm aluminum as the bottom electrode. Heats up the Tetraethoxy silane (TEOS) to 180℃ was injected by nitrogen (50％) and oxygen (50％) as carrier gases which is the deposition source of silicon oxide. Silicon oxide is deposited on the top of aluminum metal gate at room temperature under an atmospheric-pressure with the plasma power is established around 50 W with an appropriate scanning rate (cycle).

Silicon oxide is deposited on the aluminum thin film by atmospheric-pressure plasma technology (APPT) with varied flow (0.1sccm, 1sccm and 5sccm respectively). We adopt 60 times and heat 150 ℃ in the substrate parameters to compare with different flow of APPT.

Finally, all top contact electrodes are deposited 300 nm thick aluminum layer defined with shadow mask by thermal coater system. The active region pad of all capacitors is diameter 200 μm. The process flow is shown in Figure 2-4.

2.3.2 Silicon oxide deposited by APPT on the metal insulator metal (MIM) structure and relation with different metal gates

In this section, we are resolution to deposit silicon oxide dielectric on the bottom contact electrode metal by atmospheric-pressure plasma technology with different metal gate.But silicon oxide is not deposited on

the metal at room temperature. Accordingly, we heat the bottom of n

⁺

-Si substrate and enable TEOS to be deposited on the metal.

First, an n-type bare silicon wafer is cleaned by the standard RCA cleaning process. An insulating layer of silicon dioxide is grown by thermal oxidation (wet oxidation) 34min at 1000℃ for isolation purpose.

The thickness of silicon dioxide is 3040Å measured by n&k system. And deposited 30 nm different metals (Al(300nm), Ni, Pd, Ir, TaN) and different temperature of substrate as the bottom electrode. Heats up the Tetraethoxy silane (TEOS) to 180℃ is injected by nitrogen (50％) and oxygen (50％) as carrier gases which is the deposition source of silicon oxide. Silicon oxide is deposited on the top of different metal gate at room temperature under an atmospheric-pressure with the plasma power is established around 50 W with an appropriate scanning rate (sccm /cycle). We adopt 60 times and flow 0.1 sccm and heat 100, 150 and 200

℃ in the substrate parameters to compare with different metal gates.

Finally, all top contact electrodes are deposited 300 nm thick aluminum layer defined with shadow mask by thermal coater system. The active region pad of all capacitors was diameter 200 μm. The process flow rate is shown in Figure 2-5.

Additional we used atomic force microscope (AFM) to observe the surface morphology.

2.3.3 Plasma treatment of silicon oxide deposited by APPT

on the metal insulator metal (MIM) structure

In this section, we are resolution to try plasma treatment for silicon dioxide dielectric which is deposited by APPT. First, an n-type bare silicon wafer is cleaned by the standard RCA cleaning process. An insulating layer of silicon dioxide is grown by thermal oxidation (wet oxidation) 34min at 1000℃ for isolation purpose. The thickness of silicon dioxide is 3040Å measured by n&k system. And we deposited 30nm nickel as the bottom electrode. Heats up the Tetraethoxy silane (TEOS) to 180℃ was injected by nitrogen (50％) and oxygen (50％) as carrier gases which is the deposition source of silicon oxide. Silicon oxide is deposited on the top of nickel metal gate at room temperature under an atmospheric-pressure with the plasma power is established around 50 W with an appropriate scanning rate (sccm/cycle). Silicon oxide is deposited on the nickel thin film by atmospheric-pressure plasma technology (APPT) with 0.1 sccm and 60 times.

Then we use PECVD to do plasma treatment. The plasma power is established around 20 W and the treatment pressure is 68 Pa. We use of N

₂

and NH

₃

and to do plasma treatment. We divide two stages into the step. First, we regular the treatment time (1min) then change the gas quantity (50, 100, 200 and 400 sccm). Second, we select the better treatment flow then change the treatment time (0.5, 1, 2 and 4 min).

Finally, all top contact electrodes are deposited 30 nm thick nickel layer defined with shadow mask by Dual E-Gun system. The active region pad of all capacitors was diameter 200 μm. The process flow is shown in Figure 2-6.

In order to further analyze the phenomenon about surface treatment,

we used atomic force microscope (AFM) to observe the surface morphology. Contact angle was measured to judgethe surface state. We use SEM to measure the films thickness.

2.4 Fabrication of OTFT

In this section, for a start, we are resolution to choose nickel as gate in our experiment. Subsequently, silicon oxide is deposited by 0.1 sccm and 60 times of APPT. After we deposit the insulator, we choose the best plasma treatment parameter to treat the gate dielectric layers.

First, an n-type bare silicon wafer is cleaned by the standard RCA cleaning process. An insulating layer of silicon dioxide is grown by thermal oxidation (wet oxidation) 34min at 1000℃ for isolation purpose.

The thickness of silicon dioxide is 3040Å measured by n&k system. And deposit 30 nm thick nickel layer as the gate electrode. The nickel layer is deposited by Dual E-Gun and silicon oxide deposited by atmospheric-pressure plasma technology (APPT) at 200℃ under an atmospheric pressure with 0.1 sccm scanning 60 times is used as gate insulator. Then we use thermal coater to deposit 30 nm thick gold as source/drain electrodes. Pentacene is evaporated by thermal coater as active layer in our study. The channel length, L, is 100 µm and width, W, is 2000 µm. During deposition of pentacene active layer, the substrate is heated to 70℃ at power 17 W at a pressure chamber of around 1x10

^-6

Torr. The process flow is shown in Figure 2-7.

2.5 Characteristic measurement of devices

We use HP 4284A precision LCR meter parameter to analyze Capacitance-Voltage (C-V) characteristic diagrams at 1MHz and the characteristic curves of Current-Voltage (I-V) are measured with semiconductor parameter analyzer by HP 4156. We measure all measurements are at room temperature in an air atmosphere.

(a)

Multiple Plasma Jet System

• Scale-up of single jet for 3-D atmospheric coating

Handheld Plasma Applicator

(b)

Figure 2-1 (a) APP system of ITRI (b) the other APP systems

(a)

(b)

Figure 2-2 (a)The structure of APPT (b)The diagram of plasma surface treatment

(a) Vg = Vs = Vd = 0

(b) Vs = Vd = 0, Vg > 0

(c) Vs = Vd = 0, Vg < 0

(d) Vs =0, Vg < Vd < 0

(e) Vs =0, Vd < Vg < 0

(f) Vs = Vg = 0, Vd < 0

Figure 2-3 Schematic of operation of organic thin film transistor, showing

a lightly doped semiconductor; + indicates a positive charge in semiconductor; - indicates a negatively charge in semiconductor. (a) No-bias; (b) Depletion mode; (c) Accumulation mode; (d) Non-uniform charge density; (e) Pinch-off of channel; (f) Growth of the depletion zone

Figure 2-4 The MIM structure of different APPT flow rates

RCA clean N

⁺

substrate wafer

Thermal oxidation 34 min at 1000℃

Deposition of 300 nm aluminum as the bottom electrode

Deposition of SiO

2

by APPT with different flow rates (0.1, 1 and 5 sccm)

Deposition of 300 nm aluminum as the top electrode through shadow mask

Figure 2-5 The MIM structure of different metal gates

RCA clean N

⁺

substrate wafer

Thermal oxidation 34 min at 1000℃

Deposition of different metals (Al, Ni, Ir, TaN and Pd) as the bottom electrode

Deposition of SiO

2

by APPT with 0.1 sccm flow rate

Deposition of 300 nm aluminum as the top electrode through shadow mask

RCA clean N

⁺

substrate wafer

Thermal oxidation 34 min at 1000℃

Deposition of nickel as the bottom electrode

Deposition of SiO

2

by APPT with 0.1sccm flow rate 60 times

Surface treatment:

1. N

2

plasma 2. NH

3

plasma

Figure 2-6 The MIM structure of plasma treatment dielectric gate Deposition of 30 nm nickel as the top electrode through shadow mask

RCA clean N

⁺

substrate wafer

Thermal oxidation 34 min at 1000℃

Deposition of 30 nm nickel as the gate electrode

Deposition of SiO

2

by APPT with 0.1sccm flow rate 60 times

Surface treatment:

1. N

2

plasma 2. NH

3

plasma

Figure 2-7 The OTFT structure

Deposition of pentacene as the active layer

Deposition of 30 nm gold as the source and drain electrode

Chapter 3

Results and Discussion

3.1 Determination of threshold voltage and mobility

The linear regime field effect mobility can be obtained by the calculation described below. At low V

D

, I

D

increases linearly with V

D

(linear regime) and is approximately determined by the following equation: capacitance per unit area of the insulating layer, V

T

is the threshold voltage, and μ is the field effect mobility, which can be calculated in the linear regime from the transconductance,

G

^m

=

_n C _ox V _D

and equating the value of the slope of this plot to Gm, then find Gm,max which can gain the value of threshold voltage (V

_T

) and linear mobility.

For the known values included C

_ox

, V

T,

and W/L, the value of saturation mobility can be obtained from equation (3-3)

3.2 Result of different conditions

3.2.1 The influence of different flow rates

In our experiments, we try to test the different flow rates of APPT and discuss their influence. There are three different flow rates of APPT which 0.1, 1, and 5 sccm are used in our experiment. The other detail process will be not repeated in this section. Silicon oxide is deposited by APPT on the bottom electrode surface with different flow rates of APPT at substrate temperature at 150℃. The I-V and C-V characteristic is shown in Figure 3-1. The horizontal axis and vertical axis of Figure 3-1 (a) represent the swept voltage set and the value of capacitance respectively.

We can see the values of capacitor from Figure 3-1 (a) is influenced by the flow of APPT. We can know from the Figure 3-1 (a) the flow of carrier gases will influence the quantity that the TEOS gas comes out.

The flow of carrier gases increases and leads to the fact the coming out amount of TEOS gas to increase.

To summarize this section, we would choose 0.1 sccm as our optimal parameter. The leakage current density of 0.1 sccm is minimum and the breakdown voltage is maximum between the three deposition flow rates of APPT.

3.2.2 The influence of different metal gates

In our experiments, we try to test the different metal gates and discuss their influence. There are five different metal gates which Al, Ni, Ir, TaN and Pd are used in our experiment. The other detail process will be not repeated in this section. Silicon oxide is deposited by APPT on the bottom electrode surface with different metal gates at substrate

temperature at 100, 150 and 200℃. The I-V and C-V Characteristic is shown in Figure 3-2 ~ Figure 3-7. The horizontal axis and vertical axis of Figure 3-2(a) ~ Figure 3-7(a) represent the swept voltage set and the value of capacitance respectively. We can learn from the Figure 3-7 that

temperature at 100, 150 and 200℃. The I-V and C-V Characteristic is shown in Figure 3-2 ~ Figure 3-7. The horizontal axis and vertical axis of Figure 3-2(a) ~ Figure 3-7(a) represent the swept voltage set and the value of capacitance respectively. We can learn from the Figure 3-7 that

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