Thesis Organization

In chapter 1, a brief overview of 3D-ICs and LTPS TFTs technology was given to explain the crystallization process. The motivations of this thesis were subsequently explained to introduce this thesis.

In chapter 2, technologies for realizing 3D-stacked CMOS, including fabrication processes and design issues, were introduced. Then the elevated channel method and the single grain boundary polycrystalline silicon thin-film transistors with bottom gate structure were introduced. Also, the experimental processes of elevated channel thin films were introduced. The mechanism of lateral growth of elevated channel thin films was proposed by material analysis. The material properties were analyzed by scanning electron microscopy (SEM).

In chapter 3, the process flows for the fabrication of 3D-SSGB-TFTs were introduced.

The electrical characteristics, including the field-effect mobility, the subthreshold swing, the threshold voltage, and the uniformity were investigated. Also, the electrical characteristics of 3D-SSGB-TFTs for the CMOS applications would be discussed in detail.

Finally, summary and conclusions were given in chapter 4.

Chapter 2

Basic Concepts of 3D-Stacked CMOS and Fabrication of Location-Controlled

Single Grain Boundary by Elevated Channel Methods Using

Excimer Laser Annealing Devices

2.1 Technologies for Realizing 3D-Stacked CMOS

To reduce footprint and interconnect distance, stacking devices on top of each other to form integrated circuits with the multilayer structure is an effective way. Therefore, the realization of three-dimensional stacked complementary metal-oxide semiconductor (3D-stacked CMOS) could be an elementary goal for the 3D-IC applications. Generally, the technologies for realizing 3D-stacked CMOS could be classified into two major categories, one is that the active devices and interconnects interleaving each other and the other is that

the active devices and interconnects grouped separately, as illustrated in Fig. 2-1. Making active devices and interconnects interleave could provide flexibility in performing vertical and horizontal routing. Nevertheless, this method becomes impractical in the layer-by-layer process since the allowable thermal budget is significantly reduced after the formation of the interconnect metals. Moreover, the circuit density for this method would be limited by the via size and spacing that can be achieved. Therefore, this method becomes less attractive for applications requiring very densely packed active devices such as memory. The other method for realizing 3D-stacked CMOS is having all the active device layers formed before the interconnect metal. The active devices can be fabricated in a layer-by-layer sequential manner by this method. Furthermore, this method could allow the active devices to be packed very closely together and has been applied to fabricate high-density static random access memory (SRAM) cells [2.1]-[2.4]. The major challenge for this method is the formation of high-quality silicon films beyond the first device layer. To achieve high circuit density, wafer bonding after active device fabrication is less preferred because of the wafer-to-wafer misalignment between layers. As a result, to fabricate the 3D-stacked CMOS using the layer-by-layer process, the formation of high-quality upper silicon layers on the insulating dielectrics is definitely required. For further consideration of fabricating 3D-stacked CMOS with the layer-by-layer approach, several specific fabrication processes and design issues will be introduced in the following sections.

2.1.1 Fabrication Processes for Realizing 3D-Stacked CMOS

There are more factors have to be considered when fabricating the 3D-stacked CMOS, as opposed to the conventional 2D CMOS. In the layer-by-layer process, the devices in the bottom active layer are fabricated first before processing the top layer. One major concern in this process is the thermal budget experienced by the lower layer when processing the upper devices, which might result in serious dopant diffusion in the source, drain, and gate regions. This issue would not only limit the dopant activation process for the upper-layer devices but also the formation of high-quality silicon film for active device fabrication since most methods for the formation of high-quality silicon layers require high-temperature treatment. Therefore, using the conventional layer-by-layer process without the LTPS technology alone could only produce stacked CMOS circuits with a few layers. Considering the thermal budget, it is preferred to have the n-channel devices fabricated in the lower

layers and the p-channel devices fabricated in the upper layers because of the more serious diffusion at high temperature of p-type dopants (mostly boron) compared with n-type dopants.

Recently, some simultaneous multilayer processing methods have been developed in which all devices on different active layers are being fabricated at the same time. This method resolved the thermal budget problems in the conventional layer-by-layer process without the LTPS technology. As all devices are fabricated after the formation of multilayer high-quality silicon films, the constraints to anneal the material using low-temperature processes could be relieved. More mature material-handling processes such as layer transfer with wafer bonding and double separation by implantation of oxygen (SIMOX) can be used to form the multiple high-quality silicon device layers [2.5]. Nevertheless, the simultaneous multilayer processing presents many challenges, such as the gate definition of the lower layer, doping of the bottom devices, and interconnecting different layers. That is, the simultaneous multilayer processing still suffers from complex procedures and finite usable range. Therefore, the layer-by-layer process with novel LTPS technology might be the most promising fabrication approach for realizing the 3D-stacked CMOS due to its low thermal budget and simple procedures.

2.1.2 Design Issues for Realizing 3D-Stacked CMOS

In order to totally exploit the advantage of small footprint offered by the 3D-stacked CMOS structure, the layout of devices in standard circuit components must be carefully designed. Generally, a basic CMOS inverter requires the p-channel devices to have twice the channel width of the n-channel devices to provide symmetrical rise and fall time, as illustrated in Fig. 2-2 (a). When directly stacking the n-channel device and the p-channel device together, the footprint is apparently limited by the larger p-channel device as shown in Fig. 2-2 (b). Therefore, the area-saving resulting from the 3D-stacked CMOS structure is lower than expected. In more advanced CMOS technology, double-gate devices have been proposed. In this case, the p-channel devices can be implemented with the double-gate structure while the n-channel devices are designed with a conventional single-gate structure to reduce the footprint, as illustrated in Fig. 2-2 (c). That is, a 3D-stacked CMOS with both symmetric electrical characteristics and enhanced area-saving could be achieved at the same time by stacking a double-gate p-channel device and a single-gate n-channel device using

the same channel length and width.

2.2 Introduction to Elevated Channel Method

In order to realize LTPS thin films, several methods have been proposed, such as SPC, MILC, and laser annealing [2.6]-[2.9]. Among these methods, the ELC might be the most promising one due to simple process and no metal contamination issue. Moreover, the unique advantages of strong optical absorption of the UV light, which the excimer laser emits in, in silicon and short pulse duration show that high temperature could be produced in the silicon surface region without significant damage of glass substrates [2.10].

Furthermore, ELC polycrystalline silicon thin films show good crystallinity and few intra-grain defects because of the melt-regrowth process. During excimer laser annealing process, the mechanism of grain growth is very sensitive to the laser energy density, as illustrated in Fig. 2-3. As shown in Fig. 2-3 (a), when the laser energy density is sufficiently high to cause the complete melting of the entire a-Si thin film, homogeneous nucleation occurs for deep super-cooling, resulting in small grain size [2.11]. As shown in Fig. 2-3 (b), when the laser energy density is relatively low to cause only surface melting of a-Si thin films but not the entire silicon films, vertical solidification would occur and the un-melted solid layer remains to be a-Si, while the melted silicon layer already transform into polycrystalline silicon with small grain size [2.12]. When the laser energy density is controlled around a certain threshold value, large-grained polycrystalline silicon films could be obtained with grain sizes many times larger than the thickness of the total silicon film, as illustrated in Fig. 2-3 (c). This is the so-called super lateral growth (SLG) regime [2.13], which shows the behavior of melted a-Si to recrystallize from very few un-melted Si residues to each other. That is, the lateral growth phenomenon, which causes large grain size, could be realized with very few residues as seeds.

Nevertheless, there are still some limits for the ELC process even when the laser energy density is controlled in the SLG regime. Firstly, the seeds of SLG regime only appear randomly. That is, the location of grain and grain boundary could not be controlled and thus the variation of grain size would be large. Fig. 2-4 shows the non-uniformity of grain size. Secondly, there are many fluctuation factors in the ELC process, i.e., the pulse-to-pulse variation of excimer laser energy, the variation of a-Si film thickness, and the

narrow process window of ELC process. As a result, a novel method, the Elevated Channel Method, is proposed to enhance the uniformity of grain crystallinity and the location of grain and grain boundary. Furthermore, much larger process window could be obtained with the elevated channel method, as opposed to the conventional ELC process.

In the following sections, the experimental procedures of the elevated channel method would be introduced. The lateral-growth mechanism of the elevated channel method would be studied by material analysis equipments. The material properties of the elevated channel thin films were investigated by scanning electron microscopy (SEM).

2.3 Introduction to Single Grain Boundary (SGB) and Bottom Gate (BG) Polycrystalline Silicon Thin-Film Transistors Fabricated by Elevated Channel Method

The bottom-gate (BG) structure, which locates the gate electrode below the semiconductor layer, is the most common configuration for a-Si TFTs because of the clean interface. Therefore, if the bottom-gate is used for polycrystalline silicon TFTs, it would offer some benefits over the top-gate structure for the AMLCD applications. Firstly, clean interface control could be easily achieved because of the ability to deposit the gate dielectric and silicon films sequentially in a single system without breaking vacuum. Secondly, the plasma hydrogenation diffusion rate in the bottom-gate TFT structure is significantly higher than that in the top-gate (TG) TFT structure since the channel thin film is not blocked by the gate-electrode thin films during hydrogenation passivation. As a result, in the early stage of the development of LTPS TFTs, bottom-gate TFT structure was very attractive since the excimer laser annealing was thought as an additional process step to the a-Si TFTs.

Nevertheless, bottom-gate TFTs suffered from worse electrical performance than top-gate TFTs. Generally, the effective carrier mobility of bottom-gate TFTs is much lower than that of top-gate TFTs due to the smaller polycrystalline silicon grain size and poor crystallized silicon grain quality, which were resulted from the bottom-gate metal acting as a heat sink during the ELC process [2.14]-[2.15]. Therefore, only a few studies have been conducted

for bottom-gate TFTs with short channel length and top-gate TFTs have been widely adopted in AMLCDs for the last decade.

In the following sections, a novel and simple lateral grain growth method would be proposed using the conventional fabrication process of bottom-gate a-Si TFTs. When the excimer laser irradiation is applied on the a-Si thin film, the applied laser energy density is controlled to completely melt the thin region of a-Si film in the channel region but partially melt the thicker region of a-Si films near the edges of bottom gate. As a result, lots of un-melting solid seeds remain near the edges of bottom gate electrode and a lateral temperature gradient could be produced between the local thin and thick regions of a-Si film, and the lateral grain growth would start from the un-melted silicon solid seeds at the base neighbor to the bottom-gate corner, then extended toward the completely melted region until the solid-melt interface from opposite direction could impinge, as shown in Fig.

2-5. Therefore, large and uniform longitudinal grains could be formed in the device channel regions, which result in the improved device performance and uniformity. Furthermore, a wide laser process window could be also shown in this method.

2.4 Material Analyses of Single Grain Boundary Polycrystalline Silicon Thin Films Fabricated by Elevated Channel Method

2.4.1 Process Flows of Material Analyses of Single Grain Boundary Polycrystalline Silicon Thin Films Fabricated by Elevated Channel Method

The detailed process flows of prepared samples of the bottom layer and the top layer were shown in Fig. 2-6 and Fig. 2-7, respectively. For preparing the samples of the bottom layer, firstly, thermal oxide films with thickness of 20000Å-thick were deposited as buffer

oxide by atmospheric-pressure chemical vapor deposition (APCVD) at 980°C. Secondly, in-situ doping phosphorus polycrystalline silicon thin films with thickness of 1000Å-thick were deposited by pyrolysis of pure SiH4 and PH3 by low-pressure chemical vapor deposition (LPCVD) at 550°C on the buffer oxide. Thirdly, the doped polycrystalline silicon layer was defined to form polycrystalline silicon gate by transverse coupled plasma reactive ion etch (TCP-RIE). Fourthly, a 1000Å-thick TEOS oxide layer was deposited as gate oxide by LPCVD at 700°C. Fifthly, a 1000Å-thick amorphous silicon layer was deposited as the active layer by LPCVD at 550°C with SiH4 as gas source. The elevated channel was named after the channel region which is elevated for bottom-gate structure.

Laser crystallization was performed by KrF excimer laser (λ=248nm). The excimer laser system was shown in Fig. 2-8. During the laser irradiation, the samples were located on a substrate in a vacuum chamber pumped down to 10^-3Torr and the substrate was maintained at room temperature. The number of laser shots per area was 20 (i.e., 95% overlapping) and laser energy density was varied. For preparing the samples of the top layer, the process flows started from the already prepared bottom layer samples. Firstly, TEOS oxide films with different thicknesses of 1000Å and 5000Å were deposited as separation oxide by LPCVD at 700°C. Secondly, the same fabrication processes, including the polycrystalline silicon gate, the TEOS gate oxide, and the amorphous silicon active layer, of the bottom layer samples were repeated. Then, excimer laser crystallization with the same conditions of the bottom layer samples were also repeated. The grain structure of the crystallized polycrystalline silicon thin film was analyzed using the scanning electron microscopy (SEM). Besides, in order to facilitate the SEM observation, all the samples were processed by Secco etching before SEM analysis.

2.4.2 Scanning Electron Microscopy (SEM) Analysis

It has been reported that lateral thermal gradient could arise as a result of the heat generated at moving solid-melting interface [2.16]. When a proper laser energy density irradiated the silicon thin film containing different thicknesses, the thin region in the channel region was completely melted while the thick region in the corner due to the step structures of the bottom gate was only partially melted, leaving behind islands of solid material. Therefore, grains would grow laterally towards the complete melting region from the retained solid seeds. The lateral growth would start from the still solid amorphous

silicon spacer seeds and stretch toward the completely melted region until the solid-melt interface from opposite direction collided. The grain boundaries perpendicular to the current flow in the channel region could be reduced because of the in-situ design of thin channel region. As a result, the field-effect mobility of polycrystalline silicon TFTs could be greatly enhanced with this crystallization method. On the other hand, when a longer channel length was adopted for this crystallization method, the laser energy would have to be increased high enough to make longitudinal grains collide with those grown from the other side, or small grains resulted from spontaneous homogeneous nucleation would form in the center of the channel region.

Fig. 2-9 and Fig. 2-10 show the SEM graphs of polycrystalline silicon thin films in the bottom layer with different laser energy densities while the channel length was kept at 1.2μm and 2μm, respectively. Also, Fig. 2-11 shows the SEM graphs of polycrystalline silicon thin films in the bottom layer with different channel lengths while the laser energy density was kept at 460mJ/cm². It was found that the largest size of longitudinal grains formed in the channel was about 0.7μm, which means that the single grain boundary could be achieved when the channel length was under 1.5μm and proper laser energy densities were applied. As the laser energy density was increased from 420mJ/cm² to 500mJ/cm², we obtained analogous gate structure in channel region. As expected, when the laser energy densities are controlled to complete melt of 1000 Å-thick silicon thin film in the channel region but partial melting of the thicker a-Si film near the edge of the bottom-gate corners, there are always two columns of longitudinal grains colliding in the middle of channel region. Therefore, if the channel length were adjusted in a moderate distance, lateral grain growth will be manufactured without any spontaneous nucleation as the applied laser energy density is beyond the fully melting threshold of the thin a-Si region. If the spontaneous nucleation can be suppressed or delayed, the lateral grain growth would become longer, thus producing larger silicon grains. The higher local temperature in the completely melting region resulting from the higher laser energy density implies that the corresponding longer time to achieve the deeply super-cooling is required for spontaneous nucleation. As a result, while the channel length was kept at 1.2μm and 2μm, larger grains were obtained when the laser energy density was 460mJ/cm², as opposed to the laser energy density was under 440mJ/cm². On the other hand, while the channel was kept at 1.2μm and 2μm, the obtained grains were almost the same with different laser energy densities of 460mJ/cm² and 500mJ/cm², which means that the total a-Si layer was not completely melted when laser energy density was 500mJ/cm², thus the deeply super-cooling would not

generate at corners of the bottom gate. That is, we could conclude that the process window of the elevated channel method is much larger than that of conventional excimer laser annealing on whole flat amorphous silicon thin film. For comparison, conventional SPC polycrystalline silicon thin films with the same bottom-gate structure as the ELC samples were also fabricated in the same run, as shown in Fig. 2-12.

Fig. 2-13 shows the SEM graphs of polycrystalline silicon thin films in the top layer on a 5000Å-thick separation oxide layer with different laser energy densities while the channel length was kept at 1.2μm, and Fig. 2-14 shows the SEM graphs of the same films with different channel lengths while the laser energy density was kept at 460mJ/cm². It was found that the results of lateral growth, including the largest grain size and process window, were almost the same as in the bottom layer. Moreover, when the thickness of the separation oxide layer was changed to 1000Å, the same results of lateral growth as in the bottom layer were obtained in the top layer again, as shown in Fig. 2-15 and Fig. 2-16.

Therefore, stacked SGB polycrystalline silicon thin films isolated by separation oxide layers were successfully achieved by means of the elevated channel method. What is more, the process window of this method was almost the same for separation oxide layers with

Therefore, stacked SGB polycrystalline silicon thin films isolated by separation oxide layers were successfully achieved by means of the elevated channel method. What is more, the process window of this method was almost the same for separation oxide layers with