Technologies for Realizing 3D-Stacked CMOS

To reduce footprint and interconnect distance, stacking devices on top of each other to form integrated circuits with the multilayer structure is an effective way. Therefore, the realization of three-dimensional stacked complementary metal-oxide semiconductor (3D-stacked CMOS) could be an elementary goal for the 3D-IC applications. Generally, the technologies for realizing 3D-stacked CMOS could be classified into two major categories, one is that the active devices and interconnects interleaving each other and the other is that

the active devices and interconnects grouped separately, as illustrated in Fig. 2-1. Making active devices and interconnects interleave could provide flexibility in performing vertical and horizontal routing. Nevertheless, this method becomes impractical in the layer-by-layer process since the allowable thermal budget is significantly reduced after the formation of the interconnect metals. Moreover, the circuit density for this method would be limited by the via size and spacing that can be achieved. Therefore, this method becomes less attractive for applications requiring very densely packed active devices such as memory. The other method for realizing 3D-stacked CMOS is having all the active device layers formed before the interconnect metal. The active devices can be fabricated in a layer-by-layer sequential manner by this method. Furthermore, this method could allow the active devices to be packed very closely together and has been applied to fabricate high-density static random access memory (SRAM) cells [2.1]-[2.4]. The major challenge for this method is the formation of high-quality silicon films beyond the first device layer. To achieve high circuit density, wafer bonding after active device fabrication is less preferred because of the wafer-to-wafer misalignment between layers. As a result, to fabricate the 3D-stacked CMOS using the layer-by-layer process, the formation of high-quality upper silicon layers on the insulating dielectrics is definitely required. For further consideration of fabricating 3D-stacked CMOS with the layer-by-layer approach, several specific fabrication processes and design issues will be introduced in the following sections.

2.1.1 Fabrication Processes for Realizing 3D-Stacked CMOS

There are more factors have to be considered when fabricating the 3D-stacked CMOS, as opposed to the conventional 2D CMOS. In the layer-by-layer process, the devices in the bottom active layer are fabricated first before processing the top layer. One major concern in this process is the thermal budget experienced by the lower layer when processing the upper devices, which might result in serious dopant diffusion in the source, drain, and gate regions. This issue would not only limit the dopant activation process for the upper-layer devices but also the formation of high-quality silicon film for active device fabrication since most methods for the formation of high-quality silicon layers require high-temperature treatment. Therefore, using the conventional layer-by-layer process without the LTPS technology alone could only produce stacked CMOS circuits with a few layers. Considering the thermal budget, it is preferred to have the n-channel devices fabricated in the lower

layers and the p-channel devices fabricated in the upper layers because of the more serious diffusion at high temperature of p-type dopants (mostly boron) compared with n-type dopants.

Recently, some simultaneous multilayer processing methods have been developed in which all devices on different active layers are being fabricated at the same time. This method resolved the thermal budget problems in the conventional layer-by-layer process without the LTPS technology. As all devices are fabricated after the formation of multilayer high-quality silicon films, the constraints to anneal the material using low-temperature processes could be relieved. More mature material-handling processes such as layer transfer with wafer bonding and double separation by implantation of oxygen (SIMOX) can be used to form the multiple high-quality silicon device layers [2.5]. Nevertheless, the simultaneous multilayer processing presents many challenges, such as the gate definition of the lower layer, doping of the bottom devices, and interconnecting different layers. That is, the simultaneous multilayer processing still suffers from complex procedures and finite usable range. Therefore, the layer-by-layer process with novel LTPS technology might be the most promising fabrication approach for realizing the 3D-stacked CMOS due to its low thermal budget and simple procedures.

2.1.2 Design Issues for Realizing 3D-Stacked CMOS

In order to totally exploit the advantage of small footprint offered by the 3D-stacked CMOS structure, the layout of devices in standard circuit components must be carefully designed. Generally, a basic CMOS inverter requires the p-channel devices to have twice the channel width of the n-channel devices to provide symmetrical rise and fall time, as illustrated in Fig. 2-2 (a). When directly stacking the n-channel device and the p-channel device together, the footprint is apparently limited by the larger p-channel device as shown in Fig. 2-2 (b). Therefore, the area-saving resulting from the 3D-stacked CMOS structure is lower than expected. In more advanced CMOS technology, double-gate devices have been proposed. In this case, the p-channel devices can be implemented with the double-gate structure while the n-channel devices are designed with a conventional single-gate structure to reduce the footprint, as illustrated in Fig. 2-2 (c). That is, a 3D-stacked CMOS with both symmetric electrical characteristics and enhanced area-saving could be achieved at the same time by stacking a double-gate p-channel device and a single-gate n-channel device using

the same channel length and width.