Chapter 1 Introduction
1.2 Thesis Organization
In the Chapter 2 of the thesis, some theoretical MOSFET noise model and noise theory are introduced. Although these basic concepts provide a guidance to design a low noise amplifier, it is not enough to design a superior fully on-chip CMOS LNA including the consideration of some other important figure of merit such as gain, power consumption etc. . A systematic LNA design method associated with CMOS process is developed earlier [3] and represented in this chapter.
In the Chapter 3, a narrow band LNA using Darlington pair structure intended for application of the 5-GHz wireless LAN is introduced. The detailed circuit analysis and design equation is presented. Circuit simulation and comparison with single-ended inductive source degeneration topology are also discussed. Finally, measurement result of the LNA chip fabricated by TSMC 0.18um CMOS technology is discussed.
In the Chapter 4, a 3 to 8-GHz wideband amplifier intended for UWB system is proposed. The gain flatness technique using frequency compensation method to derive flat gain over the entire frequency band is introduced. The combination of negative feedback resistor and inductive source degeneration network is designed to achieve input matching.
Also, some design consideration and trade-off is discussed. The measured data and simulation result of the circuit is compared and discussed. Finally, based on the measurement result of this chip, a second modified version is designed to achieve better performance. Also, the variable gain function is added to the circuit. In the last chapter, all the work is summarized and concluded.
Chapter 2
Low Noise Amplifier Basic Concepts
In this Chapter, some theoretical MOSFET noise model and noise theory are presented in section 2.1. Although these basic concepts provide a guidance to design a low noise amplifier, it is not enough to design a superior fully on-chip CMOS LNA including the consideration of some other important figure of merit such as gain, power consumption etc..
In section 2.2, a systematic narrow band LNA design method associated with CMOS process developed earlier [3] is discussed. Finally, some broadband LNA architecture is discussed in section 2.3
2.1 Noise in MOSFET
To develop good CMOS RF circuit design skills, a fundamental understanding of noise source in a MOSFET is necessary. Noise can be roughly defined as any random interference unrelated to the signal of interest, which can be sorted out interference noise and inherent noise. Interference noise results from interaction between circuit and outside world, or between different parts of the circuit itself. Interference noise can be reduced by carefully circuit layout and wire routing. On the other hand, inherent noise originates from the fundamental property of the circuit itself and it can be reduced but never eliminated. Inherent noise is only moderately affected by circuit layout, such as using multiple finger number to reduce the gate resistance of a MOSFET. However, inherent noise can be significantly reduced by proper circuit design, such as choosing circuit topology and increasing power consumption.
2.1.1 Source of Noise
drain
2
i
ndsource
In this section, we will focus on the inherent noise of a MOSFET, which can be categorized into three parts: drain noise, gate noise and Flicker noise, mainly.
2.1.1.1 Drain Noise
The dominant noise source in a MOSFET is the channel noise, which basically is a thermal noise originated from the voltage-controlled resistor mechanism of a MOSFET. Thus, one would expect noise commensurate with the resistance value. Indeed, detailed theoretically considerations lead to the following expression for the channel noise of a MOSFET, which is modeled as a shunt current noise “ “in the output current of the device, as shown in Fig.2.1:
(2-1)
Where gd0 is the zero-bias drain conductance of the device, and γ is a bias dependence factor.
In long channel device, the value of parameter γ is unity at zero drain-source voltage, and decreased to 2/3 when device is saturated. Unfortunately, γ is much greater than 2/3 for short channel device operating in saturation. This excess noise is originated from carrier heating by large electric field in short channel device. This value would worsen the noise performance as the technology proceeds.
2.1.1.2 Gate Noise
In addition to channel noise, the thermal agitation of channel charge has another important consequence: gate noise. If the MOSFET are biased so that channel operates in the inverted condition, fluctuations in channel charge will induce physical current in the gate due to capacitive coupling. Although this noise can be neglected at low frequencies, it dominates
f g kT 4
i2nd = γ d0∆
2
ind
Fig.2.1 drain current noise model
gate
at radio frequencies. The companion effect of the gate noise that occurs at high frequencies arises due to its ‘distributed’ nature of the MOSFET. As operating frequency approaches cutoff frequency ωt of a MOSFET, the gate impedance of the device exhibits a significant phase shift from it purely capacitive value at lower frequencies. This shift can be accounted for a real, noiseless conductance, gg, in the gate current. Thus, the circuit model to represent the gate noise is the current noise connected between gate and source terminal shunted by a conductance gg, as shown in Fig.2.2 (a). Van der Ziel [4] has shown that the gate noise may be expressed as
(2-2) where the parameter gg
and the typical value of the coefficient of gate noise “δ”, equal to 3/4 in long channel device while 4 to 6 in short channel one. The gate noise current clearly has a power spectral density that is not constant. In reality, gate noise increases as frequency increases, so it is often called
“blue noise” to continue the optical analogy. For those who prefer not to analyze a system that has no blue noise source, it is possible to recast the model in a form with a noise voltage source that possesses a constant power spectral density. The alternative model can be derived first transform the parallel RC network into equivalent series RC network. If one assumes
high Q of the network, then the capacitance C would roughly not change during the transformation, while the parallel resistance becomes a series resistance whose value is
(2-3) which is independent of frequency. Finally, equate the short circuit currents of the original network and the transformed version, the equivalent voltage noise source is then found to be (2-4) which possesses a constant power spectral density. Hence, the final noise model contains a voltage noise source in series with a equivalent resistance whose value is not dependent on the frequency as shown in Fig.2.2(b).
Because the two noise source do share a common origin, they are also correlated, that is, there is a component of the gate noise current that is proportional to the drain current on an instantaneous basis. The correlation between gate and drain noise can be expressed mathematically as follows [4]:
(2-5)
where the value of 0.395j is exact for long channel devices. The correlation can be treated by expressing the gate noise as the sum of the two components, the first of which is fully
correlated with the drain noise, and the second of which is uncorrelated with the drain noise.
Hence, the gate noise is re-expressed as
(2-6) where the first term is uncorrelated and the second term is correlated to drain noise. Because of the correlation, special attention must be paid to the reference polarity of the correlated component. The value “c” is positive for the polarity shown in Fig.2.2 (a)
f
drain
Charge trapping and releasing by the defects and impurities on the interface between thin oxide and channel are usually invoked to explain the flicker noise (1/f noise). Since a MOSFET is surface device, it would exhibit more 1/f noise than bipolar device. One means of comparison is to specify a ‘corner frequency’, where the flicker noise is equal to the thermal noise. A lower corner frequency means less total noise. In RF circuit design, it is not important to care about flicker noise in bipolar devices, whose corner frequency often below tens or hundreds of hertz, while MOSFET often exhibit 1/f corners of tens of kilohertz to a megahertz or more. For a MOSFET, the 1/f noise can be represented by a drain current noise connected between drain and source terminal as shown in Fig2.3, and its value is
(2-7)
where “A” is the area of the gate(=WL) and K is a device-specific constant. For NMOS device, K is typically about 10-28 C2/m2, whereas for PMOS devices it is about 50 times larger. From the first equation above, one can observe that larger dimension size and thinner dielectric exhibit less 1/f noise, because larger gate capacitance smoothes the fluctuations of the channel charge. For the second equation, one can see the 1/f would worsen as technology proceeds because of the positive proportional dependence on the cutoff frequency (ωt).
2.1.2 Noise Models of the MOS Transistors
From previous introduction of noise source, a standard MOSFET noise model is
Fig.2.4(a) MOSFET noise model f
Fig.2.3 Flicker noise model
Fig.2.4 (b) equivalent input referred noise model
presented in Fig.2.4. In Fig.2.4 (a), is the drain current noise, and is the gate current noise, which is separated into correlated ( ) and uncorrelated ( ) terms. Also, is added to represent the noise originated from the parasitic resistor of gate terminal, which may be due to the gate resistor of the device or the parasitic resistor of the input inductor. Also, we have neglected the effect of gg under the assumption that the gate impedance is largely capacitive at the frequency of interest. Here, the noise model also can be represented as a noiseless network together with two equal noise sources ( and ) in Fig.2.4 (b). The relationship between two equivalent models is as follows
(2-7)
(2-8)
2.2 Low Noise Amplifier Basic
In this section, we discuss some LNA architecture, and introduce the most popular architecture, inductive source degeneration topology [3].
2.2.1 Low Noise Amplifier Topology and Basic
In the design of low noise amplifiers, there are several common goals. These include minimizing the noise figure of the amplifier, providing gain with sufficient
Rg
linearity—typically measured in terms of the third-order intercept point, IP3—and providing a stable 50Ω input impedance to terminate an unknown length of transmission line which delivers signal from the antenna to the amplifier. A good input match is even more critical when a pre-select filter precedes the LNA because such filters are often sensitive to the quality of their terminating impedances. The additional constraint of low power consumption which is imposed in portable systems further complicates the design process.
The first work of designing LNA circuit is to provide stable input impedances. Here, the four basic architectures are illustrated in simplified form in Fig 2.5. Each of these architectures may be used in a single-ended form, or in a differential form. Note that differential form will require the use of a balun or similar element to transform the single-ended signal from the antenna into a differential signal. Practical baluns introduce extra loss which adds directly to the noise figure of the system.
Zin
Zin
Zin
Zin
(a) (b)
(d) (c)
Fig.2.5 Common LNA architecture (a) Resistive termination (b) 1/gm termination (c) shunt-series feedback, and (d) inductive degeneration
The first technique uses resistive termination of the input port to provide a 50Ω impedance. There are two effects to degenerate the noise performance of the amplifiers. First, the added resistor contributes its own noise to the output which equals to the contribution of the source resistance. Second, the input is attenuated by the added input resistance. The larger noise penalty resulting from these effects therefore makes this architecture unattractive for the more general situation where a good input termination is desired. A second approach uses the source of the common-gate stage as the input termination, is shown in Fig 2.5(b). A simplified analysis of the common-gate architecture, assuming matched conditions, yield the following lower bounds on noise factor for the cases of and CMOS amplifiers
CMOS:
where the γ is the coefficient of the channel thermal noise and α is the ratio of the device trans-conductance gm and zero-bias drain conductance gd0 . In the short-channel device, α is smaller than one and γ is greater than one due to hot electrons in the channel. Above the previous analysis, the minimum theoretically achievable noise figure tend to be around 2.2dB or greater practically.
The third architecture of the amplifiers is shunt-series feedback, as illustrated in Fig 2.5(c). In this topology, input-matching and output-matching network can be achieved by using shunt and series feedback resistances. However, the amplifiers using that shunt-series feedback usually have high power dissipation compared to other types of low noise amplifiers.
The higher power consumption is partially owing to the fact that shunt-series amplifiers are wideband ones. In many applications, such as GPS, GSM, a wideband front end is not required and it is able to make use of the narrowband structure to reduce power. For this reason, the shunt-series feedback method is not applied in the narrow band design. The Forth architecture utilizes inductive source degeneration impedance as represented in Fig 2.5(d) to generate a real term in the input impedance. The narrow band matching can get good power
) dB ( 2 . 3 2 1 5
F ≥ =
α + γ
=
performance as well as better tuning of the input matching of amplifiers. This technique is not only used in the narrow-band wireless communications, such as GPS or GSM receivers, but also employed for ultra-wideband system, which we will introduce in Chapter 4. In the following section, the discussion of low noise amplifier will focus on the inductive source degeneration structure.
2.2.2 Inductive Source Degeneration LNA
In 1997, Thomas H. Lee and Derek K. Shaeffer suggested a popular method to optimize the noise performance of the inductive source degeneration (ISD) LNA [3]. In the section, the noise optimization on the inductive degeneration topology under gain and power constraint is discussed.
2.2.2.1 Operational Basic and noise figure calculation
Selecting the first stage of a LNA is a very important thing for obtaining good noise and input matching. The topology of the cascode LNA with ISD and the equivalent circuit for input stage noise calculation are shown in Fig 2.6(a) and Fig 2.6(b). In Fig 2.6(a), the input impedance of the cascode amplifier is represented by
2
vrg Rg 2
ingu ingc2 Cgs
+
− vgs
2
ind gs
mv
g g L
Ls
Rs
VDD 2
iout
2
vs
Lg
Ls
M1
M2
Vbias
Zin
(a) (b)
Fig.2.6 (a) Common source input stage (b) input stage of ISD LNA noise model
C )
where we obtain the input impedance Zin is equal to the multiplication of cutoff frequency of the device and source inductance at resonant frequency, this value will be set to 50Ω for input matching. In Fig 2.6(b), Rg represents the series resistance of the inductor as well as the gate resistance of the NMOS device, and represents the channel thermal noise of the device, while the and are the gate noise with correlated and uncorrelated term. Here, analysis based on this circuit neglects the contribution of subsequent stages to the amplifier noise figure. This simplification is justifiable provided that the first stage possesses sufficient gain and permits us to examine in detail the salient features of this architecture. Then recall the noise figure for a circuit is defined as:
(2-10)
To find the output noise, we first evaluate the trans-conductance of the input stage. With the output current proportional to the voltage on Cgs and nothing that the input circuit takes the form of series-resonant network, the trans-conductance at the resonant frequency is given by
(2-11)
where Qin is the effective Q of the amplifier input circuit. From this equation, the output noise power density due to the source is
(2-12) In a similar way, the output noise power density due to Rg can be expressed as
source
(2-13) Next, the noise power density associated with the correlated portion of the gate noise and drain noise can be expressed as
(2-14) where
The last noise term is the contribution of the uncorrelated portion of the gate noise. This contributor has the following power spectral density:
(2-15)
where
We observe that the equation (2-14) and (2-15) can all proportional to the power spectral density of drain current noise, then the two equation can be combined as a simplified form:
(2-16) where χ is defined as
According to (2-10), (2-13) and (2-16), the noise figure at the resonant frequency can be written by the following equation:
2
(2-17) To understand the implications of this new expression for F, we observe that χ includes terms which are constant, proportional to QL, and proportional to QL2. It follows that (2-17) will contain terms which are proportional to QL as well as inversely proportional to QL. Therefore, a minimum F exits for a particular QL.
2.2.2.2 Optimizations of LNA Design Flow
So far, we have analyzed the noise performance of the input stage of an inductive source degeneration topology. This analysis can now be drawn upon in designing the LNA. Besides noise performance, gain and power dissipation are another important considerations in LNA circuit design. In this subsection, how to pick the appropriate device width and bias point to optimize noise performance given specific objectives for gain and power dissipation is our goal.
To quantify these terms, a simple second-order model of the MOSFET trans- conductance can be employed which accounts for high-field effects in short channel devices.
Assume that drain current Id has the form
sat
where Cox is the gate oxide capacitance per unit area, νsat is the saturation velocity, and εsat
is the velocity saturation field strength. To simplify the following analysis, (2-18) can be reformulated as
Because the device M1 must operate in saturation region, the range of overdrive should be Hence, the parameter η should be within the range
sat
Having established an expression for Id, we can formulate the power consumption of the amplifier as follows:
To differentiate (2-18), we can determine the trans-conductance of device M1 )
From (2-22), we can derive the cutoff frequency of the device M1
L
Here, we have assumed that gate-source capacitance is equal to (2/3)WLCox, and the gate-drain capacitance(Cgd) have been neglected. Substituting (2-23) into (2-11) gives
] This expression shows that the trans-conductance of the input stage is only dependent on the bias condition and frequency of operation given specific technology and source resistance, while the power dissipation not only depend on bias condition but also on the gate width of device M1 as shown in (2-22).
Finally, substituting (2-24) into (2-17) gives
1
The expression shows that a minimum F exits for a particular width W, and the higher the bias point, the lower the F.
There are two approaches to this optimization problem which deserve special attention.
The first assumes a fixed trans-conductance, Gm, for the amplifier. The second assumes fixed power consumption. Now, we review the two different conditions using the equation we have developed.
1) Fixed Gm optimization: To fix the value of the trans-conductance, Gm, we need only assign a constant value to η. Once η is determined, we can minimize the noise factor by taking
WF =0
∂
∂ (2-27)
which, after some algebraic manipulations, results in
(2-28)
The optimal width will gives the minimal noise factor given that bias condition has been determined by Gm. Finally, the power consumption is determined by the optimal width and bias condition. In this approach, the main advantage is that designer can choose the
1
The disadvantage is that we sacrifice the power consumption to achieve noise performance.
2) Fixed PD Optimization: An alternative method of optimization fixes the power dissipation and adjusts width, W, and bias point, ρ, to minimize the noise factor. Under fixed
2) Fixed PD Optimization: An alternative method of optimization fixes the power dissipation and adjusts width, W, and bias point, ρ, to minimize the noise factor. Under fixed