Chapter 3 5.5 GHz High Gain LNA Using Darlington
3.3 Discussion on Simulation and Measurement Result
3.3.2 Chip Implementation
Fig 3.5 shows the microphotograph of the Darlington pair LNA circuit. The circuit is fabricated in the TSMC 0.18um CMOS technology. The die area including bonding pads is 0.89 mm by 0.87 mm. Careful layout is observed in order to maximize performance. The layout is done in a uni-directional fashion, i.e. no signal returns close to it origins, to avoid coupling back to the input. The RF input and output ports are placed on opposite sides of the chip to improve port-to-port isolation. Since on-chip probing is used to measure the LNA’s performance, standard Ground-Signal-Ground (GSG) configuration is used at both the input and output RF ports. In order to minimize the effect of substrate noise on the system, a solid ground plane, constructed using a low resistive metal-1 material, is placed between the signal pads (metal-6 and metal-5) and the substrate. Also, since the operation of inductors involves magnetic fields, they can affect nearby signals and circuits, and cause interference. Therefore, inductors are placed far apart from each other, as well as from the main circuit components, with reasonable distances. Furthermore, many ground connections to substrate are located near all inductors to reduce substrate noise.
3.3.3 Simulation and Measurement Result
Measured S-parameters are plotted in Fig. 3.6, 3.7 and 3.8, together with simulation results for comparison. The circle plot is the simulation result by using inductor model provided by the TSMC model file, and the triangle plot is the one by using inductor together with passive interconnection analyzed by the electromagnetic simulation tool of Agilent MOMENTUM. The solid line is the measured data. The measured power gain achieves the maximum value of 15.5dB at 6GHz, and input return ratio reaches -19dB at 6.2 GHz. The measured data drift to higher frequency may be due to the inaccurate inductor modeling, and all the S-parameter show the consistent trend. The square plot is the MOMENTUM
1 2 3 4 5 6 7 8 9
0 10
-20 -10 0 10
-30 20
-60 -40 -20 0 20
-80 40
S21[dB] S12[dB]
simulation with CITI file measure result
Momentum + variation simulation with Momentum
simulation minus ten percent of inductance of every inductor for trouble shotting. After trouble shotting, the simulated curve agree well to the measured date. Thus, we attribute the drift to that the realistic inductance of the inductor is smaller than the inductor modeling. Fig 3.9 shows the minimum noise figure is 3.5dB at 5.8GHz. Also, Linearity analysis is conducted by the two-tone test. Measured at 6 GHz, the two-tone test results of the third-order inter-modulation distortion are plotted in Fig. 3.10. The IIP3 is -6dBm and the 1-dB compression point -15dBm. The total power of the LNA circuit dissipates 11mW with a power supply 1.8V. TABLE I summarizes the performance of the Darlington pair LNA and comparison with general inductive source degeneration topology simulated by TSMC 0.18um CMOS model.
Fig 3.6 Simulation and measured result of power gain (S21) and isolation (S12) Frequency [GHz]
2 3 4 5 6 7 8 9
1 10
-20 -10
-30 0
simulation with CITI file measure result
Momentum + variation
simulation with Momentum
2 3 4 5 6 7 8 9
1 10
-20 -10
-30 0
simulation with CITI file measure result
Momentum + variation
simulation with Momentum
Fig 3.7 Simulation and measured result of input match
Fig 3.8 Simulation and measured result of output match Frequency [GHz]
Frequency [GHz]
S22 [dB] S11 [dB]
-30 -20 -10
-40 0
-50 0
-100 50
input power[dBm]
output power[dBm]
IIP3=-6dBm
2 4 6 8 10
0 12
2 4 6 8
0 10
noise figure[dB]
simulation with CITI file measure result
Momentum + variation
simulation with momentum only *
Fig 3.9 Simulation and measured result of noise figure
Fig 3.10 Measured result of two-tone test at 5 GHz Frequency [GHz]
TABLE I Summary of simulation and measured result of Darlington pair LNA and comparison with single input MOS
Circuit ISD architecture Darlington pair (Sim.) Darlington pair(Meas.)
S11 -11(dB) -28(dB) -20(dB)
S22 -29(dB) -35(dB) -24(dB)
S21 14(dB) 18.6(dB) 15.5(dB)
S12 -28(dB) -29(dB) -21(dB)
NF 2.5(dB) 2.7(dB) 3.5(dB)
1dB -14(dBm) -20(dBm) -15(dBm)
IIP3 -4(dBm) -9(dBm) -6(dBm)
Power 10(mW) 11(mW) 13(mW)
3.4 Conclusion
A narrow band high gain low noise amplifier using Darlington pair structure is analyzed and designed for wireless local network area (WLNA) operating at 5.5 GHz frequency band. We employ the double cutoff frequency property of Darlington pair to achieve high gain design.
Measured data show that the amplifier achieves maximum power gain (S21) of 15.5 dB, -10 dB input return loss (S11), and minimal noise figure of 3.5dB on the 5.8GHz frequency while consuming 13mW.
CHAPTER 4
A 3 to 8GHz Ultra-Wideband CMOS LNA
4.1 Introduction
As the demand for broadband data communication increases, the ultra-wideband (UWB) system is an emerging wireless technology for transmitting high-speed digital data over a wide spectrum of frequency bands at a very low power level. The low noise amplifier (LNA) in the receiver path of the UWB system critically determines several system parameters. The amplifier must hold flat gain, minimum noise figure, broadband input impedance matching, and good linearity, over the entire frequency band. In recent years, distributed amplifiers (DAs) were widely used to realize broadband amplifier [6-8]. The architecture is generally large in size because of many on-chip inductors, and consumes a high power level owing to several stages cascaded to derive an adequate gain level. An interesting approach employs a band-pass filter as the broadband impedance matching network, and the technique of gain peaking to derive flat gain [11]. In doing so, an additional capacitor is required to be placed in parallel to the gate-source of the input device for the filter design, which results in lower cut-off frequency (ωt) and available gain.
In this chapter, an LNA suitable for ultra-wideband system is designed in a standard 0.18um CMOS process. With the techniques of negative feedback and gain compensation, this LNA circuit achieves the broadband requirement in low power consumption.
4.2 Principle of the circuit design
4.2.1 Ultra-Wideband LNA Circuit Topology
The schematic of the LNA circuit is shown in Fig.4.1. The circuit includes three stages of the common-source input stage m1 for input trans-conductance, the common-gate inter-stage m2 for less Miller’s effect and better reverse isolation, and the common-source buffer stage m3 as the output buffer. The resistors Rf and Rf1 not only provide negative feedback but also self-biasing.
Circuit performance can be analyzed by the small signal equivalent circuit as shown in Fig4.2. The shunt elements, Zfm, Rfm1 and Rfm2, represent the Miller’s effect for Rf and Rf1. Note that we neglect the Miller impedance produced by Rf at the drain node of m1 since the input impedance of the common-gate stage is typically low. The overlap capacitance Cgd is ignored without loss of generality. The DC block capacitor Cpass is also neglected. Detail analysis is described as in the following.
Fig.4.1 Schematic of Ultra Wide-band LNA
⎟ ⎟
Fig.4.2 Small signal analysis of ultra wide band LNA 4.2.2 Broadband Input Matching
The configuration of inductive source degeneration would only provide narrow-band impedance matching to 50Ω [3]. The main advantage of the inductive source degeneration matching is on the high input trans-conductance at resonant frequency of the matching network. The detailed analysis of the input trans-conductance is shown in the following section 4.2.3. To preserve the advantage, the technique of resistive negative feedback is therefore employed to extend the frequency band of the matching network [8]. Thus, the matching network of the LNA is the combination of resistive negative feedback and inductive source degeneration matching network.
From small signal analysis in Fig.4.2, The input impedance can be derived as
(4-1)
where Zfm is the miller impedance of the feedback resistor Rf and Av0(s) is the voltage gain from Vin to Vsg2. For the case at very low frequencies, Zin1 is close to an open-circuit due to the gate capacitance Cgs1, and the input impedance is
(4-2) a resistive level determined by the feedback resistor (Rf) as well as the trans-conductance of transistors m1 and m2. On the Smith chart as shown in Fig.4.6, we place the Zin(ω~0) at point
Ls
Ls C 1gs
g 1m Ls
C 1gs g 1m Zfm
01) (
Zinω=ω ≈ ≈
I, which is a resistive value higher than 50(Ω). For the case at the resonant frequency (ω01), Zin1 is a low resistive value (ωtLs) compared to Zfm, thus the total input impedance Zin is approximately equal to Zin1:
(4-3) The Zin (ω=ω01) which is approximately a resistive value lower than 50(Ω) were placed around Point in Fig.Ⅱ 4.6. Since these two levels Zin(0) and Zin(ω01) give the impedance range as the frequency sweeps, adjusting both levels near 50Ω shall ensure good S11 over the entire frequency band. Similarly output impedance matching is realized by the parallel connection of Rfm2 and Rd, as shown in Fig.4.2.
4.2.3 Gain flatness technique
Gain flatness is realized by gain compensation among the three stages. Under the condition of impedance match, available power gain shall be the same as the voltage gain. From the model in Fig.4.2, the overall voltage gain can be expressed as
Fig.4.3 Illustration of signal amplification
(4-5) where Gm is the trans-conductance of the input stage, β is the current gain of the inter-stage, and Zm is the transfer function of the buffer stage.
Although the frequency response of each stage appears as narrow-band tuned, the composite response can achieve broadband gain flatness with appropriate design. An inter-stage matching inductor Ld1 is inserted in the cascoded configuration to enhance the gain level at high frequencies [12]. As illustrated in Fig.4.3, the frequency responses of the first two stages are tuned with peaking around 8-GHz, while that of the third stage around 3-GHz. As a result, the frequency response of the cascaded circuit yields to broadband gain flatness.
The trans-conductance Gm of the input stage can be derived as
(4-6)
where
the response which is a second low pass filter reaches for a maximum at the resonant frequency (ω01). In this work the resonant frequency is set to be around the frequency of 8GHz, and the value of Q1 is chosen to broaden the bandwidth. The frequency response of the Gm is shown in Fig.4.3 (a). Note that, the larger the Q1, the higher the trans-conductance (Gm) in our operating frequency band. Under matching issue from above section mentioned in (4-3), the Ls is chosen lower than general inductive source degeneration narrow band LNA, which gives matching input impedance to 50(Ω) at resonant frequency. Thus, we can derive higher Q1 as well as Gm
in the frequency band from 3 to 8 GHz.
gate-source capacitance (Cgs2) of m2. Together they are considered as a part of the inter-stage.
The transfer function of current gain β is
(4-7)
With the inductor Ld1, the response at the frequency of 8-GHz is further boosted, as shown in Fig.4.3 (b).
The trans-impedance Zm of the buffer stage is required to compensate for the roll-off generated by the overall trans-conductance of the first two stage, Gm*β. The transfer function of Zm is derived as
(4-8)
where
The inductor Ld2 is tuned to resonate with the gate-drain capacitance (Cgd2) and the gate-source capacitance (Cgs3) at the frequency of 3GHz. The response is shown in Fig.4.3(c).
The cascaded circuit can achieve a flat voltage gain over the entire frequency band, as shown in Fig.4.3 (d).
4.2.4 Design Considerations and Trade off
The resistance of Rf shall be designed appropriately for impedance matching. The resistance, however, shall be large to minimize noise performance degradation. From simulation the value is chosen as 200Ω.
High trans-conductance in the input stage yields to good noise performance. Since the
gm2
trans-conductance of the input stage appears as narrow-band tuned, noise performance of the designed circuit is better near the in-band high frequency of 8-GHz. In addition, tuning at higher frequency calls for a smaller gate inductance Lg. Consequently the parasitic resistance is smaller in practice, and the degradation to noise performance is minimized. Simulation shows the minimum noise figure is 4.5 dB around 8GHz, and the maximum value is 6 dB around 3-GHz.
To meet the requirement of Zm, the value of the inductor Ld2 is chosen around 6 nH. The self resonant frequency of this inductor must be high above the frequency range for broadband operation. On the other hand, use of a low-Q inductor is acceptable as far as the broadband application is concerned. Thus, the metal width of 8um, narrower than the typically size in the design kit, is actually applied to this design to reduce parasitic capacitance and the occupied area. All of the inductors and interconnects are analyzed by the electromagnetic simulation tool of Agilent MOMENTUM. Circuit performance is analyzed together with the simulated S-parameters of the passives.
4.3 Chip Implementation and Measured Result
4.3.1 Microphotograph of Chip
A microphotograph of the LNA circuit is shown in Fig.4.4. The circuit is fabricated in the TSMC 0.18um CMOS technology. The die area including bonding pads is 0.81 mm by 0.8 mm. As can be seen, the size of Ld2 is approximately the same as that of the inductor Lg
(~1.2nH and metal width =15um).
Fig.4.4 Microphotograph of the UWB LNA circuit 4.3.2 Measurement and Simulation Result
Measurement is conducted by on-wafer RF probing. Measured S-parameters are plotted in Fig.4.5 and Fig.4.6, together with simulation results with and without trouble shotting for comparison. The measured power gain achieves the maximum value of 9.2 dB at 3GHz and degrades to 6.3 dB at 8GHz. It agrees well with the simulated data below 6GHz. Above 6GHz, the measured power gain start to decrease and deviate from the simulation result. There is a difference of 1.5dB at 8GHz and the 3dB-bandwidth is 2-to-8.2GHz. From the gain flatness technique, the inductive source degeneration structure was employed to provide enough trans-conductance gain to suppress noise figure of in band high frequency. The lower the trans-conductance gain of input stage, the lower S21 and higher noise figure would result.
Hence, the discrepancy between measured data and simulation result on the S21 may be due to Ld2
Lg Ld1
Ls
G
S
G
G
G S
P G P
the lower trans-conductance of input stage in the implemented circuit. From (3-1), we have known the cutoff frequency of input stage transistor m1 ( ) determines the input trans-conductance, a capacitor (C=0.08pF) is included between the gate and source node of the transistor m1 to reduce the input trans-conductance for trouble shooting. Note that, because the measured power consumption and biasing are roughly equal to the simulation result, we consider the intrinsic trans-conductance of transistor m1 (gm1) doesn’t change compared to simulation result. In Figure 4.5, the square plot shows the S21 result after adding the capacitor C, it agrees well with the measured result. On the other hand, the measured S11 is worse than -10dB above 5.5 GHz, while the S22 achieves excellent performance due to resistive matching.
It can be observed that the input impedance deviates from 50Ω at high frequencies on the Smith chart, the discrepancy may be due to unexpected parasitic capacitance that has not been included in the transistor model or resulted from process variation. We added parasitic capacitance (C1=0.1 pF and C2=0.4 pF) between ground and source node of transistor m1 and m2 respectively. We consider the parasitic capacitance mainly result from the PN junction capacitor between Deep n well and P-substrate. Note that, this parasitic effect has not been included in the device model provided by TSMC. The square plot of Figure 4.6 shows the conjecture agrees well with the measured result.
Fig.4.7 shows the noise figure, which is with an average value of 6.1 dB and minimum value of 5.65 dB at 7.5 GHz. Measured data agree with simulated data below 6GHz.
Discrepancy at high frequencies may be due to degradation of S21 and inaccurate noise model.
Linearity analysis is conducted by the two-tone test. Measured at 5 GHz, the two-tone test results of the third-order inter-modulation distortion are plotted in Fig.4.8. The IIP3 is -3.1dBm and the 1-dB compression point -19dBm. The total power of the LNA circuit dissipates 15mW with a power supply 1.5V. The comparison of wideband LNA between previously published work and this work is summarized in TABLE .Ⅱ
gs m T =g /C ω
Fig.4.5 Simulation and measured result of power gain (S21) and isolation (S12)
Fig.4.6 Simulation and measured result of input match and output match
1 2 3 4 5 6 7 8 9 10 11
0 12
-5 0 5 10
-10 15
-50 -40 -30 -20 -10
-60 0
Frequency[GHz]
S21[dB] S12[dB]
simulation result
measure result simulation result after trouble shotting
2 3 4 5 6 7 8 9 10 11
1 12
-40 -30 -20 -10
-50 0
-30 -20 -10
-40 0
Frequency[GHz]
S11[dB] S22[dB]
simulation result S11 measure result
simulation result after trouble shotting
ω=ω01
ω=0
Fig.4.7 Simulation and measured result of noise figure
Fig.4.8.Measured result of two-tone test at 5 GHz; Measured IIP3 versus frequency
4 5 6 7 8 9 10
3 11
4 6 8
2
10
simulation result
measure result
simulation result after trouble shotting
-35 -30 -25 -20 -15 -10 -5
-40 0
-100 -80 -60 -40 -20 0
-120 20
Source power [dBm)
Output Power (dBm)
IIP3= -3.1dBm
4 5 6 7
3 8
-4.0 -3.5 -3.0
-4.5 -2.5
freq, GHz
IIP3[dBm]
Noise Figure [dB]
Frequency [GHz]
TABLE Ⅱ. Summary of measured result and performance comparison to other wideband amplifier.
BW† [dB] Gmax [dB] S11 [dB] NFmin [dB] IIP3 [dBm] Area [mm2] Pw [mW]
* 2-2.8 9.2 < -5.8 5.65 -3.1 0.65 15
[11] 2.9-9.2 9.3 <-9.9 4 -6.7 1.1 18‡
[6] 0.6-22 8.1 <-8 4.3 N/A 1.35 52
[7] 0.5-4 7.4 <-7 5.4 N/A 1.12 83.4
[8] 1.5-7.5 7 <-6 8.7 N/A 3.67 216
==================================================================================================
*this work †-3dB bandwidth ‡total circuit power
==================================================================================================
4.4 Improved UWB LNA
From previous UWB LNA design, measured data show some deviation from simulation result at high frequency. It can be observed from the S11 on the Smith chart that unexpected parasitic occur such that the response is far from 50-Ω at high frequencies above 6GHz. The S21 degradation at high frequency may be due to low trans-conductance of input stage. Noise figure also show consistent trend as result of the degradation S21. To solve these problems, a modified UWB LNA circuit as shown in Fig.4.9 is introduced. The matching network is modified to achieve good input matching at high frequency and higher trans-conductance of the input stage by adding Lg1 and Cp. Output buffer stage is transformed to a common drain stage to reduce the complexity of the previous resistive feedback common source stage. Also, a broadband variable gain function is added by tuning the RC network between second and third stage.
Fig.4.9 Schematic of the modified UWB LNA 4.4.1 wide-band input matching
From previous UWB LNA design, we combined the resistive feedback resistor and inductive source degeneration to achieve input matching in-band. The measured results show some parasitic effect at high frequency, hence the S11 deviate from the simulation result. Also, to increase the trans-conductance of the first stage, the Q1 of the equation (4-6) should be increased. The only way to increase the Q1 without increasing DC power is to decrease the source degeneration inductance Ls. From equation (4-3), the input impedance Zin will be much far from 50Ω, this will worsen the input return loss. To overcome the awkward situation, the input matching network is modified to remedy the poor input return loss at high frequency. An L-section matching network (Lg1 and Cp) is added to our previous one as shown in Fig.4.10.
Fig.4.10 Modified input matching network to improve S11 at high frequency in band
The S11” is the previous input matching network. The only difference is that the Ls were decreased to increase the Q1 of input trans-conductance. From the Smith chart, the resonant frequency point is far from the 50Ω. Our goal is to provide good input matching between 3 and 8 GHz. The Lg1 is added to shift the S11” to inductive direction. The S11’ shows the input return loss after adding Lg1. Finally, the inductive part is compensated by the parallel capacitance (Cp), the S11 shows the input return loss of the overall input matching network. From the matching network, we not only remedy the degradation of the input return loss at high frequency to within -10dB, but also increase the input trans-conductance.
Fig.4.11 Using mutual inductance to reduce spiral inductor area
Taking the chip area into consideration, the input matching network which has two inductors Lg1 and Lg will require larger die area to implement the two spiral inductors. A
Lg
Ls
Zfm
Cgs
Lg1
C
p
S11”
S11 S11’
8GHz
50Ω
-10dB S11”
S11 S11’
L-section network 0Hz
Lg1 Vin1 Lg
Gate(m1)
Rf (high impedance => i1~i2)
i1 i2
M Vin
Vin1 Lg1’ Lg’
Gate(m1)
i1 i2 Rf
(a) (b) (c)
transformer-like inductor shown in Fig.4.11(c) is implemented to reduce die size. From simulation result, the inductance value of the two uncoupled inductors (Lg1’ and Lg’) require 0.6 (nH) and 0.9 (nH) respectively, as shown in Fig.4.11(a). Taking the coupling effect of the two inductors into consideration as shown in Fig.4.11(b), if the impedance seeing into the resistive feedback resistor is high enough compared to the inductive source degeneration impedance Zin1 (Fig.4.2) , the i1 ~i2 holds. As a result, we can derive
(4-9 )
The mutual inductance M not only reduce the separate inductor value that we require but also can help to integrate the two inductors into one inductor with a tapping connected to Rf. Fig.4.11(c) shows layout of the transformer-like inductor. And the simulation result is shown in Fig.4.12.
Fig.4.12 Simulation result of the transformer-like spiral inductor
Fig.4.12 Simulation result of the transformer-like spiral inductor