Chapter 2 Low Noise Amplifier Basic Concepts
2.2 Low Noise Amplifier Basic
2.2.3 Introduction to Broadband LNA
Ultra wideband (UWB) systems are a newly wireless technology capable of transmitting data over a wide spectrum of frequency bands with very low power and high data rates.
Although the UWB standard (IEEE 802.15.3a [5]) has not been completely defined, most of the proposed applications are allowed to transmit in a band between 3.1 and 10.6 GHz. How to design a low noise amplifier suitable for the receiver path of the UWB system becomes a challenge for RF circuit designer. In general, this type of amplifier would have constant gain and good input matching over the desired frequency bandwidth, and provide low enough noise figure while consuming power as little as possible.
With recent advances in RF integrated circuit and device processing technology,
Lg Lg Lg Lg
Ld Ld Ld Ld
Zg
Zd
Input
Output
Fig.2.7 Configuration of an N-stage distributed amplifier
distributed amplifiers (DAs) were widely used to realize broadband amplifier [6-8]. The basic configuration of DAs is shown in Fig 2.7. A cascade of N identical FETs have their gates connected to a series inductors, Lg , while the drains are connected to a series inductors, Ld. The combination of gate-source capacitance(Cgs) of each device and the series inductors, Lg, forms a approximate transmission line with characteristic impedance Zg’ ( L /g Cgs ) equal to Zg. If the Zg is equal to 50Ω, the approximate transmission line will give good input matching to 50Ω. In the same way, the output matching will be achieved. In amplification aspect, the input signal propagates down the gate line, with each FET tapping off some of the input power. The output signals amplified by the trans-conductance of FETs form a traveling wave on the drain line. The inductors (Ld’s) are chosen for constructive phasing of the output signals, and the termination impedances on the lines serve to absorb waves traveling in the reverse directions [9].
In CMOS technology, Bandwidths extending to tens of giga-hertz of DAs are possible, with good input and output matching. Distributed amplifiers can not achieve very high gains or very low noise figure, however, and generally are larger in size because of many on-chip inductors. The main drawback on the DAs is that power consumption is generally large owing to several stages cascaded to derive an adequate gain level. Also, the bandwidth of the DAs basically is a low pass filter, whose excess amplification below 3.1 GHz would distort the wanted signal for ultra-wideband application.
An alternative approach to the design of broadband amplifiers is to use negative feedback [10]. One particularly useful broadband circuit that employs negative feedback is the shunt-series amplifier as shown in Fig 2.8. With the assistance of negative feedback resistor, the Rin and Rout can be matched to 50 easily in low frequency. Formally, Rin and Rout is given by
Rs
Comparing the expressions for input and output resistance, we see that if Rs and RL are equal (as is commonly the case) then Rin and Rout will also be precisely equal. This happy coincidence is one reason for the tremendous popularity of this topology. Unfortunately, the presence of gate-source capacitance, Cgs , and Miller-augmented gate-drain capacitance, Cgd , which appear between gate and ground, makes it impossible to achieve perfect input impedance matching at high frequency. These effects can be mitigated to a certain extent by using L-match network to transform the resistive part up to the desired level. Of the possible types of L-matches, the best choice is usually one that places an inductance in series with the gate and a shunt capacitance across the amplifier input; such a network becomes transparent at low frequencies, where no correction is required. After some assumption and calculation, we can derive the relationship between voltage and bandwidth:
1
This topology trades gain for bandwidth, so amplifier bandwidths in excess multi-gigahertz using CMOS technology are possible at the expense of gain and noise figure.
From previous discussion, we found that a broad band amplifier generally suffers from two problems: low gain and power hungry. The first problem would degrade noise performance on the following stage in the receiver path, and the second one would not be
Fig.2.8 Configuration of shunt-series amplifier
suitable for general portable device. In section 2.2.2, we have known that inductive source degeneration architecture possess near-optimum noise performance [3], and high gain potential in term of cutoff frequency of input MOS device, while dissipating less power than broad band amplifier. In Chapter 4, we will utilize these advantages of inductive source degeneration combined with the resistive feedback technique to design a wideband amplifier suitable for the UWB system.
CHAPTER 3
5.5 GHz High Gain LNA Using Darlington Pair
3.1 Motivation
We have introduced the inductive source degeneration topology to design LNA in section 2.2.2. From (2-11) and (2-17), we found that the cutoff frequency of the input device determines the gain and noise performance of the inductive source degeneration LNA. As CMOS process technology continues to improve, the higher gain and lower noise performance may be expected. Now, device cutoff frequency, fT , is bounded within any given technology, so it would seem that once biasing conditions that maximize fT have been established, the designer has done all that can be done. However this facile conclusion overlooks the possibility of topological routes to increasing fT. In this chapter, an alternative inductive source degeneration LNA using Darlington pair input stage to increase fT is analyzed and implemented.
3.2 Analysis of Darlington Pair LNA Topology
3.2.1 Design principle
In section 2.2.2, we have derived the trans-conductance of an inductive source degeneration LNA input stage as shown in (2-11). Now, we rewrite and reconsider this equation.
(3-1) we can reformulate this equation as
(3-2)
Zin 1
Lg
2
Lg
m1
m2
m3
Ld
Cs
Cp
Cpass
output
input
Rl
Z1
of the input device and inverse proportional to the frequency of operation, and the Zin is the input impedance of the input stage. Eq.(3-2) stands for the trans-conductance of the input stage is proportional to the current gain itself at the operating frequency under input matching condition. In other words, the input stage acts as a current amplifier at the frequency of operation. If we can increase the current gain of the input stage without changing the input matching condition, we will get larger trans-conductance to derive more gain and suppress noise of the subsequent stage at the operating frequency.
Fig 3.1 Schematic of Darlington pair low noise amplifier
3.2.2 Analysis and Design of the LNA using Darlington Pair
Because Darlington pair has approximate double cutoff frequency [10], it means that Darlington pair has larger current gain. Now, the Darlington pair topology has been employed to replace the input stage of our designed LNA circuit as shown in Fig 3.1. The Lg1 and Lg2
are designed to achieve input matching, and cascode common-gate device m2 for less Miller’s effect and better reverse isolation. The resistor, Rl, is designed for biasing. Because the value of Rl is large enough compared to Z1 at operating frequency, the bias resistor would not affect the normal operation of the Darlington Pair. Also, Ld1, Cs and Cp are designed for output matching, while Cpass for local small signal ground.
3.2.2.1 Trans-conductance in Darlington Pair Stage
To analyze the trans-conductance of input stage, we neglect the contribution of subsequent stages and the overlap capacitance Cgd. The use of a cascoded first stage helps to ensure that this approximation will not introduce serious errors. After some small signal calculation, the trans-conductance of the Darlington pair at operating frequency gives
s we have assumed input impedance matching to Rs.
To compare the trans-conductance of the Darlington pair and a single device, (3-1) and (3-3) were combined as
where the M means the profit using Darlington pair compared to single device.
To gain more insight of the profit, we consider the following case. If we roughly assumed that ωT ∝ PD and
where we have assumed the frequency of operation is 5 GHz, and the cutoff frequency (ωT) is 30 GHz, a typical value in 0.18um CMOS process. More detailed will be simulated in Section 3.3.1.
3.2.2.2 Input impedance matching
The configuration of inductive source degeneration topology provides impedance matching to 50Ω with the help of source inductor (Ls). To derive input matching to 50Ω in the Darlington pair topology, an inductor Lg2 is inserted between the source of the device m1 and the gate of the device m2 as shown in Fig 3.1. A portion of Lg2 (Lt) is designed to tune out the gate-source capacitance of device m2, while the remainder serves as the inductive source degeneration inductor (eq. Ls) of device m1 for input matching. The analysis is shown as follows
3.3 Discussion on Simulation and Measurement Result
3.3.1 Verification of Equation (3-4)
The 0.18um RF CMOS model provided by the TSMC is employed to simulate and verify the validity of equation (3-4). Here, we have assumed the drain current of device m1 and m2 are one half of that of the single device. In other words, the total current consumed by Darlington pair is equal to that of a single device. Now, we find out the cutoff frequency of every device (m1, m2 and M1) under the specified bais condition, the result is shown in Fig 3.2.
Finally, we substitute the cutoff frequency for the (3-4), and compared it to the simulated result, as shown in Fig 3.3. The calculation result of (3-4) agrees well with the simulated result. Thus, the validity of (3-4) is verified. Also, we find under the same current consumption the trans-conductance of Darlington pair is 1.5 to 6 times larger than a single device. This means, we can use the Darlington pair to derive larger trans-conductance without dissipating too much power compared to a single device.
In previous verification, we have assumed the output load of the input stage is zero.
Unfortunately, the cascoded stage still hold low input impedance, this would degrade the trans-conductance of the input stage due to Miller effect. Because the Darlington pair has larger trans-conductance, it would result in larger voltage gain from output to the input compared to the single device under the same cascoded input impedance. In Fig 3.4, we saw the trans-conductance degradation of Darlington pair is larger than that of single device due to Miller effect. Here, we have assumed the cascoded stage is an ideal current buffer with a low impedance 20Ω (a typical value of 0.18um NMOS) and the output of the cascoded stage has been matched to 50Ω.
Fig 3.2 Cutoff frequency of device m1, m2 and M1 versus drain current
Fig 3.3 Profit (M) versus total current of input stage
Fig 3.4 Influence of miller effect on the S21
Fig 3.5 Microphotograph of the Darlington pair LNA circuit
3.3.2 Chip Implementation
Fig 3.5 shows the microphotograph of the Darlington pair LNA circuit. The circuit is fabricated in the TSMC 0.18um CMOS technology. The die area including bonding pads is 0.89 mm by 0.87 mm. Careful layout is observed in order to maximize performance. The layout is done in a uni-directional fashion, i.e. no signal returns close to it origins, to avoid coupling back to the input. The RF input and output ports are placed on opposite sides of the chip to improve port-to-port isolation. Since on-chip probing is used to measure the LNA’s performance, standard Ground-Signal-Ground (GSG) configuration is used at both the input and output RF ports. In order to minimize the effect of substrate noise on the system, a solid ground plane, constructed using a low resistive metal-1 material, is placed between the signal pads (metal-6 and metal-5) and the substrate. Also, since the operation of inductors involves magnetic fields, they can affect nearby signals and circuits, and cause interference. Therefore, inductors are placed far apart from each other, as well as from the main circuit components, with reasonable distances. Furthermore, many ground connections to substrate are located near all inductors to reduce substrate noise.
3.3.3 Simulation and Measurement Result
Measured S-parameters are plotted in Fig. 3.6, 3.7 and 3.8, together with simulation results for comparison. The circle plot is the simulation result by using inductor model provided by the TSMC model file, and the triangle plot is the one by using inductor together with passive interconnection analyzed by the electromagnetic simulation tool of Agilent MOMENTUM. The solid line is the measured data. The measured power gain achieves the maximum value of 15.5dB at 6GHz, and input return ratio reaches -19dB at 6.2 GHz. The measured data drift to higher frequency may be due to the inaccurate inductor modeling, and all the S-parameter show the consistent trend. The square plot is the MOMENTUM
1 2 3 4 5 6 7 8 9
0 10
-20 -10 0 10
-30 20
-60 -40 -20 0 20
-80 40
S21[dB] S12[dB]
simulation with CITI file measure result
Momentum + variation simulation with Momentum
simulation minus ten percent of inductance of every inductor for trouble shotting. After trouble shotting, the simulated curve agree well to the measured date. Thus, we attribute the drift to that the realistic inductance of the inductor is smaller than the inductor modeling. Fig 3.9 shows the minimum noise figure is 3.5dB at 5.8GHz. Also, Linearity analysis is conducted by the two-tone test. Measured at 6 GHz, the two-tone test results of the third-order inter-modulation distortion are plotted in Fig. 3.10. The IIP3 is -6dBm and the 1-dB compression point -15dBm. The total power of the LNA circuit dissipates 11mW with a power supply 1.8V. TABLE I summarizes the performance of the Darlington pair LNA and comparison with general inductive source degeneration topology simulated by TSMC 0.18um CMOS model.
Fig 3.6 Simulation and measured result of power gain (S21) and isolation (S12) Frequency [GHz]
2 3 4 5 6 7 8 9
1 10
-20 -10
-30 0
simulation with CITI file measure result
Momentum + variation
simulation with Momentum
2 3 4 5 6 7 8 9
1 10
-20 -10
-30 0
simulation with CITI file measure result
Momentum + variation
simulation with Momentum
Fig 3.7 Simulation and measured result of input match
Fig 3.8 Simulation and measured result of output match Frequency [GHz]
Frequency [GHz]
S22 [dB] S11 [dB]
-30 -20 -10
-40 0
-50 0
-100 50
input power[dBm]
output power[dBm]
IIP3=-6dBm
2 4 6 8 10
0 12
2 4 6 8
0 10
noise figure[dB]
simulation with CITI file measure result
Momentum + variation
simulation with momentum only *
Fig 3.9 Simulation and measured result of noise figure
Fig 3.10 Measured result of two-tone test at 5 GHz Frequency [GHz]
TABLE I Summary of simulation and measured result of Darlington pair LNA and comparison with single input MOS
Circuit ISD architecture Darlington pair (Sim.) Darlington pair(Meas.)
S11 -11(dB) -28(dB) -20(dB)
S22 -29(dB) -35(dB) -24(dB)
S21 14(dB) 18.6(dB) 15.5(dB)
S12 -28(dB) -29(dB) -21(dB)
NF 2.5(dB) 2.7(dB) 3.5(dB)
1dB -14(dBm) -20(dBm) -15(dBm)
IIP3 -4(dBm) -9(dBm) -6(dBm)
Power 10(mW) 11(mW) 13(mW)
3.4 Conclusion
A narrow band high gain low noise amplifier using Darlington pair structure is analyzed and designed for wireless local network area (WLNA) operating at 5.5 GHz frequency band. We employ the double cutoff frequency property of Darlington pair to achieve high gain design.
Measured data show that the amplifier achieves maximum power gain (S21) of 15.5 dB, -10 dB input return loss (S11), and minimal noise figure of 3.5dB on the 5.8GHz frequency while consuming 13mW.
CHAPTER 4
A 3 to 8GHz Ultra-Wideband CMOS LNA
4.1 Introduction
As the demand for broadband data communication increases, the ultra-wideband (UWB) system is an emerging wireless technology for transmitting high-speed digital data over a wide spectrum of frequency bands at a very low power level. The low noise amplifier (LNA) in the receiver path of the UWB system critically determines several system parameters. The amplifier must hold flat gain, minimum noise figure, broadband input impedance matching, and good linearity, over the entire frequency band. In recent years, distributed amplifiers (DAs) were widely used to realize broadband amplifier [6-8]. The architecture is generally large in size because of many on-chip inductors, and consumes a high power level owing to several stages cascaded to derive an adequate gain level. An interesting approach employs a band-pass filter as the broadband impedance matching network, and the technique of gain peaking to derive flat gain [11]. In doing so, an additional capacitor is required to be placed in parallel to the gate-source of the input device for the filter design, which results in lower cut-off frequency (ωt) and available gain.
In this chapter, an LNA suitable for ultra-wideband system is designed in a standard 0.18um CMOS process. With the techniques of negative feedback and gain compensation, this LNA circuit achieves the broadband requirement in low power consumption.
4.2 Principle of the circuit design
4.2.1 Ultra-Wideband LNA Circuit Topology
The schematic of the LNA circuit is shown in Fig.4.1. The circuit includes three stages of the common-source input stage m1 for input trans-conductance, the common-gate inter-stage m2 for less Miller’s effect and better reverse isolation, and the common-source buffer stage m3 as the output buffer. The resistors Rf and Rf1 not only provide negative feedback but also self-biasing.
Circuit performance can be analyzed by the small signal equivalent circuit as shown in Fig4.2. The shunt elements, Zfm, Rfm1 and Rfm2, represent the Miller’s effect for Rf and Rf1. Note that we neglect the Miller impedance produced by Rf at the drain node of m1 since the input impedance of the common-gate stage is typically low. The overlap capacitance Cgd is ignored without loss of generality. The DC block capacitor Cpass is also neglected. Detail analysis is described as in the following.
Fig.4.1 Schematic of Ultra Wide-band LNA
⎟ ⎟
Fig.4.2 Small signal analysis of ultra wide band LNA 4.2.2 Broadband Input Matching
The configuration of inductive source degeneration would only provide narrow-band impedance matching to 50Ω [3]. The main advantage of the inductive source degeneration matching is on the high input trans-conductance at resonant frequency of the matching network. The detailed analysis of the input trans-conductance is shown in the following section 4.2.3. To preserve the advantage, the technique of resistive negative feedback is therefore employed to extend the frequency band of the matching network [8]. Thus, the matching network of the LNA is the combination of resistive negative feedback and inductive source degeneration matching network.
From small signal analysis in Fig.4.2, The input impedance can be derived as
(4-1)
where Zfm is the miller impedance of the feedback resistor Rf and Av0(s) is the voltage gain from Vin to Vsg2. For the case at very low frequencies, Zin1 is close to an open-circuit due to the gate capacitance Cgs1, and the input impedance is
(4-2) a resistive level determined by the feedback resistor (Rf) as well as the trans-conductance of transistors m1 and m2. On the Smith chart as shown in Fig.4.6, we place the Zin(ω~0) at point
Ls
Ls C 1gs
g 1m Ls
C 1gs g 1m Zfm
01) (
Zinω=ω ≈ ≈
I, which is a resistive value higher than 50(Ω). For the case at the resonant frequency (ω01), Zin1 is a low resistive value (ωtLs) compared to Zfm, thus the total input impedance Zin is approximately equal to Zin1:
(4-3) The Zin (ω=ω01) which is approximately a resistive value lower than 50(Ω) were placed around Point in Fig.Ⅱ 4.6. Since these two levels Zin(0) and Zin(ω01) give the impedance range as the frequency sweeps, adjusting both levels near 50Ω shall ensure good S11 over the entire frequency band. Similarly output impedance matching is realized by the parallel connection of Rfm2 and Rd, as shown in Fig.4.2.
4.2.3 Gain flatness technique
Gain flatness is realized by gain compensation among the three stages. Under the condition of impedance match, available power gain shall be the same as the voltage gain. From the model in Fig.4.2, the overall voltage gain can be expressed as
Fig.4.3 Illustration of signal amplification
(4-5) where Gm is the trans-conductance of the input stage, β is the current gain of the inter-stage, and Zm is the transfer function of the buffer stage.
Although the frequency response of each stage appears as narrow-band tuned, the composite response can achieve broadband gain flatness with appropriate design. An inter-stage matching inductor Ld1 is inserted in the cascoded configuration to enhance the gain level at high frequencies [12]. As illustrated in Fig.4.3, the frequency responses of the first two stages are tuned with peaking around 8-GHz, while that of the third stage around 3-GHz. As a result, the frequency response of the cascaded circuit yields to broadband gain flatness.
The trans-conductance Gm of the input stage can be derived as
(4-6)
where
the response which is a second low pass filter reaches for a maximum at the resonant frequency (ω01). In this work the resonant frequency is set to be around the frequency of 8GHz, and the
the response which is a second low pass filter reaches for a maximum at the resonant frequency (ω01). In this work the resonant frequency is set to be around the frequency of 8GHz, and the