Thesis Organization - 應用於超寬頻系統之可調頻低雜訊放大器

Chapter 1 Introduction

1.3 Thesis Organization

This thesis discusses about the tunable LNA design and implementation for the UWB frequency hopping system.

In Chapter 2, fundamentals of conventional low noise amplifiers will be introduced. And theoretical MOSFET noise model and noise theory are presented.

In Chapter 3, an ultra-wideband tunable LNA is presented in section 3.2, and in section 3.3 the amended circuit is proposed to enhance the tunable range, and then the tunable LNA integrated with high Q MEMS inductors is discussed in section 3.4.

In Chapter 4, to conclude the tunable LNA design. In Chapter 5, the future work is described. Some issues that should be noted for future works on this topic are also summarize.

Chapter 2 The Fundamentals in LNA Design

Fundamentals of the low noise amplifier will be introduced. In section 2.1 illustrates the noise sources in MOSFET [3, 4]. The design basic of the low noise amplifier is discussed in section 2.2 [3, 4].

2.1 Noise in MOSFET

The noise performance of LNA is the first consideration because it represents a lower limit to the signal amplified by a circuit without significant deterioration in signal quality. The various sources of electronic noise are considered, and MOSFET’s noise model will be described here.

The noise process of thermal noise is random, and we would expect a dependence on the absolute temperature, T. It turns out that thermal noise power is exactly proportional to T. The every physical resistor has a noise source associated with thermal noise. The thermal noise can be represented by v² =4kTR f∆ or

2 =4 (1/ )∆

i kT R f , where k is Boltzmann’s constant and f∆ is the noise bandwidth in hertz.

Since MOSFETs are essentially voltage-controlled resistors, they exhibit thermal noise. Thus, detailed theoretical considerations lead to the following expression for the drain current noise of FETs:

d2 d0

i =4kT gγ ∆ ,f

(2-1) where gd0 is the drain-source conductance at zero VDS. The parameter γ has a value of unity at zero VDS and, in long devices, decreases toward a value of 2/3 in saturation.

Note that the drain current noise at zero VDS is precisely that of an ordinary conductance of value gd0. Unfortunately, γ is greater then 2/3 for short channel device, and thus the value will lead to worsen the noise performance as the technology proceeds.

Gate noise,i is another kind of thermal noise due to the thermal agitation of ^g² channel charge. The fluctuating channel potential couples capacitively into the gate terminal, leading to a noisy gate current. Although this noise is negligible at low frequencies, it can dominate at radio frequencies. The gate current noise may be expressed as

And δis the coefficient of gate noise, classically equal to 4/3 for long-channel devices while 4 to 6 in short channel one. The gate noise is partially correlated with the drain noise, with a correlation coefficient expressed as

The value of -0.395j is exact for long-channel devices. The correlation can be treated by expressing the gate noise as the sum of two components, the first of which is fully correlated with the drain noise, and the second of which is uncorrelated with the drain noise. Hence, the gate noise is re-expressed as

g2 2 2

g g

i =4kT g (1-|c| )+4kT g |c|

f δ δ

∆ . (2-4) Because of the correlation, special attention must be paid to the reference polarity of the correlated component.

Charge trapping leads to the flicker noise, which is a type of noise found in all active devices. These traps capture and release carriers in a random fashion and the time constants associated with the process give rise to a noise signal with energy concentrated at low frequencies. In electronic devices, 1/f noise (flicker noise) arises from a number of different mechanisms, and is most prominent in devices that are sensitive to surface phenomena. Charge trapping phenomena are usually invoked to explain 1/f noise in transistors. Some types of defects and certain impurities can randomly trap and release charge. The trapping times are distributed in a way that can lead to a 1/f noise spectrum in both MOS and bipolar transistors. Larger MOSFETs exhibit less 1/f noise because their larger gate capacitance smooth the fluctuation in the channel charge. Here, if good 1/f noise performance is to be obtained from MOSFETs, the largest practical device sizes must be used (for a given gm). The mean-square 1/f drain noise current is given by

2 2

n 2 T

K g K

i = f A f

f WLC⋅ ⋅ ∆ ≈ f ω ⋅ ⋅ ∆ , (2-5) where A (=WL) is the area of the gate and K is a device-specific constant. Thus, a larger dimension size and a thinner dielectric lead to small 1/f noise.

2.2 Low Noise Amplifiers Basic

To satisfy the targets of LNA design are minimizing the noise figure, providing gain with sufficient linearity and providing a stable 50Ω input impedance matching to terminate an unknown length of transmission line which delivers signal from the antenna to the amplifier. Several kinds of the LNA architectures are illustrated below.

The additional constraint of low power consumption and noise performance further complicate the design process.

2.2.1 Low Noise Amplifier Topology and Basic

Fig 2.1 Common LNA architectures. (a) Resistive termination (b) 1/gm termination (c) Shunt - series feedback (d) Inductive degeneration [3].

The four basic topologies of low noise amplifiers for 50 ohm input impedance matching are shown in Fig. 2.1. Fig. 2.1(a) uses 50Ω resistive termination of the input port to provide impedance matching. Unfortunately, the use of real resistors in this fashion has a deleterious effect on the amplifier’s noise figure. Fig. 2.1(b) uses a

common gate stage as the input termination. It’s also called 1/g^m termination architecture. Assuming matched conditions, yields the following lower bounds on noise factor for CMOS amplifiers:

γ 5

F=1+ =2.2dB

α ≥3 , where ^m

g α =g .

In CMOS expressions, γ is the coefficient of channel thermal noise, gm is the device transconductance, and gd0 is the zero bias drain conductance. For long channel devices, γ=2/3, α=1. But in short channel MOS devices, γ can be greater than one, and α can be much less than one. Accordingly, the minimum theoretically achievable noise figures tend to be around 3dB or greater in practice.

The third topology is shown in Fig. 2.1(c). This architecture uses resistive shunt and series feedback to set the input and output impedances of the LNA. Amplifiers using shunt-series feedback often have high power dissipation compared to others with similar noise performance. Intuitively, the higher power is partially due to the fact that shunt series amplifiers of this type are naturally broadband, and hence techniques which reduce the power consumption through LC tuning are not applicable.

Fig. 2.1(d) is desirable to have a narrowband RF signal processing, to get rid of out of band blockers. It employs inductive source degeneration to generate a real term in the input impedance. It offers the possibility of achieving the best noise performance of any architecture. That will describe in following sub-section.

2.2.2 Inductive source degeneration LNA Analysis

Fig. 2.2 Cascode LNA architecture.

Fig. 2.3 Small-signal model for LNA noise model [3].

The basic cascode LNA architecture is shown in Fig. 2.2. The input impedance is derived as

in s g s T s

gs gs

1 g

Z =s(L +L )+ +( )L = L (at resonance)

sC C ω . (2-6) The impedance matching achieved by multiplication of cutoff frequency and Ls. The noise model can be derived by analyzing the circuit shown in Fig. 2.3. Rg is the gate resistance of the NMOS device. The channel thermal noise of the device denotes

i . The portion of the total gate noise with and without correlating the drain noise denote i^g²^,^c and i^g²^,^u respectively. The noise factor is defined as

Total_output_noise

F=Total_output_noise_due_to_the_source. (2-7)

To evaluate the output noise based on driven by a 50Ω source, the transconductance of the input stage is computed first. With the output current proportional to the voltage on Cgs, and noting that the input circuit takes the form of a series-resonant network

m T The output noise power density due to source Rs is

The noise power density associated with the correlating portion of the gate noise to drain noise can be expressed as

d g d The power spectral density of un-correlating gate noise and drain noise is derived as

g d

The noise contribution of the drain noise comes from the first device M1

proportional to

S

^{a i}^,^d( )

ω

^o . Hence, it is convenient to define the contribution of M1 as the noise factor can be re-expressed as

g o

The equations show that

χ

proportional to QL2. The noise factor is proportional to

χ

over QL. Thus a minimum F exists for a particular QL.

Chapter 3 Ultra-Wideband Tunable Low Noise Amplifier

3.1 Introduction

Some diverse topologies of low noise amplifier with output tunable load are proposed in this chapter to relax the linearity limitation of the next stage in receiver front- end and to increase the dynamic range.

Section 3.2 addresses the architecture of 6 to 10 GHz ultra-wideband tunable low noise amplifier. Section 3.3 delineates the detail description of the amended circuit based on measurement results proffered to improve the noise performance and to enhance the tunable range. High quality MEMS inductors are used to promote the noise performance and frequency tunable range over 3 to 8 GHz presented in section 3.4.

3.2 A 6 to 10 GHz UWB Tunable LNA

3.2.1 Ultra-Wideband Tunable LNA Circuit Topology

To design an LNA for the frequency hopping system, it is better to allow only the signal in the specified sub-band to pass through the path rather than signal in the entire band. In doing so, out-of-band and in-band noise is rejected such that the linearity or dynamic range requirement of the following stage can be greatly relaxed.

This has been applied to LNA design in [5, 6]. In this section, an LNA is designed to operate over a wide frequency tuning range from 6GHz to 10GHz, which are the sub-bands of group C and group D in the UWB spectrum allocation. The frequency

tuning rang exceeds 4GHz, which is great larger than that of 6% in [5], and that of 35% in [6]. Given the target of frequency tuning range over several GHz, the designed LNA requires wideband input impedance matching network different from the inductive source degeneration used in the conventional narrow-band CMOS LNA [3].

In addition, gain level over the entire band must remain as flat as possible. The schematic of the proposed LNA circuit is as shown in Fig. 3.1, consisting of cascode configuration and a source-follower output buffer. The circuit achieves the wideband input matching by a three-section band-pass Chebyshev filter configuration [7]. The inter-stage inductor, Lb, improves gain flatness among sub-bands. A varactor, Cvar, provides frequency tuning capability. Technologies to achieve the wideband tuning and gain flatness are discussed narrowly below.

Fig. 3.1 Shematic of the poposed ultra-wideband tunable LNA.

3.2.2 Broadband Matching Techniques

The technique of filter design is employed for broadband input impedance matching. The two kinds of the most common used filter design technique are image

parameter method and insertion loss method. The first one, image parameter method, consists of a cascade of simpler two-port filter sections to provide the desired cutoff frequencies and attenuation characteristics. Thus, although the procedure is relatively simple, the design of filters by image parameter method often must be iterated many times to achieve the desired results and that will result in large chip area. The other one, insertion loss method, uses network synthesis techniques to design filters with a completely specified frequency response. The design is simplified by beginning with low-pass filter prototypes that are normalized in terms of impedance and frequency.

Transformations are applied to convert the prototype designs to the desired frequency range and impedance level [8]. The insertion loss method is used to design the broadband input impedance matching for diminishing the implement cost. The Butterworth and Chebyshev filter design are two familiarly practical filter responses by used insertion loss method. The Butterworth design offers a smooth response curve with maximal flatness at zero frequency. The Chebyshev design offers a steeper response curve at the 3 dB cutoff frequency and requires fewer components. In this work, to have precipitous response curve at 3 dB cutoff frequency, the Chebyshev filter design is chosen. The design of a Chebyshev filter will begin at low-pass filter prototypes which are normalized in terms of impedance and frequency; this normalization simplifies the design. The low-pass prototypes are then scaled to the desired frequency and impedance. The design process is illustrated in Fig. 3.2.

Filter

specifications Low-pass

prototype Scaling and

transformation Circuit implement Filter

specifications Low-pass

prototype Scaling and

transformation Circuit implement

Fig. 3.2 The process of filter design.

In the insertion loss method, a filter response is defined by its insertion loss, or power loss ratio, PLR,

LR 2

Power available from source 1

P = Power delivered to load ⁼1 | ( ) |− Γω , (3-1)

2 2

M( )

| ( ) |

M( ) N( ) ω ω

ω ω

Γ =

+ , (3-2) where M and N are real polynomials inω². Substitute equation (3-2) into (3-1), thus PLR can be re-expressed as

) N(

) 1 M(

P ₂

LR ω

+ ω

= . (3-3)

In this work, the Chebyshev polynomial is used to specify the insertion loss of an N-order low-pass filter as

2 2

LR N

P =1+k T ( ω )

ω , (3-4) then a sharper cutoff will result.T_N(x) Oscillates between ± 1 for x ≤1, and

k determines the pass-band ripple level. From the power loss ratio equation of 2

Chebyshev filter, the normalized element values of L and C of low pass filter prototype can be figured out. The element definitions of the ladder circuits for low-pass filter prototypes is shown in Fig. 3.3, and the normalize values are listed in Table 3.1.

Fig. 3.3 Ladder circuit for low-pass filter prototypes and their element definitions.

Table 3.1 Element values for Chebyshev Low Pass Filter prototypes (g0=1, ω_c=1, ripple=0.5dB)

N (order) g1 g2 g3 g4

1 0.6986 1.0000

2 1.4029 0.7071 1.9841

3 1.5963 1.0967 1.5963 1.0000

Low pass filter prototypes design could be transferred to be a band-pass filter response. At the beginning, scale the impedance from unity to the load and source impedance, and also scale the frequency from unity of the low pass prototype to the cutoff frequency of the band-pass one. ω₁and ω₂ denote the 3-dB cut-off frequency of the band-pass filter. Thus the band-pass response could be obtained as

0 0 0

The low-pass prototype transfers to the band-pass filter type based on Table 3.1.

The low-pass filter elements are converted to series or parallel resonant circuits. The low impedance at resonance, such as a series inductor, Lk, converts to a series LC circuit with element values of Table 3.1,

The high impedance at resonance, such as a shunt capacitor, Ck, transfers to a shunt LC circuit with element values of Table 3.1,

L '=k

ω C

∆ , (3-8)

k k 0

C '= C ω

∆ . (3-9) Both series and parallel resonator have the same resonant frequency ofω₀. Fig. 3.4 shows that condition, where Z0 means the source impedance. Fig. 3.5 shows the complete transformation circuit of low-pass filter converted to band-pass filter.

Low-pass Bandpass

Fig. 3.4 Components convert from low pass filter to band-pass filter.

(a) Series inductor transferred to series LC (b) Parallel capacitor transferred to shunt LC

L1 L₁

Fig. 3.5 The transformation circuit of low pass filter converted to band-pass filter.

Employ the filter design technique to do the broadband input impedance matching from 6 to 10 GHz. The small signal model of the input matching network is as shown in Fig. 3.6.

Fig. 3.6. The small signal model of the input impedance.

The filter actually makes use of the parasitic gate-source capacitance Cgs. The values of all elements are chosen following the third-order Chebyshev filter design which have discussed above with corner frequencies set to be 6GHz and 10GHz. The input impedance is derived as

Similar to narrow-band matching, the source inductor, Ls, results in a real resistive value equal to gmLs/Cgs1 to match with the source impedance of 50ohm.

The size of the transistor M1 must be selected carefully. The parasitic capacitance Cgs1 must follow the required component value in the filter design. On the other hand, the device size must yields to sufficient noise performance and power constraint [9]. It may be necessary to adjust the filter corner frequency and choose a reasonable size in order to meet all the specifications.

3.2.3 Tunable RLC Tank

The frequency tuning is achieved by the first order RLC tank, as shown in Fig 3.7. Thus we could derive the impedance as below.

Fig. 3.7 The first order RLC tank.

( ) ( ) ( )

Consequently, choose tuning L or tuning C according to the result of

ω ω

( . In this work, sub-band in 500MHz should be selected. Thus,

the load impedance should not be steep. That is to say the quality of output tunable load must be poor. Larger C will result in narrower selective band. To fix the capacitor value while tuning the inductor, the quality of selective bands independence with

frequency, as shown in Fig. 3.8. If larger C is picked the impedance magnitude will be more precipitous, as the black line shown in Fig. 3.8. Tow of the most used ways for tunable inductors are switching and active inductors. To switch inductors will increase chip area, besides the poor Q resulting from switching parasitic resistors must be considered. There is no such issue in active inductors, but power consumption increase. To maintain low power level, hence a tunable MOS varactor capacitor is chosen to provide frequency tuning. The smaller inductor is chosen to preserve quality factor in the high frequency, as the blue line with circles shown in Fig. 3.9.

4 6 8 10 12 14 16

2 18

20 40 60 80

0 100

Frequency (GHz)

Zin (magnitude)

Fig. 3.8 Fix C and tuning L. (the black line shows the larger C value, and the blue line with circle shows the smaller C value.)

4 6 8 10 12 14 16

Fig. 3.9 Fix L and tuning C. (the black line shows the larger L value, and the blue line with circle shows the smaller L value.)

In this design, frequency tuning is achieved by a tunable LC tank at the output of the common-gate transistor drain. This resonator consists of a fixed-value inductor and a MOS varactor. To obtain frequency tuning over 6~10GHz, the value of the capacitance in this work varies from 0.46pF to 1.46pF. The equivalent circuit model of the LC tank is as shown in Fig. 3.10, including the gate-drain capacitor, Cgd2, of M2. The resistors Rls, and Rcs, standing for the parasitic of the inductor Ld and the varactor Ct, respectively, degrade the quality factor of the resonator. The resonance frequency and the quality factor are therefore determined as

3.2.4 Gain Compensation Technique

At resonant frequency, the gain of this LNA is mainly proportional to the LC tank impedance level, which can be derived as

Higher Q value of the LC tank leads to larger LNA gain. Besides, the impedance level appears to be smaller at lower frequencies. To maintain gain flatness, an inductor Lb is inserted into the cascode stage to enhance the circuit transconductance, Gm1, at lower frequencies. The small signal model of the input stage is shown in Fig.3.11. The Gm1

can be derived as equation (3-14).

V

Fig.3.11 The small signal model of the input stage.

)

Cx is the sum of the gate-to-drain capacitor and drain-to-source capacitor of M1. The factor of (s²L_bC_x +1) is less than one at low frequencies such that Gm1 is enhanced.

3.2.5 Design Considerations and Trade off

This is a tunable low noise amplifier with wideband tunable load and broadband input impedance matching. Since the Cgs of M1 included into the Chebyshev broadband filter design, the capacitance must be around 250fF. Therefore, the size of M1 is selected to conform to the broadband matching issue. In this work, 132.5um width and the 0.18um length are chosen. However, such choice leads to mismatch noise optimum and the low power level. To overcome those issues, another amended circuit is proporsed in section 3.3.

In order to compensate the smaller gain at the lower frequency which comes from the poor Q factor of the MOS varactor, the inter- stage inductor Lb included is 1.8nH to enhance the transconductance at 6~7GHz. While load impedance is higher, and then the gain is larger. Therefore, the Q factor of the load inductor, Ld , must be as

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