Resonance Matching Technique

The input impedance small signal model is as shown in Fig.3.23, the well-known narrow band impedance can be derived as Z, which the impedance trend in smith chart is shown as the solid line in Fig. 3.24. At the resonant frequency,ω₀, impedance of Z is matched to 50 ohm, and while the operation frequency is upper than the resonant frequency, Z characters an inductive impedance, and otherwise characters a capacitive impedance. Tank, L1 and C1 is added to provide capacitive impedance in the upper operation frequency to compensate the inductive one, and the same compensation technique is in the lower operation frequency. The impedance compensation trend is the dot line, Z^’ , as shown in Fig. 3.24. The broad band input impedance matching is achieved by the resonance technique.

Fig. 3.23 The input impedance small signal model.

( ) 1

Fig. 3.24 The impedance trend in smith chart.

3.3.3 Design Considerations and Trade off

As mentioned in section 3.3.1, the tunable load impedance is different from the switch transistor turned on or off. Thus the gain of tunable LNA in this work is mainly proportional to the LC tank impedance level at resonance frequency, which can be derived as To compare equation (3-23) with (3-24), there is smaller load impedance at low frequency due to the parasitic resistance of switched transistor, Rgmp. The smaller load impedance level leads to the low power gain. Thus, the power gain at low frequency is enhanced by boosted the transconductance, Gm1, of M1 at 6-to-7 GHz. The Gm1

could be derived as

Real axis of the Smith chart )

s g m

s

gs Q g L

L L

C _{1 0 1}

0

, 1 ) (

1

ω =ω

= + . (3-26)

Obviously, Gm1 is shown as a second order low pass filter. The Q value of that filter is designed to enhance Gm1. Besides Gm1 to be augmented for low gain level, the high Q value of the LC tank also leads to large LNA gain. Thus, how large the parasitic resistance is must be concerned while the size of switched transistor is chosen. The larger size of switched transistor is, the smaller parasitic resistance is. But the large size of Msw leads to large overlap capacitor, Covgd. That will result in the large capacitor of Ctot2 at Msw turned off, as shown in Fig 3.22(e), which comes the operation frequency drift to lower then what designed. In this work, the size of Msw

would be chosen at 87.5um width and 0.18 lengths. In this work, the Cgs of M1 does not be included into the broadband filter design and the noise optimization could be achieved. The noise figure is optimized to be 3.23-to-3.8 dB. The source- follower buffer is biased by the voltage divided of R1 and R2. The process variation of resistors must be concerned to make sure the output buffer satisfied the output impedance matching to 50 ohm for measurement.

3.3.4 Consideration of Layout

The higher Q value of the inductor Ld is, the larger gain of the LNA has. The small inductor leads to the Q peak at higher frequency. In this work, small inductor value of 0.5nH is used. In order to move the Q peak into 6- to 10 GHz, the width of Ld is 34um. The total chip area is 0.825mm by 0.94mm. The RF input and output ports are placed on opposite sides of the chip to improve the isolation of the output to input port. The patterned ground shield is used for reduce substrate noise. Except Ld , all other inductors are used by the layout of TSMC supported. All long interconnects should be minimized and built on the most top metal to minimize the substrate loss.

All interconnects of the DC voltage supply has bypass capacitors to be ac ground path to reduce the parasitic inductances.

3.3.5 Microphotograph of Chip

The microphotograph of the tunable LNA circuit is shown in Figure3.25. The circuit is fabricated in the TSMC 0.18µm CMOS process technology. The die area including bonding pads is 0.825 mm by 0.94 mm.

L₁

Fig. 3.25 Microphotograph of the amended tunable LNA.

3.3.6 Simulation and Measurement results and Discussion

Measurement is conducted by on-wafer RF probing. Measured results are plotted as shown from Fig. 3.26 to Fig.3.29. The LNA measurement shows frequency tunable range from 6.3GHz to 9.3GHz, which is smaller then design due to 100fF

parasitic capacitance in the layout of the tunable LC tank load. The measured power gain S21 achieves the maximum value of 9.3dB at 9.4GHz. According to equation (3-23), while the parasitic resistance of the switched transistor is large and thus the power gain will become small. The measured gain is larger at high frequency then at low frequency due to Cgs1 of M1 is smaller then designed; thus comes at Gm1 enhanced at high frequency. Fig. 3.26 shows the condition. The input return loss is shown in Fig.

3.27. As we mentioned in section 3.3.4, all the metal lines of DC bias supply need bypass capacitors to be ac ground path to reduce the parasitic inductance. However, the metal line of the gate bias for M1 had been left out to add the ac ground path. The parasitic inductance of 10pH needs to be added. 10fF of layout parasitic capacitor of C1 also has to be included. The smaller Cgs1 of M1, the added parasitic inductance and the capacitance are all together included to re-simulate the input impedance, and thus the input impedance trend is more matched to measurement results. The measurement and simulation result of output return loss, S22, is shown in Fig. 3.28. Fig. 3.29 is the simulation and measurement result of noise figure. The linearity analysis is conducted by the two tone test. Fig.3.30 is the IIP3 measured data. The total power of the tunable LNA is 17.44mW with a power supply 1.5V. Table 3.3 is the summary of measured performance and comparison to the previous tunable amplifier.

6 7 8 9 10

Switch on Switch off

6 7 8 9 10

Switch on Switch off

(a) S22 Simulation

Switch on Switch off

6 7 8 9 10

Switch on Switch off

6 7 8 9 10

(b) S22 measurement

Fig. 3.26 S21 simulation and measured result of the amended tunable LNA, (a) is the simulation result and (b) is the measurement result.

4 6 8 10

2 12

-20 -15 -10 -5

-25 0

Frequency (GHz)

S11 (dB)

Sim. w/ troubleshooting Sim.

Meas.

4 6 8 10

2 12

-20 -15 -10 -5

-25 0

Frequency (GHz)

S11 (dB)

Sim. w/ troubleshooting Sim.

Meas.

(a) S11 measurement and simulation results

freq (2.000GHz to 12.00GHz)

S11

Sim. w/ troubleshootingSim.

Meas.

freq (2.000GHz to 12.00GHz)

S11

Sim. w/ troubleshootingSim.

Meas.

(b) S11 smith chart

Fig. 3.27 S11 simulation and measured result of the amended tunable LNA, (a) S11 measurement and simulation results and (b) S11 smith chart trend.

7 8 9 10

6 11

-35 -30 -25 -20 -15 -10

-40 -5

freq, GHz

S22 (dB)

(a) S22 simulation

7 8 9 10

6 11

-14 -12 -10 -8 -6

-16 -5

Frequency (GHz)

S22 (dB)

(b) S22 measurement

Fig. 3.28 S22 simulation and measured result of the amended tunable LNA.

(a) The simulation result, (b) The measurement result.

5 6 7 8 9 10

4 11

4 5 6 7

3 8

freq, GHz

NF (dB)

(a) NF simulation

3 4 5 6 7 8 9 10

0 2 4 6 8 10 12 14

Frequency (GHz)

NF (dB)

(b) NF measurement

Fig. 3.29 Noise Figure of the amended tunable LNA. (a) simulation result (b) measurement result.

-12 -11 -10 -9 -8 -7 -6 -5 -4

5 6 7 8 9 10 11 12

Frequency (GHz)

IIP3 (dBm)

Meas.

Sim.

Fig. 3.30 IIP3

TABLE 3.3 Summary of measured performance and comparison to the previous tunable amplifier

Summary and Comparison Performance Section 3.2

Simulation Section 3.2

Measurement This work

Simulation This work Measurement Technology 0.18um TSMC CMOS Standard

Supply voltage 1.5V

S21(max) 11.6 dB 7 dB (at 6.8GHz) 14.9 dB 9.3 dB

S11 <-9dB <-4 (5~7GHz)

<-9 ^(7~11GHz) <-11dB <-6dB S22 <-12dB <-10 ^(5~7GHz) <-15dB <-10 dB S12 <-38 dB < -40(5~7GHz) <-40 dB <-41 dB

NF(average) 4.75 dB 5.7dB (at 6.8GHz) 3.5 dB 4.5 dB

IIP3(average) 1.15 dBm 3.2 dBm -10 dBm -6 dBm

Center Frequency

tuning range 6.0 ~ 10.0 GHz 5.1~6.8 GHz 6.3 ~ 10

GHz 6.3 ~ 9.4 GHz Frequency tuning

ratio 50% 28% 45.3% 39.5%

Area 0.813 mm² 0.776 mm²

Power

consumption 19.6 mW 19.51 mW 17.4 mW 17.44 mW

3.4 A Tunable LNA with MEMES Inductors for UWB Mode-2 Device

3.4.1 Motivation

As mentioned in section 3.2, to do the wideband frequency tuning could be achieved by switching capacitors or inductors while those components have high quality factors. Nowadays, the high performance of micromachined spiral inductors has been proposed [10]. The inductor with the underneath substrate removal has four times quality factor improvement than the conventional one. The suspended inductors with the cross membrane supporting and the underneath substrate removal have not only high Q performance but also better reliability for wideband application [11]. To do frequency tunable range from 3.1 GHz to 8 GHz, there is congenital limitation by only using MOS varactor as discussed in section 3.2. To enhance the tunable range with switched capacitor is proposed in section 3.3, but this way the poor quality factor of large capacitance will degrade the gain at low frequency. Thus, to maintain gain flatness over 5GHz is a critical consideration. In this section, switched micromachined inductors and MOS varactor used to make the frequency tunable capability. To integrate micromachined inductors with the chip die of 0.18um CMOS process, the thermo- compression boding technique is used. The LNA of frequency tuning range over 5 GHz, low noise performance and low power consumption is proposed.

3.4.2 Circuit Architecture

The schematic of the proposed LNA circuit is similar to that in section 3.2, as shown in Fig. 3.31, exception the inductor switched mechanism and the external capacitor parallel with Cgs of M1 included. The wideband input matching by a three-section band-pass Chebyshev filter configuration consists of L1, L2, Lg, Ls, C1,

C2, Cex and Cgs of M1, where Cex provides enough capacitance for satisfying the filter design issue. Micromachined inductors, L1, L2, and Lg have small parasitic resistance due to substrate lossless with underneath substrate removal. Thus, the thermal noise will be decreased apparently. Msw is used to switch inductors. A large resister Rb is employed to provide high impedance for reducing the overlap parasitic capacitances.

The micromachined inductor, Ld1, is utilized to provide high power gain. M3 and M4

implement a source- follower output buffer. R1 and R2 are used to bias the buffer.

L1 C₁

RF

in

L

g

RFout

C

var

V

gs

L

s

M

1

M2

M

3

M4

V

tune

V

sw

V

DD

R

1

R

2

M

sw

L

2

1

L

d 2

L

d

C

ex

C

2

Fig. 3.31 The schematic of the tunable LNA for 3~8 GHz.

(Where inductors with dot line are MEMS fabricated.)

3.4.3 MEMS Inductors

The micromachined inductor is fabricated with underneath substrate removal to decrease the substrate loss at high frequency and that will provide a high quality factor inductor. However, the micromachined passive components tend to be affected by the external disturbance, such as air pressure, mechanical thermal force and gravity, etc. Thus, the suspended inductors with the cross membrane supporting are proposed to increase the reliability of the micromachined inductors [11]. The suspended inductor with the cross membrane supporting high Q performance of micromachined spiral inductors is shown in Fig. 3.32, and the cross view of the cross membrane inductor is shown in Fig. 3.33. The measurement result of high Q inductors is shown in Fig.3.34. The measurement shows that the Q of inductor can achieve 45, while the inductor value is around 4nH at 4~8GHz. The amazing good performance is expected to improve the circuit design for radio frequency.

Fig. 3.32 The suspended inductor with the cross membrane supporting

Fig. 3.33 The cross view of the cross membrane inductor.

Fig. 3.34 The measurement result of the cross membrane inductor.

(Where S denotes suspend, M denotes membrane and CM denotes cross membrane.)

3.4.4 Ultra Wide-band Tunable Load

The tunable load with switched capacitor, as shown in Fig. 3.35(a), is discussed in section 3.3. The power gain is proportion to Q value of the load as mentioned in section 3.3. Therefore, using switched capacitor can not maintain gain flatness due to Q degraded for a large capacitor at low frequency. High Q MEMS inductors are used to maintain gain flatness over several GHz. Output tunable load with switched inductor consist of Ld1, Ld2 and Msw, as shown in Fig. 3.35(b).

Vsw

Csw Msw

L

Vdd Vtune Vsw

Msw

Ld1 Ld2 Cvar

Cvar

Vtune

(a) (b)

Fig. 3.35 The tunable mechanism (a) the switched capacitor, (b) the switched inductor

The equivalent model of switched inductors is shown in Fig. 3.36, where Rb is included to reduce the overlap parasitic capacitor. Fig. 3.36 (a) shows the equivalent model of switched transistor turned on. When Msw turns on, the signal current will flow as the blue line path. Otherwise, while Msw turns off, it will be the red path as shown in Fig. 3.36 (b).

Fig. 3.36 The effected inductor, (a) switch turned on, (b) switch turned off.

When Msw turns on, the effected inductance is as

ls p

d swon

eff d swon

eff R R

Q ωL L

L _{_} ≈ ₁, _{_} = +¹ . (3-27)

Rls is the parasitic resistance of Ld1. The Q value of effected inductor will degrade by Rls and Rp. As mentioned in section 3.1, Q values of L and C will affect the load

impedance level. Therefore, the high Q micromachined inductor, Ld1, is used to maintain high enough load impedance. While Msw turns off, the effected inductor value is as

Obviously, there is a self resonant frequencyω_self = L_d2C_ovp . The self resonant frequency must move over the operating frequency to diminish the effect, as shown in Fig. 3.37. Small Covp results in high self resonant frequency. Small Covp indicates small size of Msw, which will increase the parasitic resistance Rp. Therefore, the optimum size of Msw is a critical design in this work.

4 6 8 10 12 14

Fig. 3.37 The equivalent inductor value.

3.4.5 Noise Considerations

The broadband input matching approach in section 3.2 is trade off by the noise performance and the power consumption. To improve the noise performance, the high Q micromachined inductors are used in input broadband matching to decrease the thermal noise. The external capacitor parallel with C of M is applied

for power level decreasing. The noise model of NMOS with external capacitor is shown in Fig. 3.38(a), and the small signal model is in Fig. 3.38(b). The equivalent noise voltage and current source are derived as equation (3-29) and (3-30) for without and with external capacitor, respectively.

ind

Cex i_nd

noiseless

iout

Fig. 3.38 The noise model, (a) NMOS with external capacitor, (b) the small signal noise model, (c) the equivalent noise model.

rg

Let the value of the gate- to- source capacitor is fixed. Compare with two conditions,

Cex conclude that the noise will be decreased by external capacitor added.

3.4.6 Consideration of Layout

To test the DC current, the consideration schematic and layout is shown in Fig. 3.39 and Fig. 3.40. In Fig. 3.39, the dot line pad, VDD_DC and Vgs_DC, is only for DC current test. The dot line between Ld2 and drain of M2 is used for DC current path of testing and it will be moved by laser cut. Another dot line between gate of M1 and pad, Vgs_DC, is used to bias M1, and will be removed too. L1, L2, Lg, and Ld1 are fabricated in micromachined inductors. In order to bond the chip die with the micromachined inductors, the passivating layer is drawn on the connected point. All interconnect metal lines are considered for circuit design.Fig.3.40 shows the layout of the chip die.

Fig. 3.39 Schematic of the tunable LNA fabricated on the chip die

L

_s

L

_d2

V

_gs

_DC

V

_DD

_DC GND

GND

GND

L₂ L₁

L_g

L_d1

L

_s

L

_d2

V

_gs

_DC

V

_DD

_DC GND

GND

GND

L₂ L₁

L_g

L_d1

Fig. 3.40 Layout of the chip die

3.4.7 Package Integrated Technique

The complete layout of this work is shown in Fig. 3.41. All the ground pads are connected together to have the same reference plan for the chip die and the micromachined inductors mask. The thermo- compression bonding is used as shown in Fig. 3.42. The temperature is better at 375⁰C for fusing the connected gold metal layer.

Fig. 3.41 Layout of the complete integrated circuit

Substrate removal

Fig. 3.42 The bonding technique

3.4.8 Simulation results and Comparison

Lastly, the simulation results and compare with that similar circuit with switched MIM capacitor summarized in section 3.2. Table 3.4 shows that.

TABLE 3.4 Summary of simulation performance and comparison to the circuit of section 3.2

Summary and Comparison Performance Circuit of Section 3.2

Simulation Switched with MIM Cap.

Circuit of this work Simulation Switched with MEMS Ind.

Technology 0.18um TSMC CMOS Standard

Supply voltage 1.5V

Center Frequency

Chapter 4

Conclusion

The wideband tunable LNA apply for the receiver path of UWB system was proposed and the amended tunable circuit for band tuning capability was also fabricated in standard TSMC 0.18µm CMOS process. The tunable LNA achieved tunable frequency range over 6.3 GHz to 9.3 GHz. To enhance the tunable range and to improve the noise performance, the high Q MEMES inductors were integrated with the tunable low noise amplifier in the third circuit. The tunable LNA circuit with MEMS inductors was proposed in low power level and achieved ultra- wideband frequency tunable range over 3.1GHz to 8GHz and average noise figure of 3.5dB in 10.5 mW power used.

Chapter 5

Future Work

The wideband tunable LNA with MEMS inductors for UWB Mode-2 device is

taped out. While the measurement is consistent with the target proposed, the circuit can extended to a wideband tunable front- end receiver for UWB system in low noise and low power performance.

REFERENCES

[1] K. Mandke, and H. Nam, and L. Yerramneni, and C. Zuniga, “The Evolution of Ultra Wide Band Radio for Wireless Personal Area Netwoks,” Summit Technical Media, LCC, High Frequency Electronics, Sep. 2003.

[2] IEEE 802.15 WPAN High Tate Alternative PHY Task Group 3a(TG3a)[Online].

[3] D. K. Shaeffer and T. H. Lee, “A 1.5V, 1.5GHz CMOS Low Noise Amplifier,”

IEEE Journal of Solid-State Circuit, vol. 32,no.5, p.745, May. 1997.

[4] T. H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits, Chapter 10, Cambridge.

[5] T. K. K. Tsang, and M. N. El-Gamal, “Gain and frequency controllable sub-1V 5.8GHz CMOS LNA,” IEEE International Symposium on Circuits and Systems, vol. 4, pp.795-798, May. 2002.

[6] M. Benmansour, and P. R. Mukund, “A tuned wideband LNA in 0.25/spl mu/m IBM process for RF communication applocations,” IEEE International Conference on VLSI Design, Proceedings. 17th, pp. 631-634, 2004.

[7] A. Bevilazqua, “An Ultra-Wideband CMOS LNA for 3.1 to 10.6GHz Wireless Receivers,” IEEE International Solid-State Circuits Conference, vol. 37, pp.382-383, 2004.

[8] D. M. Pozar, Microwave Engineering, Chapter 6, Second edition, Wiley.

[9] J. M. Lopev-Villegas, “Improvement of Quality Factor of RF Integrated Inductors by Layout Optimization,” IEEE Proc., vol. 48, No1. Jan. 2000.

[10] H. Lakawala, X. Zhu, H. Luo, S. Santhanam, L. R. Carlaey and G. K. Fedder,

“Micromachined high-Q inductors in a 0.18-um copper interconnect low-k dielectric CMOS process”, IEEE, J. of Solid-State Circuits, vol.37, no.3, pp.

394-403, March 2002.

[11] J. W. Lin, An Optimum Design of the Micromachined RF Inductor, Master Thesis, National Chiao-Tung University, 2004.

[12] B. Razavi, RF Microelectronics, Chapter 6, PH PTR.

Vita

姓 名: 陳仰鵑

學 歷:

國立清華大學電子工程學系 ( 88 年 9 月 ~ 92 年 6 月) 國立交通大學電子工程所 ( 92 年 9 月 ~ 94 年 7 月)

Publication

Yang-Chaun Chen, Chien-Nan Kuo, "A 6~10-Ghz Ultra-Wide Band Tunable LNA", IEEE International Symposium on Circuits and Systems, May. 2005.

在文檔中 應用於超寬頻系統之可調頻低雜訊放大器 (頁 49-0)