Inductive Source Degeneration LNA Analysis

Fig. 2.2 Cascode LNA architecture.

Fig. 2.3 Small-signal model for LNA noise model [3].

The basic cascode LNA architecture is shown in Fig. 2.2. The input impedance is derived as

m1

in s g s T s

gs gs

1 g

Z =s(L +L )+ +( )L = L (at resonance)

sC C ω . (2-6) The impedance matching achieved by multiplication of cutoff frequency and Ls. The noise model can be derived by analyzing the circuit shown in Fig. 2.3. Rg is the gate resistance of the NMOS device. The channel thermal noise of the device denotes

d2

i . The portion of the total gate noise with and without correlating the drain noise denote i^g2,c and i^g2,u respectively. The noise factor is defined as

Total_output_noise

F=Total_output_noise_due_to_the_source. (2-7)

To evaluate the output noise based on driven by a 50Ω source, the transconductance of the input stage is computed first. With the output current proportional to the voltage on Cgs, and noting that the input circuit takes the form of a series-resonant network

m T The output noise power density due to source Rs is

T2

The noise power density associated with the correlating portion of the gate noise to drain noise can be expressed as

d g d The power spectral density of un-correlating gate noise and drain noise is derived as

g d

The noise contribution of the drain noise comes from the first device M1

proportional to

S

^{a i,d}( )

ω

^o . Hence, it is convenient to define the contribution of M1 as the noise factor can be re-expressed as

g o

The equations show that

χ

proportional to QL2. The noise factor is proportional to

χ

over QL. Thus a minimum F exists for a particular QL.

Chapter 3

Ultra-Wideband Tunable Low Noise Amplifier

3.1 Introduction

Some diverse topologies of low noise amplifier with output tunable load are proposed in this chapter to relax the linearity limitation of the next stage in receiver front- end and to increase the dynamic range.

Section 3.2 addresses the architecture of 6 to 10 GHz ultra-wideband tunable low noise amplifier. Section 3.3 delineates the detail description of the amended circuit based on measurement results proffered to improve the noise performance and to enhance the tunable range. High quality MEMS inductors are used to promote the noise performance and frequency tunable range over 3 to 8 GHz presented in section 3.4.

3.2 A 6 to 10 GHz UWB Tunable LNA

3.2.1 Ultra-Wideband Tunable LNA Circuit Topology

To design an LNA for the frequency hopping system, it is better to allow only the signal in the specified sub-band to pass through the path rather than signal in the entire band. In doing so, out-of-band and in-band noise is rejected such that the linearity or dynamic range requirement of the following stage can be greatly relaxed.

This has been applied to LNA design in [5, 6]. In this section, an LNA is designed to operate over a wide frequency tuning range from 6GHz to 10GHz, which are the sub-bands of group C and group D in the UWB spectrum allocation. The frequency

tuning rang exceeds 4GHz, which is great larger than that of 6% in [5], and that of 35% in [6]. Given the target of frequency tuning range over several GHz, the designed LNA requires wideband input impedance matching network different from the inductive source degeneration used in the conventional narrow-band CMOS LNA [3].

In addition, gain level over the entire band must remain as flat as possible. The schematic of the proposed LNA circuit is as shown in Fig. 3.1, consisting of cascode configuration and a source-follower output buffer. The circuit achieves the wideband input matching by a three-section band-pass Chebyshev filter configuration [7]. The inter-stage inductor, Lb, improves gain flatness among sub-bands. A varactor, Cvar, provides frequency tuning capability. Technologies to achieve the wideband tuning and gain flatness are discussed narrowly below.

Fig. 3.1 Shematic of the poposed ultra-wideband tunable LNA.

3.2.2 Broadband Matching Techniques

The technique of filter design is employed for broadband input impedance matching. The two kinds of the most common used filter design technique are image

parameter method and insertion loss method. The first one, image parameter method, consists of a cascade of simpler two-port filter sections to provide the desired cutoff frequencies and attenuation characteristics. Thus, although the procedure is relatively simple, the design of filters by image parameter method often must be iterated many times to achieve the desired results and that will result in large chip area. The other one, insertion loss method, uses network synthesis techniques to design filters with a completely specified frequency response. The design is simplified by beginning with low-pass filter prototypes that are normalized in terms of impedance and frequency.

Transformations are applied to convert the prototype designs to the desired frequency range and impedance level [8]. The insertion loss method is used to design the broadband input impedance matching for diminishing the implement cost. The Butterworth and Chebyshev filter design are two familiarly practical filter responses by used insertion loss method. The Butterworth design offers a smooth response curve with maximal flatness at zero frequency. The Chebyshev design offers a steeper response curve at the 3 dB cutoff frequency and requires fewer components. In this work, to have precipitous response curve at 3 dB cutoff frequency, the Chebyshev filter design is chosen. The design of a Chebyshev filter will begin at low-pass filter prototypes which are normalized in terms of impedance and frequency; this normalization simplifies the design. The low-pass prototypes are then scaled to the desired frequency and impedance. The design process is illustrated in Fig. 3.2.

Filter

specifications Low-pass

prototype Scaling and

transformation Circuit implement Filter

specifications Low-pass

prototype Scaling and

transformation Circuit implement

Fig. 3.2 The process of filter design.

In the insertion loss method, a filter response is defined by its insertion loss, or power loss ratio, PLR,

LR 2

Power available from source 1

P = Power delivered to load ⁼1 | ( ) |− Γω , (3-1)

2 2

2 2

M( )

| ( ) |

M( ) N( ) ω ω

ω ω

Γ =

+ , (3-2) where M and N are real polynomials inω². Substitute equation (3-2) into (3-1), thus PLR can be re-expressed as

) N(

) 1 M(

P ₂

2

LR ω

+ ω

= . (3-3)

In this work, the Chebyshev polynomial is used to specify the insertion loss of an N-order low-pass filter as

2 2

LR N

c

P =1+k T ( ω )

ω , (3-4) then a sharper cutoff will result.T_N(x) Oscillates between ± 1 for x ≤1, and

k determines the pass-band ripple level. From the power loss ratio equation of 2

Chebyshev filter, the normalized element values of L and C of low pass filter prototype can be figured out. The element definitions of the ladder circuits for low-pass filter prototypes is shown in Fig. 3.3, and the normalize values are listed in Table 3.1.

Fig. 3.3 Ladder circuit for low-pass filter prototypes and their element definitions.

Table 3.1 Element values for Chebyshev Low Pass Filter prototypes (g0=1, ω_c=1, ripple=0.5dB)

N (order) g1 g2 g3 g4

1 0.6986 1.0000

2 1.4029 0.7071 1.9841

3 1.5963 1.0967 1.5963 1.0000

Low pass filter prototypes design could be transferred to be a band-pass filter response. At the beginning, scale the impedance from unity to the load and source impedance, and also scale the frequency from unity of the low pass prototype to the cutoff frequency of the band-pass one. ω₁and ω₂ denote the 3-dB cut-off frequency of the band-pass filter. Thus the band-pass response could be obtained as

0 0 0

The low-pass prototype transfers to the band-pass filter type based on Table 3.1.

The low-pass filter elements are converted to series or parallel resonant circuits. The low impedance at resonance, such as a series inductor, Lk, converts to a series LC circuit with element values of Table 3.1,

k

The high impedance at resonance, such as a shunt capacitor, Ck, transfers to a shunt LC circuit with element values of Table 3.1,

L '=k

ω C

∆ , (3-8)

k k 0

C '= C ω

∆ . (3-9) Both series and parallel resonator have the same resonant frequency ofω₀. Fig. 3.4 shows that condition, where Z0 means the source impedance. Fig. 3.5 shows the complete transformation circuit of low-pass filter converted to band-pass filter.

Low-pass Bandpass

Fig. 3.4 Components convert from low pass filter to band-pass filter.

(a) Series inductor transferred to series LC (b) Parallel capacitor transferred to shunt LC

L1 L₁

Fig. 3.5 The transformation circuit of low pass filter converted to band-pass filter.

Employ the filter design technique to do the broadband input impedance matching from 6 to 10 GHz. The small signal model of the input matching network is as shown in Fig. 3.6.

L1

Fig. 3.6. The small signal model of the input impedance.

The filter actually makes use of the parasitic gate-source capacitance Cgs. The values of all elements are chosen following the third-order Chebyshev filter design which have discussed above with corner frequencies set to be 6GHz and 10GHz. The input impedance is derived as

s

Similar to narrow-band matching, the source inductor, Ls, results in a real resistive value equal to gmLs/Cgs1 to match with the source impedance of 50ohm.

The size of the transistor M1 must be selected carefully. The parasitic capacitance Cgs1 must follow the required component value in the filter design. On the other hand, the device size must yields to sufficient noise performance and power constraint [9]. It may be necessary to adjust the filter corner frequency and choose a reasonable size in order to meet all the specifications.

3.2.3 Tunable RLC Tank

The frequency tuning is achieved by the first order RLC tank, as shown in Fig 3.7. Thus we could derive the impedance as below.

Fig. 3.7 The first order RLC tank.

( ) ( ) ( )

Consequently, choose tuning L or tuning C according to the result of

ω ω

( . In this work, sub-band in 500MHz should be selected. Thus,

the load impedance should not be steep. That is to say the quality of output tunable load must be poor. Larger C will result in narrower selective band. To fix the capacitor value while tuning the inductor, the quality of selective bands independence with

frequency, as shown in Fig. 3.8. If larger C is picked the impedance magnitude will be more precipitous, as the black line shown in Fig. 3.8. Tow of the most used ways for tunable inductors are switching and active inductors. To switch inductors will increase chip area, besides the poor Q resulting from switching parasitic resistors must be considered. There is no such issue in active inductors, but power consumption increase. To maintain low power level, hence a tunable MOS varactor capacitor is chosen to provide frequency tuning. The smaller inductor is chosen to preserve quality factor in the high frequency, as the blue line with circles shown in Fig. 3.9.

4 6 8 10 12 14 16

2 18

20 40 60 80

0 100

Frequency (GHz)

Zin (magnitude)

Fig. 3.8 Fix C and tuning L. (the black line shows the larger C value, and the blue line with circle shows the smaller C value.)

4 6 8 10 12 14 16

Fig. 3.9 Fix L and tuning C. (the black line shows the larger L value, and the blue line with circle shows the smaller L value.)

In this design, frequency tuning is achieved by a tunable LC tank at the output of the common-gate transistor drain. This resonator consists of a fixed-value inductor and a MOS varactor. To obtain frequency tuning over 6~10GHz, the value of the capacitance in this work varies from 0.46pF to 1.46pF. The equivalent circuit model of the LC tank is as shown in Fig. 3.10, including the gate-drain capacitor, Cgd2, of M2. The resistors Rls, and Rcs, standing for the parasitic of the inductor Ld and the varactor Ct, respectively, degrade the quality factor of the resonator. The resonance frequency and the quality factor are therefore determined as

3.2.4 Gain Compensation Technique

At resonant frequency, the gain of this LNA is mainly proportional to the LC tank impedance level, which can be derived as

Higher Q value of the LC tank leads to larger LNA gain. Besides, the impedance level appears to be smaller at lower frequencies. To maintain gain flatness, an inductor Lb is inserted into the cascode stage to enhance the circuit transconductance, Gm1, at lower frequencies. The small signal model of the input stage is shown in Fig.3.11. The Gm1

can be derived as equation (3-14).

V

in

Fig.3.11 The small signal model of the input stage.

)

Cx is the sum of the gate-to-drain capacitor and drain-to-source capacitor of M1. The factor of (s²L_bC_x +1) is less than one at low frequencies such that Gm1 is enhanced.

3.2.5 Design Considerations and Trade off

This is a tunable low noise amplifier with wideband tunable load and broadband input impedance matching. Since the Cgs of M1 included into the Chebyshev broadband filter design, the capacitance must be around 250fF. Therefore, the size of M1 is selected to conform to the broadband matching issue. In this work, 132.5um width and the 0.18um length are chosen. However, such choice leads to mismatch noise optimum and the low power level. To overcome those issues, another amended circuit is proporsed in section 3.3.

In order to compensate the smaller gain at the lower frequency which comes from the poor Q factor of the MOS varactor, the inter- stage inductor Lb included is 1.8nH to enhance the transconductance at 6~7GHz. While load impedance is higher, and then the gain is larger. Therefore, the Q factor of the load inductor, Ld , must be as larger as possible. The technique of layout optimization[9] usd increase the quality factor up to 15~16.

3.2.6 Consideration of Layout

As discussed in Section 3.2.5, the higher Q value of the inductor Ld is, the larger gain of the LNA has. Standard CMOS integrated inductors have inherently low quality factor because of serious substrate losses at GHz frequencies. The technique of layout optimization [9] is used to increase the quality factor. The symmetric two-turn inductors are built on the top most metal layer. The width of the inductor is smaller gradually from the outer circle into the inner circle to increase the internal diameter.

The width of the outer circle is larger, 34um, to move the Q peak into 6-10 GHz. The quality factor is larger than 15 at 6-10GHz as shown in Fig. 3.12.

4 5 6 7 8 9 10 11

3 12

11 12 13 14 15 16

10 17

freq, GHz

Q

4 5 6 7 8 9 10 11

3 12

11 12 13 14 15 16

10 17

freq, GHz

Q

Fig. 3.12 The quality factor of the inductor Ld .

The total chip area is 0.897mm by 0.906mm. The RF input and output ports are placed on opposite sides of the chip to improve the isolation of the output to input port.

The patterned ground shield is used for reduce substrate noise. All long interconnects should be minimized and built on the most top metal to minimize the substrate loss.

3.2.7 Microphotograph of Chip

The microphotograph of the tunable LNA circuit is shown in Figure3.13. The circuit is fabricated in the TSMC 0.18µm CMOS process technology. The die area including bonding pads is 0.897 mm by 0.906 mm.

G RFin

RFout G

G

G G Vdd

G Vtune

Vbias Vbias

Ld

Lb

G RFin

RFout G

G

G G Vdd

G Vtune

Vbias Vbias

Ld

Lb

Fig. 3.13 Microphotograph of the tunable LNA.

3.2.8 Simulation and Measurement results and Discussion

Measurement is conducted by on-wafer RF probing. Measured results are plotted from Fig. 3.14 to Fig.3.20. Compare with simulation data, the LNA measurement results show narrower tunable range and lower operation frequency over 5.1GHz to 6.8GHz. The measured power gain S21 achieves the maximum value of 7dB at 6.8GHz. Fig. 3.14 shows that condition, the solid black line is the simulation result and the dot gray one the measurement data. The tunable frequency drifts due to

inconsistency of MOS varactor models in design kit of simulator, ADS, and layout model. The discrepancy is shown in Fig. 3.15. Obviously, the varactor capacitance of the layout model in TSMC document is larger then that of the design kit in ADS simulator. Thus the unconfirmed varactor model used results in the conflict measurement results. To re-simulate the circuit used the affirmed varactor model, and then the tunable frequency matches to the measurement data, as shown in the Fig.

3.16. The input return loss is shown in Fig. 3.17, the black line is the measurement data, and the blue line is the simulation data, and the red line with squares is the simulation with 10% drift of the inductors. After considering the 10% drift of the inductors, L1, L2, Lg, and Ls, and to re-simulate the circuit gets the similar trend to the measurement data. The measurement and simulation result of output return loss, S22, is shown in Fig. 3.18. Fig. 3.19 is the simulation result of noise figure. Since S11 and S21 matched at 6.8GHz only, therefore the noise figure at 6.8GHz is 5.7dB. The linearity analysis is conducted by the two tone test. Fig.3.21 is IIP3 measured data;

lower power gain results in higher linearity. The total power of the tunable LNA is 19.51mW with a power supply 1.5V. Table 3.2 is the summary of measured performance and comparison to other tunable amplifier.

5 6 7 8 9 10 11

4 12

-3 2 7

-8 12

frequency (GHz)

S21 (dB)

Fig. 3.14 S21 simulation and measured result of the tunable LNA. (Solid black line is the simulation result and the dot gray line is the measurement result.)

Tuning voltage vs. Varactor capacitor

0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

0.80 0.90 1.00 1.10 1.20 1.30 1.40 1.50

Tuning voltage (V)

Capacitor value (pF)

C_ADS design kit C_TSMC Document Model

Fig. 3.15 The tuning voltage relative to the varactor capacitance

Tunning voltage vs. Frequency

5.0 6.0 7.0 8.0 9.0 10.0 11.0

0.80 0.90 1.00 1.10 1.20 1.30 1.40 1.50

Tuning voltage (V)

Center frequency (GHz)

sim._Cvar_w/design kit measurement sim._Cvar_w/document

Fig. 3.16 The tuning voltage relative to the center frequency. (the blue line with diamonds is the simulation with the ADS design lit, and the red line with triangles is the simulation with the model in TSMC document, and the green line with stars is the measurement data.)

4 5 6 7 8 9 10 11

3 12

-30 -20 -10

-40 0

Frequency (GHz)

S11 (dB)

Measurement Simulation

Trouble shooting

Fig. 3.17 S11 simulation and measured result of the tunable LNA.

5 6 7 8 9 10 11

4 12

-15 -10

-20 -5

freq, GHz

S22 (dB)

(a) simulation

(b) measurement

5 6 7 8 9 10 11

4 12

-15 -10

-20 -5

freq, GHz

S22 (dB)

(a) simulation

(b) measurement

Fig. 3.18 S22 simulation and measured result of the tunable LNA.

(a) The simulation result (b) The measurement result

Fig. 3.19 Noise Figure simulation result.

-5 -4 -3 -2 -1 0 1 2 3 4 5

0.9 0.95 1 1.05 1.1 1.15 1.2 1.25 1.3 1.35 1.4 1.45 1.5 Tuning Voltage (V)

IIP3 (dBm)

模 擬 IIP3 量 測 IIP3 Simulation IIP3 Measurement IIP3 -5

-4 -3 -2 -1 0 1 2 3 4 5

0.9 0.95 1 1.05 1.1 1.15 1.2 1.25 1.3 1.35 1.4 1.45 1.5 Tuning Voltage (V)

IIP3 (dBm)

模 擬 IIP3 量 測 IIP3 Simulation IIP3 Measurement IIP3

Fig. 3.20 IIP3 versus frequency simulation and measured result.

TABLE 3.2 Summary of measured performance and comparison to other tunable amplifier

Summary and Comparison Performance Simulation Measurement [5]

ISCAS 02

[6]

VLSI 04 Technology 0.18um CMOS Standard 0.25um CMOS

IBM

S21(max) 11.6 dB 7 dB (at 6.8GHz) 13.2 dB 11.7 dB

S11 <-9dB <-4 (5~7GHz)

<-9 ^(7~11GHz) -5.3dB <-10dB S22 <-12dB <-10 ^(5~7GHz) -10.3dB <-24dB

NF(average) 4.75 dB 5.7dB (at 6.8GHz) 2.59 dB 2.6 dB

IIP3(average) 1.15 dBm 3.2 dBm N/A -3.98 dBm

Center Frequency

tuning range 6.0 ~ 10.0 GHz 5.1~6.8 GHz 5.6 ~ 5.96

GHz 1.4 ~ 2.0 GHz Frequency tuning

ratio 50% 28% 6% 35%

Power

consumption 19.6 mW 19.51 mW 22.2 mW 40 mW

3.3 Improved 6 to 10GHz UWB Tunable LNA

Discussed in section 3.2, the frequency tunable range is narrower then simulation one. The tunable LNA is revised as shown in Fig. 3.21. The amended circuit incorporates not only enhanced band tuning range but also broadband impedance matching to improve noise performance. Since the input broadband matching in the previous circuit, Chebyshev filter design is used. The gate to source capacitor of the transconductance stage is included to consist of the Chebyshev filter.

Thus, the noise optimum mismatched as mentioned in section 3.2. The revised circuit achieves wideband input impedance matching by the resonance matching technique.

L1 and C1 are used to improve the input impedance matching bandwidth. A varactor, Cvar, and a switch capacitor, Csw, provide frequency tuning capability. M1 and M2

consist of cascode configuration to minimize the miller effect and to improve the isolation between the tunable load and broadband input impedance. M3 and M4

implement a source- follower output buffer. R1 and R2 are used to bias the buffer and the bypass capacitor is put on the gate of M4 to be an ac ground path. The transconductance (Gm) of the input stage must be designed to compensate the gain discrepancy between sub-bands.

L1 C₁

RF

in

L

g

RFout

Cpad

C

sw

C

var

V

gs

L

s

M

1

M2

M

3

M4

V

tune

V

sw

V

DD

C

pass

R

1

R

2

L

d

M

sw

C

pass

Fig. 3.21 The amended UWB tunable LNA schematic

3.3.1 Frequency Tunable Mechanism

The frequency tuning is enhanced by a switched capacitor at the output tunable load. This resonator consists of a fixed-value inductor, a tunable MOS

The frequency tuning is enhanced by a switched capacitor at the output tunable load. This resonator consists of a fixed-value inductor, a tunable MOS

在文檔中 應用於超寬頻系統之可調頻低雜訊放大器 (頁 23-0)