Chapter 1 Introduction
1.5 Thesis Organization
In Chapter 1, introduces the basic background knowledge of ESD protection design and the thesis organization.
In Chapter 2, novel dual-directional silicon-controlled rectifier (DDSCR) ESD protection devices will be introduced in detail. In this study, all testing devices are fabricated in 0.18um CMOS process.
In Chapter 3, novel high-voltage output driver is successfully verified in 0.18um CMOS process in the chapter, some simulation of the high-voltage output driver will be introduced. Next, the novel high-voltage output driver will also be equipped with the novel ESD protection devices to measure the ESD robustness of the circuits.
The last chapter, chapter 4, recapitulates the major consideration of this thesis and concludes with suggestions for future investigation.
13
Chapter 2
Novel Dual-Directional SCR in Output Stage with Monopolar Configuration
2.1 Introduction
CMOS technologies are attractive to implement the integrated circuits for biomedical electronics applications [24]-[26]. However, the transistors currently used in CMOS technologies are vulnerable to electrostatic discharge (ESD) events, which is the major reliability concern. In order to sustain the required ESD robustness, the on-chip ESD protection devices must be added in the IC products. A typical specification for a commercial IC on human-body-model (HBM) ESD robustness is 2 kV. If consider the reliability of biomedical integrated circuits used on the human, the required ESD robustness may be even higher.
The conventional ESD protection devices have the drawback of leakage current.
Fig. 2.1 shows the conventional ESD protection devices used in the CMOS technologies, including diode, gate-grounded NMOS (GGNMOS), silicon-controlled rectifier (SCR), and dual-directional SCR (DDSCR) [27]-[30]. A parasitic pn junction
exists in the conventional ESD protection devices with the common grounded P-substrate, as shown in Fig. 2.1.
In this chapter, a novel ESD protection design for output stage is investigated in a 0.18-um 1.8V/3.3V CMOS process.
14
Fig. 2.1. Cross-sectional view of conventional ESD protection devices: (a) diode, (b) GGNMOS, (c) SCR, and (d) DDSCR.
15
2.2 ESD Robustness of Stand-Alone Output Stage with monopolar configuration
The stacked PMOS and NMOS of the output stage of electrical stimulator are shown in Figs. 2.2(a) and 2.2(b), respectively. To investigate the I-V characteristics of the stand-alone output stage of electrical stimulator under ESD-like conditions, the transmission line pulsing (TLP) system with a 10-ns rise time and a 100-ns pulse width is used. The TLP-measured I-V curves of the test devices are shown in Fig. 2.3.
According to the test results, the stacked PMOS and NMOS under ESD-like conditions can sustain up to 27V and 25V, respectively, without damage (increasing leakage current). In other word, the additional ESD protection device must clamp the overshoot voltage lower than 25V to prevent the electrical stimulator from ESD damages.
16
Fig. 2.2. Cross-sectional view of output stage of electrical stimulator: (a) stacked PMOS and (b) stacked NMOS.
17
(a)
(b)
Fig. 2.3. Measured TLP I-V curves of (a) stacked PMOS and (b) stacked NMOS.
TLP Voltage (V)
18
2.3 ESD Protection Design for Output Stage
2.3.1 DDSCR-Based Devices for CMOS On-Chip ESD Protection
A typical SCR device provides only one direction ESD protection path. The dual-direction SCR (DDSCR) device can protect each I/O pad against ESD stress in the PS-mode (positive-to-VSS), NS-mode (negative-to-VDD), PD-mode (positive-to-VDD), and ND-mode (negative-to-VSS) [31]. The device structure of a DDSCR device illustrated in Fig. 2.4(a) is a symmetrical five-layer NPNPN structure comprising two vertical NPN and one lateral PNP. Adding another layer of N+ isolation can avoid leakage current issue of conventional ESD devices.
When a positive ESD pulse is applied to the anode of DDSCR and its cathode is relatively grounded. The positive ESD current can be discharged through the current path1 is shown in Fig. 2.4(b). Similarly, when a negative ESD pulse is applied to anode of DDSCR with its cathode grounded, the negative ESD current can be discharged through the current path2 is shown in Fig. 2.4(b). The DDSCR provides low holding voltage and low impedance path to discharge the ESD current under every stress mode.
19
Fig. 2.4 (a) The cross-sectional view of the dual-direction SCR structure, (b) Equivalent circuit schematic of a SCR device.
STI STI
20
2.3.2 Novel Dual-Directional SCR
In this work, a novel dual-directional SCR (DDSCR) device for ESD protection in biphasic output driver was proposed. This design can achieve low leakage, large swing tolerance, and high ESD robustness.
Two kinds of layout of the DDSCR device are shown in Fig. 2.5. In the Figs. 2.5(a) and 5(b), the SCR paths are divided into 4 and 8 segments, respectively. The SCR paths consist of P+/P-well/N-well/P-well/N+. The SCR paths along A-A' and B-B' provide the discharging path from I/O to GND and from GND to I/O, respectively, as shown in Fig. 2.6. The distance between I/O and GND of SCR is wished to be minimized, so the layout style with minimized “d” is used. The test devices have been fabricated in a 0.18-um 1.8-V CMOS process. All the dimensions of test devices are listed in Table 2.2.
P+
Fig. 2.5. Layout top view of DDSCR1 with (a) 4 segments and (b) 8 segments.
21
In order to reduce the switching voltage of DDSCR1 device to provide more effective ESD protection for the internal circuits, the DDSCR2 and DDSCR3 was invented. The devices structure of the DDSCR2 and DDSCR3 are illustrated in Fig. 2.7 and Fig. 2.8.
The DDSCR2 and DDSCR3 devices are made by adding an N+ diffusion is inserted into the N-well to lower the avalanche breakdown voltage of N-well/P-well junction.
The inserted N+ diffusions are connected out as the n-trigger nodes of the DDSCR2 and DDSCR3 devices. Fig. 2.6. Cross-sectional view of DDSCR1along (a) A-A' and (b) B-B'.
S Fig. 2.7. Cross-sectional view of DDSCR2 along (a) A-A' and (b) B-B'.
22 Fig. 2.8. Cross-sectional view of DDSCR3 along (a) A-A' and (b) B-B'.
2.4 Experimental Results of novel DDSCR
2.4.1 Measured TLP I-V Characteristics
To investigate the turn-on behavior and the I-V characteristics in high-current regions of the ESD protection devices, the transmission-line-pulsing (TLP) system with 10-ns rise time and 100-ns pulse width is used. The TLP-measured I-V characteristics are shown in Figs. 2.9~2.11. The trigger voltages (Vt1) of the test devices are about 9~12V, which means the ESD protection devices can sustain the signal swing up to ±9V. The secondary breakdown current (It2) of ESD protection device, which indicated the current-handling ability, can also be obtained from the TLP-measured I-V curves. All these measurement results are also listed in Table 2.3.
23
(a)
(b)
Fig. 2.9. Measured TLP I-V curves of DDSCR1 with (a) 4 segments and (b) 8 segments.
DDSCR1
24
(a)
(b)
Fig. 2.10. Measured TLP I-V curves of DDSCR2 with (a) 4 segments and (b) 8 segments.
TLP Voltage (V)
25
(a)
(b)
Fig. 2.11. Measured TLP I-V curves of DDSCR3 with (a) 4 segments and (b) 8 segments.
TLP Voltage (V)
26
2.4.2 Measured DC I-V Characteristics
In order to further ascertain the possibility of the parasitic bipolar to reach and maintain holding state, relationship between power supply voltage and holding voltage need to be explored. In this work, the snapback holding voltage of novel DDSCR devices, have been investigated by curve tracer, the measurement was carried out with Tektronix 370A curve tracer as shown in Fig. 2.12~ 2.17. All these measurement results are listed in Table 2.1.
Fig. 2.12. I-V characteristics of DDSCR1 with 4 segments measured by dc curve tracer.
27
Fig. 2.13. I-V characteristics of DDSCR1 with 8 segments measured by dc curve tracer.
Fig. 2.14. I-V characteristics of DDSCR2 with 4 segments measured by dc curve tracer.
28
Fig. 2.15. I-V characteristics of DDSCR2 with 8 segments measured by dc curve tracer.
Fig. 2.16. I-V characteristics of DDSCR3 with 4 segments measured by dc curve tracer.
29
Fig. 2.17. I-V characteristics of DDSCR3 with 8 segments measured by dc curve tracer.
Table 2.1
The I-V characteristics of the DDSCR measured results by DC curve tracer.
Test
30
2.4.3 Measured ESD Robustness
The ESD robustness of test devices are evaluated by the HBM tester. The failure criterion is defined as the I-V characteristics shifting over 30 % from its original curve after ESD stressed at every ESD test level. All these measurement results are listed in Table 2.3.
2.4.4 Measured Parasitic Capacitance
With the on-wafer measurement, the two-port S-parameters of the test devices were measured by using the vector network analyzer. The parasitic effects of the pads have been removed by using the de-embedding technique [32]. The parasitic capacitance of each test device can be extracted from the S-parameters. Fig. 2.12 shows the extracted parasitic capacitance of the test devices.
Fig. 2.18. Measured parasitic capacitances.
31
Table 2.2
Design parameters of test devices Test
32
Table 2.3
Measurement results of test devices Test
33
2.4.5 Document Comparison of DDSCR
The comparison among various DDSCR-based devices for CMOS on-chip ESD protection has been summarized in Table 2.4. The trigger voltage (Vt1) and the holding voltage (Vh) of DDSCR-based devices must be finely designed to fully and effectively protect the output stage.
Table 2.4
Comparison among the DDSCR-based devices for on-chip ESD protection Test
Device Technology W (um) protection in output driver. Verified in 0.18-um CMOS process, this design can achieve low leakage, large swing tolerance, and high ESD robustness.
34
Chapter 3
Novel Embedded SCR Device in Output Stage with Bipolar Configuration
3.1 Introduction
In nanoscale CMOS technologies, the feature size has been scaled down to improve circuit performances with the decreased power supply voltage for low-power applications. However, the higher output voltage levels are still needed for the external I/O to communicate with other circuits in the microelectronic systems or subsystems, such as 3.3V or 5V for some signaling standards. Even higher output voltage levels are needed for some applications, such as >10V for display driver and biomedical stimulator. Therefore, the high-voltage output driver must be designed with the consideration of high-voltage tolerance [33], [34]. To avoid the overstress issue without using additional high-voltage device, stacking low-voltage devices is usually used for the high-voltage output driver [35]-[37]. Once the voltage drop divided equally across the stacked devices, this configuration allows for higher voltage, and no single device is overstressed. A conventional 3xVDD-tolerant stacked-device output driver is shown in Fig. 3.1, which consists of a control circuit and a pair of triply-stacked MOS in the output stage [38], [39].
35
Electrostatic discharge (ESD), which is the significant reliability issue, may cause the damage in IC products. The transistors currently used in CMOS technologies are vulnerable to ESD events. To provide the required ESD robustness, on-chip ESD protection design must be added in the integrated circuits, including the output driver [40]. For example, a typical specification for a commercial IC on HBM ESD robustness is 2kV. With the help of high-voltage-tolerant ESD clamp circuit [41]-[43] and the parasitic body-to-drain diodes, the on-chip ESD protection for stacked-device output driver is shown in Fig. 3.2. The ESD currents can be discharged from VOUT to 3xVDD
(path ①), from GND to VOUT (path ②), from VOUT to GND (path ①+③), and from 3×VDD to VOUT (path ④ + ② ). This ESD protection design can provide the corresponding ESD current paths during all kinds of ESD events at VOUT pad. However, in the output stage, the sizes of PMOS devices are usually larger than those of NMOS devices to have symmetrical driving ability, which makes the asymmetrical ESD current paths. With the smaller NMOS devices, the ESD robustness of path ② is usually lower than that of path ①. Of course, the designer can use some dummy NMOS devices or additional ESD diodes to improve the ESD robustness. In this work, a more efficient design by using embedded silicon-controlled rectifier (SCR) to improve ESD robustness is proposed. With the assistance of embedded SCR, the ESD robustness of NMOS part of stacked-device output driver can be improved without using any additional ESD protection device and layout area.
36
Fig. 3.1. Block diagram of 3xVDD-tolerant stacked-device output driver.
MP0
Fig. 3.2. ESD current paths in 3xVDD-tolerant stacked-device output driver with high-voltage-tolerant ESD clamp circuit.
37
3.2 Design of Novel High Voltage Output Driver
Fig. 3.3 shows the design of high voltage output driver, which consists of bias circuit, control circuit, and output stage. The 3.3V transistors in a standard 0.18μm CMOS process are used. Once the voltage differences across each transistor are lower than 3.63V (3.3V + 10%) [48], the foundry promises their reliability. The output driver is controlled by the input signal (VIN) with voltage swing between 0V and 3.3V. The aims of this design are that the output signal (VOUT) can swing between 0 and ~10V (3xVDD), and the voltage differences across each transistor are lower than 3.63V to prevent from reliability issues, whether the output driver is turned on or off. In order to sustain the high voltage (~10V) without gate-oxide overstress, the stacked MOS configuration between 3xVDD and ground is used. The bias circuit, which consists of three PMOS- diodes (MR1~MR3), is used to provide the biases of 2xVDD (VDD2) and 1xVDD (VDD1) from the 3xVDD. To reduce the bias current to the range of < mA, three PMOS with small width/length ratio are used. The control circuit includes two level shifters, and three buffers. The level shifters 1 and 2 transfer the signals with low-voltage level (1xVDD) to the high-voltage levels (2xVDD and 3xVDD). The level shifter 1 with differential structure can transfer the VIN and Vi1a (voltage swing: 0V ~ 1xVDD) to Vi2
and Vi2b (voltage swing: 1xVDD ~ 2xVDD). Similarly, the level shifter 2 can further transfer the Vi2 and Vi2b to Vi3 (voltage swing: 2xVDD ~ 3xVDD). The buffers control the output stage to turn on or off.
38
39
As VIN is 0V, the gate potentials of MP0, MP1, and MP2 are designed to be 1xVDD, 2xVDD, and 3xVDD, respectively, so the stacked PMOS are kept off. In the meantime, the gate potentials of MN0, MN1, and MN2 are all 1xVDD, so the stacked NMOS conduct the VOUT to 0V. As VIN is 3.3V, the gate potentials of MN0, MN1, and MN2 are 2xVDD, 1xVDD, and 0V, respectively, so the stacked NMOS are kept off. In the meantime, the gate potentials of MP0, MP1, and MP2 are all 2xVDD, so the stacked PMOS conduct the VOUT to 3xVDD. Shown in Fig. 3.4 is the schematic of a triply-stacked output driver that enables voltage drive up to 3x the transistor rating. Both scenarios are better depicted by the schematics in Fig. 3.4(b) and 3.4(c). Simple device stacking as explained poses certain reliability risks during switching transitions.
(a) (b) (c) Fig. 3.4. (a) A triply-stacked output driver (b) high-level drive (c) low-level drive.
MP0
40
The stacked-device output driver has been simulated in HSPICE with the 0.18μm CMOS process. Fig. 3.5 ~ 3.7 shows the simulated transient waveforms of stacked-device output driver. As long as the VIN is 0V or 3.3V, the Vi1a is inverted instantaneously. The Vi2, Vi2a, and Vi2b swing between 3.3V and 6.6V, the Vi3a swing between 6.6V and 9.9V, and the VOUT finally swings between 0V and 9.9V.
Fig. 3.5. Simulated transient waveforms of high voltage output driver with VIN-VOUT. Time (us)
0 100 200 300 400 500
Voltage (V)
0 2 4 6 8 10
VIN VOUT
41
Fig. 3.6. Simulated transient waveforms of high voltage output driver with Vi2-Vi2b.
Fig. 3.7. Simulated transient waveforms of high voltage output driver with Vi1a-Vi2a-Vi3a.
Time (us)
0 100 200 300 400 500
Voltage (V)
3 4 5 6 7
Vi2
Vi2b
Time (us)
0 100 200 300 400 500
Voltage (V)
0 2 4 6 8 10
Vi1a Vi2a Vi3a
42
To verify the voltage differences across each transistor are lower than 3.63V during all VIN potentials, a ramp voltage from 0V to 3.3V is injected into VIN, and then the voltage of each node is captured. Fig. 3.8 shows the simulated |Vgd|, |Vgs|, and |Vds|, of each transistor, as the VIN is between 0V and 3.3V. For the MN2, each terminal is constrained to swing between 0V and 1xVDD, as shown in Fig. 3.8(a). For the MN1, its gate potential is kept at 1xVDD, its source potential is constrained to swing between 0V and 1xVDD, and its drain potential will swing between 0V and 2xVDD. Even though, the voltage differences across each terminals of MN1 are still lower than 3.63V, as shown in Fig. 3.8(b). For the MN0, its gate potential will swing between 1xVDD and 2xVDD, its source potential will swing between 0V and 2xVDD, and its drain potential will swing between 0V and 3xVDD. The simulation results show that the voltage differences across each terminals of MN0 are still lower than 3.63V, as shown in Fig. 3.8(c). The operations of MP0~MP2 are complementary to those of MN0~MN2, so the similar results can be found, as shown in Figs. 3.8(d) ~ 3.8(f).
43
(a) (b)
(c) (d)
(e) (f)
Fig. 3.8. Simulated |Vgd|, |Vgs|, and |Vds|, of transistors in output stage: (a) MN2, (b) MN1, (c) MN0, (d) MP0, (e) MP1, and (f) MP2.
44
With the proper design of control circuit, the PMOS and NMOS transistors in output stage are well controlled to turn on or off. The simulation results show that the voltage differences across each transistor are 3.63V at most, which meets the design target.
Although the stacked-device output driver with embedded SCR can’t be simulated, its transient behaviors should be equal to the output driver without embedded SCR, since the additional P+ region in the proposed design will not affect the operation of drain, gate, source, and body terminals of three NMOS devices during normal operation.
3.3 Proposed ESD Protection Design for Stacked-Device Output Driver
The cross-sectional view of NMOS part in output stage of conventional 3xVDD -tolerant stacked-device output driver is shown in Fig. 3.9. The N-well and deep N-well regions are used to isolate the P-well region of each stacked NMOS from the common P-substrate. The body-to-drain (P-well/N+) diodes form the ESD current path from GND to Vo. Besides, a parasitic SCR (P-well/Deep N-well/P-well/N+) can also help to discharge the ESD current from GND to VOUT, but its path is too long to effectively discharge the ESD current.
45
Fig. 3.9. Cross-sectional view of stacked NMOS devices in output stage of conventional 3xVDD-tolerant stacked-device output driver.
To have symmetrical ESD protection ability in PMOS and NMOS parts, a stacked-device output driver with embedded SCR is proposed, as shown in Fig. 3.10. In the proposed design, additional P+ region is added into the N-well region, and then an embedded SCR device is formed from GND to VOUT. Since the existing N-well region is usually large enough to contain the additional P+ region, this design will not increase the layout area. Besides, the SCR device can be safely used without latchup danger in the proposed design, since the anode (GND) potential is always lower than the cathode (VOUT) potential during normal operation, and the SCR device can’t keep turning on.
The SCR device has been reported to be useful for ESD protection. The equivalent circuit of the embedded SCR consists of the cross-coupled PNP (P+/N-well/P-well) and NPN (N-well/P-well/N+) BJTs. In the proposed design, the body-to-drain (P-well/N+) diodes play the role of trigger circuit of embedded SCR to enhance the turn-on speed.
As ESD stresses from anode (GND) to cathode (VOUT) of the SCR are applied, the diode path will turn on to discharge the initial ESD currents, and then the SCR path will take over to discharge the primary ESD currents. The positive-feedback regenerative
46
mechanism of PNP and NPN BJTs results in the SCR device becoming highly conductive to make the SCR very robust against ESD stresses.
P-Well
Fig. 3.10. Cross-sectional view of stacked NMOS devices with additional P+ region in output stage of proposed 3×VDD-tolerant stacked-device output driver with embedded SCR.
This research designed 2 kinds of high-voltage output driver, contains without ESD protective element of the driver, and the driver in the output stage with embedded SCR.
The driver match output stage of different sizes to explore the characteristics of electrostatic discharge protection design. Comparison of three different sizes, are used in the output stage of the driver, in output stage finger to change the number of transistors. In order to investigate the reliability of related problems, this study also designed test circuit as shown in Table 3.1.
47
Table 3.1.
Design parameters of the test circuits
3.4 Experimental Results
To verify the stacked-device output driver in silicon chip, both circuits without and with embedded SCR (pure output driver and driver with embedded SCR) have been fabricated in 0.18μm CMOS process. Each circuit occupies a chip area is less than 250×175μm2, including 3xVDD, GND, VIN, and VOUT pads without high-voltage-tolerant ESD clamp circuit.
Test
48
3.4.1 Transient Waveforms
A 9.9V supply voltage is used for 3xVDD, a 3.3V and 10kHz square wave is applied to VIN, a 100kΩ resistance is loaded to VOUT, and then the VOUT swing is measured, as shown in Fig. 3.11 ~ 3.18. Fig. 3.11 ~ 3.13 shows the measured waveforms of general stacked-device output driver (pure output driver), and Fig. 3.14~ 3.18 shows those of proposed stacked-device output driver with SCR (driver with embedded SCR). As long as the VIN is 0V or 3.3V, the VOUT of both circuits can swing between 0V and ~9.7V.
A 9.9V supply voltage is used for 3xVDD, a 3.3V and 10kHz square wave is applied to VIN, a 100kΩ resistance is loaded to VOUT, and then the VOUT swing is measured, as shown in Fig. 3.11 ~ 3.18. Fig. 3.11 ~ 3.13 shows the measured waveforms of general stacked-device output driver (pure output driver), and Fig. 3.14~ 3.18 shows those of proposed stacked-device output driver with SCR (driver with embedded SCR). As long as the VIN is 0V or 3.3V, the VOUT of both circuits can swing between 0V and ~9.7V.