Document Comparison of DDSCR - Experimental Results of novel DDSCR

Chapter 2 Novel Dual-Directional SCR in Output Stage

2.4 Experimental Results of novel DDSCR

2.4.5 Document Comparison of DDSCR

The comparison among various DDSCR-based devices for CMOS on-chip ESD protection has been summarized in Table 2.4. The trigger voltage (Vt1) and the holding voltage (Vh) of DDSCR-based devices must be finely designed to fully and effectively protect the output stage.

Table 2.4

Comparison among the DDSCR-based devices for on-chip ESD protection Test

Device Technology W (um) protection in output driver. Verified in 0.18-um CMOS process, this design can achieve low leakage, large swing tolerance, and high ESD robustness.

Chapter 3 Novel Embedded SCR Device in Output Stage with Bipolar Configuration

3.1 Introduction

In nanoscale CMOS technologies, the feature size has been scaled down to improve circuit performances with the decreased power supply voltage for low-power applications. However, the higher output voltage levels are still needed for the external I/O to communicate with other circuits in the microelectronic systems or subsystems, such as 3.3V or 5V for some signaling standards. Even higher output voltage levels are needed for some applications, such as >10V for display driver and biomedical stimulator. Therefore, the high-voltage output driver must be designed with the consideration of high-voltage tolerance [33], [34]. To avoid the overstress issue without using additional high-voltage device, stacking low-voltage devices is usually used for the high-voltage output driver [35]-[37]. Once the voltage drop divided equally across the stacked devices, this configuration allows for higher voltage, and no single device is overstressed. A conventional 3xVDD-tolerant stacked-device output driver is shown in Fig. 3.1, which consists of a control circuit and a pair of triply-stacked MOS in the output stage [38], [39].

Electrostatic discharge (ESD), which is the significant reliability issue, may cause the damage in IC products. The transistors currently used in CMOS technologies are vulnerable to ESD events. To provide the required ESD robustness, on-chip ESD protection design must be added in the integrated circuits, including the output driver [40]. For example, a typical specification for a commercial IC on HBM ESD robustness is 2kV. With the help of high-voltage-tolerant ESD clamp circuit [41]-[43] and the parasitic body-to-drain diodes, the on-chip ESD protection for stacked-device output driver is shown in Fig. 3.2. The ESD currents can be discharged from VOUT to 3xVDD

(path ①), from GND to VOUT (path ②), from VOUT to GND (path ①+③), and from 3×VDD to VOUT (path ④ + ② ). This ESD protection design can provide the corresponding ESD current paths during all kinds of ESD events at VOUT pad. However, in the output stage, the sizes of PMOS devices are usually larger than those of NMOS devices to have symmetrical driving ability, which makes the asymmetrical ESD current paths. With the smaller NMOS devices, the ESD robustness of path ② is usually lower than that of path ①. Of course, the designer can use some dummy NMOS devices or additional ESD diodes to improve the ESD robustness. In this work, a more efficient design by using embedded silicon-controlled rectifier (SCR) to improve ESD robustness is proposed. With the assistance of embedded SCR, the ESD robustness of NMOS part of stacked-device output driver can be improved without using any additional ESD protection device and layout area.

Fig. 3.1. Block diagram of 3xVDD-tolerant stacked-device output driver.

MP0

Fig. 3.2. ESD current paths in 3xVDD-tolerant stacked-device output driver with high-voltage-tolerant ESD clamp circuit.

3.2 Design of Novel High Voltage Output Driver

Fig. 3.3 shows the design of high voltage output driver, which consists of bias circuit, control circuit, and output stage. The 3.3V transistors in a standard 0.18μm CMOS process are used. Once the voltage differences across each transistor are lower than 3.63V (3.3V + 10%) [48], the foundry promises their reliability. The output driver is controlled by the input signal (VIN) with voltage swing between 0V and 3.3V. The aims of this design are that the output signal (VOUT) can swing between 0 and ~10V (3xVDD), and the voltage differences across each transistor are lower than 3.63V to prevent from reliability issues, whether the output driver is turned on or off. In order to sustain the high voltage (~10V) without gate-oxide overstress, the stacked MOS configuration between 3xVDD and ground is used. The bias circuit, which consists of three PMOS- diodes (MR1~MR3), is used to provide the biases of 2xVDD (VDD2) and 1xVDD (VDD1) from the 3xVDD. To reduce the bias current to the range of < mA, three PMOS with small width/length ratio are used. The control circuit includes two level shifters, and three buffers. The level shifters 1 and 2 transfer the signals with low-voltage level (1xVDD) to the high-voltage levels (2xVDD and 3xVDD). The level shifter 1 with differential structure can transfer the VIN and Vi1a (voltage swing: 0V ~ 1xVDD) to Vi2

and Vi2b (voltage swing: 1xVDD ~ 2xVDD). Similarly, the level shifter 2 can further transfer the Vi2 and Vi2b to Vi3 (voltage swing: 2xVDD ~ 3xVDD). The buffers control the output stage to turn on or off.

As VIN is 0V, the gate potentials of MP0, MP1, and MP2 are designed to be 1xVDD, 2xVDD, and 3xVDD, respectively, so the stacked PMOS are kept off. In the meantime, the gate potentials of MN0, MN1, and MN2 are all 1xVDD, so the stacked NMOS conduct the VOUT to 0V. As VIN is 3.3V, the gate potentials of MN0, MN1, and MN2 are 2xVDD, 1xVDD, and 0V, respectively, so the stacked NMOS are kept off. In the meantime, the gate potentials of MP0, MP1, and MP2 are all 2xVDD, so the stacked PMOS conduct the VOUT to 3xVDD. Shown in Fig. 3.4 is the schematic of a triply-stacked output driver that enables voltage drive up to 3x the transistor rating. Both scenarios are better depicted by the schematics in Fig. 3.4(b) and 3.4(c). Simple device stacking as explained poses certain reliability risks during switching transitions.

(a) (b) (c) Fig. 3.4. (a) A triply-stacked output driver (b) high-level drive (c) low-level drive.

MP0

The stacked-device output driver has been simulated in HSPICE with the 0.18μm CMOS process. Fig. 3.5 ~ 3.7 shows the simulated transient waveforms of stacked-device output driver. As long as the VIN is 0V or 3.3V, the Vi1a is inverted instantaneously. The Vi2, Vi2a, and Vi2b swing between 3.3V and 6.6V, the Vi3a swing between 6.6V and 9.9V, and the VOUT finally swings between 0V and 9.9V.

Fig. 3.5. Simulated transient waveforms of high voltage output driver with VIN-VOUT. Time (us)

0 100 200 300 400 500

Voltage (V)

0 2 4 6 8 10

V^IN V^OUT

Fig. 3.6. Simulated transient waveforms of high voltage output driver with Vi2-Vi2b.

Fig. 3.7. Simulated transient waveforms of high voltage output driver with Vi1a-Vi2a-Vi3a.

Time (us)

0 100 200 300 400 500

Voltage (V)

3 4 5 6 7

Vi2

V^i2b

Time (us)

0 100 200 300 400 500

Voltage (V)

0 2 4 6 8 10

V^i1a V^i2a Vi3a

To verify the voltage differences across each transistor are lower than 3.63V during all VIN potentials, a ramp voltage from 0V to 3.3V is injected into VIN, and then the voltage of each node is captured. Fig. 3.8 shows the simulated |Vgd|, |Vgs|, and |Vds|, of each transistor, as the VIN is between 0V and 3.3V. For the MN2, each terminal is constrained to swing between 0V and 1xVDD, as shown in Fig. 3.8(a). For the MN1, its gate potential is kept at 1xVDD, its source potential is constrained to swing between 0V and 1xVDD, and its drain potential will swing between 0V and 2xVDD. Even though, the voltage differences across each terminals of MN1 are still lower than 3.63V, as shown in Fig. 3.8(b). For the MN0, its gate potential will swing between 1xVDD and 2xVDD, its source potential will swing between 0V and 2xVDD, and its drain potential will swing between 0V and 3xVDD. The simulation results show that the voltage differences across each terminals of MN0 are still lower than 3.63V, as shown in Fig. 3.8(c). The operations of MP0~MP2 are complementary to those of MN0~MN2, so the similar results can be found, as shown in Figs. 3.8(d) ~ 3.8(f).

(a) (b)

(e) (f)

Fig. 3.8. Simulated |Vgd|, |Vgs|, and |Vds|, of transistors in output stage: (a) MN2, (b) MN1, (c) MN0, (d) MP0, (e) MP1, and (f) MP2.

With the proper design of control circuit, the PMOS and NMOS transistors in output stage are well controlled to turn on or off. The simulation results show that the voltage differences across each transistor are 3.63V at most, which meets the design target.

Although the stacked-device output driver with embedded SCR can’t be simulated, its transient behaviors should be equal to the output driver without embedded SCR, since the additional P+ region in the proposed design will not affect the operation of drain, gate, source, and body terminals of three NMOS devices during normal operation.

3.3 Proposed ESD Protection Design for Stacked-Device Output Driver

The cross-sectional view of NMOS part in output stage of conventional 3xVDD -tolerant stacked-device output driver is shown in Fig. 3.9. The N-well and deep N-well regions are used to isolate the P-well region of each stacked NMOS from the common P-substrate. The body-to-drain (P-well/N+) diodes form the ESD current path from GND to Vo. Besides, a parasitic SCR (P-well/Deep N-well/P-well/N+) can also help to discharge the ESD current from GND to VOUT, but its path is too long to effectively discharge the ESD current.

Fig. 3.9. Cross-sectional view of stacked NMOS devices in output stage of conventional 3xVDD-tolerant stacked-device output driver.

To have symmetrical ESD protection ability in PMOS and NMOS parts, a stacked-device output driver with embedded SCR is proposed, as shown in Fig. 3.10. In the proposed design, additional P+ region is added into the N-well region, and then an embedded SCR device is formed from GND to VOUT. Since the existing N-well region is usually large enough to contain the additional P+ region, this design will not increase the layout area. Besides, the SCR device can be safely used without latchup danger in the proposed design, since the anode (GND) potential is always lower than the cathode (VOUT) potential during normal operation, and the SCR device can’t keep turning on.

The SCR device has been reported to be useful for ESD protection. The equivalent circuit of the embedded SCR consists of the cross-coupled PNP (P+/N-well/P-well) and NPN (N-well/P-well/N+) BJTs. In the proposed design, the body-to-drain (P-well/N+) diodes play the role of trigger circuit of embedded SCR to enhance the turn-on speed.

As ESD stresses from anode (GND) to cathode (VOUT) of the SCR are applied, the diode path will turn on to discharge the initial ESD currents, and then the SCR path will take over to discharge the primary ESD currents. The positive-feedback regenerative

mechanism of PNP and NPN BJTs results in the SCR device becoming highly conductive to make the SCR very robust against ESD stresses.

P-Well

Fig. 3.10. Cross-sectional view of stacked NMOS devices with additional P+ region in output stage of proposed 3×VDD-tolerant stacked-device output driver with embedded SCR.

This research designed 2 kinds of high-voltage output driver, contains without ESD protective element of the driver, and the driver in the output stage with embedded SCR.

The driver match output stage of different sizes to explore the characteristics of electrostatic discharge protection design. Comparison of three different sizes, are used in the output stage of the driver, in output stage finger to change the number of transistors. In order to investigate the reliability of related problems, this study also designed test circuit as shown in Table 3.1.

Table 3.1.

Design parameters of the test circuits

3.4 Experimental Results

To verify the stacked-device output driver in silicon chip, both circuits without and with embedded SCR (pure output driver and driver with embedded SCR) have been fabricated in 0.18μm CMOS process. Each circuit occupies a chip area is less than 250×175μm², including 3xVDD, GND, VIN, and VOUT pads without high-voltage-tolerant ESD clamp circuit.

Test

3.4.1 Transient Waveforms

A 9.9V supply voltage is used for 3xVDD, a 3.3V and 10kHz square wave is applied to VIN, a 100kΩ resistance is loaded to VOUT, and then the VOUT swing is measured, as shown in Fig. 3.11 ~ 3.18. Fig. 3.11 ~ 3.13 shows the measured waveforms of general stacked-device output driver (pure output driver), and Fig. 3.14~ 3.18 shows those of proposed stacked-device output driver with SCR (driver with embedded SCR). As long as the VIN is 0V or 3.3V, the VOUT of both circuits can swing between 0V and ~9.7V.

Fig. 3.11. Measured transient waveforms of general 3xVDD-tolerant stacked-device output driver in Output Driver_10.

Fig. 3.12. Measured transient waveforms of general 3xVDD-tolerant stacked-device output driver in Output Driver_30.

Fig. 3.13. Measured transient waveforms of general 3xVDD-tolerant stacked-device output driver in Output Driver_50.

Fig. 3.14. Measured transient waveforms of proposed 3xVDD-tolerant stacked-device output driver with embedded SCR in Driver + SCR_10_10.

Fig. 3.15. Measured transient waveforms of proposed 3xVDD-tolerant stacked-device output driver with embedded SCR in Driver + SCR_30_10.

Driver + SCR_30_10

Time (s)

0 50x10^-6 100x10^-6 150x10^-6 200x10^-6

Voltage (V)

0 2 4 6 8 10

VIN

VOUT

Fig. 3.16. Measured transient waveforms of proposed 3xVDD-tolerant stacked-device output driver with embedded SCR in Driver + SCR_50_10.

Fig. 3.17. Measured transient waveforms of proposed 3xVDD-tolerant stacked-device output driver with embedded SCR in Driver + SCR_30_30.

Driver + SCR_50_10

Time (s)

0 50x10^-6 100x10^-6 150x10^-6 200x10^-6

Voltage (V)

0 2 4 6 8 10

V^IN V^OUT

Fig. 3.18. Measured transient waveforms of proposed 3xVDD-tolerant stacked-device output driver with embedded SCR in Driver + SCR_50_50.

3.4.2 ESD Robustness and TLP I-V Characteristics

The HBM ESD robustness of each circuit is evaluated by the HBM tester. The failure criterion is defined as the I-V characteristics shifting over 30 % from its original curve after ESD stressed at every ESD test level. According to the measurement results, the VOUT-to-3xVDD ESD robustness of both circuits are more than 1.25kV. The GND-to-VOUT ESD robustness of general stacked-device output driver (Output Driver_10 and Output Driver_30) are 0.75kV, while that of proposed stacked-device output driver with embedded SCR (Driver + SCR_10_10 and Driver + SCR_30_10) are improved to 1.75kV and 2.25kV, respectively, the GND-to-VOUT ESD robustness of general device output driver (Output Driver_50) is 1.25kV, while that of proposed stacked-device output driver with embedded SCR is improved to 2.50kV. All these HBM measurement results are listed in Table 3.2.

Table 3.2

HBM ESD robustness of test circuits

Test Circuits

HBM Level

GND-to-VOUT VOUT–to-3xVDD

Pure Output Driver

Output Driver_10 750V 1250V

Output Driver_30 750V 1250V

Output Driver_50 1250V 1500V

Driver with Embedded

SCR

Driver + SCR_10_10 1750V 1250V

Driver + SCR_30_10 2250V 1250V

Driver + SCR_50_10 2500V 1750V

Driver + SCR_30_30 4000V 3500V

Driver + SCR_50_50 4500V 4000V

To investigate the turn-on behavior and the I-V characteristics of the circuits in the domain of HBM ESD event, the transmission-line-pulsing (TLP) system with a 10ns rise time and a 100ns pulse width is used. The current-handling ability, i.e. the secondary breakdown current (It2), of test circuit can be obtained from the

TLP-measured I-V curves. The TLP-TLP-measured I-V curves of test circuits are shown in Fig. 3.19 ~ 3.28. As measuring from VOUT to 3xVDD, the test circuits of Output

Driver_10 and Driver + SCR_10_10 have almost the same TLP I-V characteristics, and the TLP-measured It2 are ~0.85A, the test circuits of Output Driver_30 and Driver + SCR_30_10 have almost the same TLP I-V characteristics, and the TLP-measured It2

are ~1.03A, the test circuits of Output Driver_50 and Driver + SCR_50_10 have almost the same TLP I-V characteristics, and the TLP-measured It2 are ~1.20A, the test circuits

of Driver + SCR_30_30 and Driver + SCR_50_50 can achieve the TLP-measured (It2) of 2.16A and 3.29A, respectively. As measuring from GND to VOUT, the embedded SCR in the proposed design can be triggered lower than ~2.5V, and then be latched to

~1.5V. The GND-to-VOUT It2 of general stacked-device output driver (Output Driver_10, Output Driver_30, and Output Driver_50) are 0.47A, 0.77A, and 1.02A, respectively, while that of proposed stacked-device output driver with embedded SCR (Driver + SCR_10_10, Driver + SCR_30_10, and Driver + SCR_50_10) are improved to 0.81A, 0.97A, and 1.26A, respectively, the test circuits of Driver + SCR_30_30, and Driver + SCR_50_50 can achieve the TLP-measured (It2) of 2.29A and 3.51A, respectively.

Fig. 3.19. Measured TLP I-V curves of Output Driver_10 and Driver + SCR_10_10, as zapping from VOUT to 3xVDD.

V

OUT

-to-3xV

TLP Voltage (V)

0 2 4 6 8 10 12 14

TLP Current (A)

0.0 0.2 0.4 0.6 0.8 1.0 1.2

Output Driver_10 Driver + SCR_10_10

Fig. 3.20. Measured TLP I-V curves of Output Driver_10 and Driver + SCR_10_10, as zapping from GND to VOUT.

Fig. 3.21. Measured TLP I-V curves of Output Driver_30 and Driver + SCR_30_10, as zapping from VOUT to 3xVDD.

GND-to-V

OUT

TLP Voltage (V)

0 2 4 6 8 10

TLP Current (A)

0.0 0.2 0.4 0.6 0.8 1.0

Output Driver_10 Driver + SCR_10_10

Fig. 3.22. Measured TLP I-V curves of Output Driver_30 and Driver + SCR_30_10, as zapping from GND to VOUT.

Fig. 3.23. Measured TLP I-V curves of Output Driver_50 and Driver + SCR_50_10, as zapping from VOUT to 3xVDD.

Fig. 3.24. Measured TLP I-V curves of Output Driver_50 and Driver + SCR_50_10, as zapping from GND to VOUT.

Fig. 3.25. Measured TLP I-V curves of Output Driver_30 and Driver + SCR_30_30, as zapping from VOUT to 3xVDD.

Fig. 3.26. Measured TLP I-V curves of Output Driver_30 and Driver + SCR_30_30, as zapping from GND to VOUT.

Fig. 3.27. Measured TLP I-V curves of Output Driver_50 and Driver + SCR_50_50, as zapping from VOUT to 3xVDD.

Fig. 3.28. Measured TLP I-V curves of Output Driver_50 and Driver + SCR_50_50, as zapping from GND to VOUT.

In order to investigate the reliability of driver and ESD protection device, using 3 different dimensions in the output stage to collocation the different size with embedded SCR. TLP measurement results as shown in Fig. 3.29.

Fig. 3.29. Measured TLP I-V curves, as zapping from GND to VOUT of driver with embedded SCR.

As measuring from VOUT to GND, the test circuits of Output Driver_10, Output Driver_30, and Output Driver_50 can achieve the TLP-measured It2 of 0.32A, 0.28A, and 0.33A, respectively as shown in Fig.3.30.

Fig. 3.30. Measured TLP I-V curves, as zapping from VOUT to GND.

As measuring from 3xVDD to VOUT, the test circuits of Output Driver_10, Output Driver_30, and Output Driver_50 can achieve the TLP-measured It2 of 0.34A, 0.39A, and 0.39A, respectively as shown in Fig.3.31.

Fig. 3.31. Measured TLP I-V curves, as zapping from 3xVDD to VOUT.

From GND to VOUT, embedded SCR varies with the size of the driver, this design consideration can be more effectively utilized in the layout area. All these TLP measurement results are also listed in Table 3.3 and Table 3.4.

3xVDD-to-VOUT

TLP Voltage (V)

0 5 10 15 20 25

TLP Current (A)

0.0 0.1 0.2 0.3 0.4 0.5 0.6

Output Driver_10 Output Driver_30 Output Driver_50

Table 3.3

TLP measurement results, as zapping from GND-to-V^OUT and VOUT-to-3xVDD

Test Circuits

TLP

GND-to-VOUT VOUT–to-3xVDD

Vt1

TLP measurement results, as zapping from VOUT-to-GND and 3xVDD-to-VOUT

Test

3.4.3 Reliability of Novel High Voltage Output Driver

Measure swing voltage of novel high voltage output driver (Output Driver_10 and Driver + SCR_10_10) for one month, as shown in Fig. 3.32. The swing voltage of novel high voltage output driver on the 30th day still can maintain about ~9.6V.

Fig. 3.32. Long-term test of high voltage output driver.

3.4.4 Comparison of High Voltage Output Drivers

Table 3.5 show the document comparison of high voltage output driver, also using stacked MOS to achieve the purpose of the output swing voltage by n x VDD, and without the use of any additional wafer production technology. The proposed novel high voltage output driver can be a good solution for ESD protection.

Table 3.5

Comparison of high voltage output drivers

3.5 Summary

The proposed stacked-device output driver with embedded SCR has been developed for on-chip ESD protection in high-voltage-tolerant output stage where the signal swing may be as high as n x VDD. The 3xVDD-tolerant stacked-device output driver with embedded SCR has been verified in silicon chip. Without using any additional ESD protection device and layout area, the proposed design has the symmetrical ESD protection ability in GND-to-VOUT and VOUT-to-3xVDD paths. Besides, the transient behaviors of the proposed design during normal operation are not degraded. Therefore, the proposed design can be used to improve the ESD robustness of stacked-device

Chapter 4 Conclusions and Future Works

4.1 Conclusions

This Chapter summarizes the main results and contributions of this study. Future works of the embedded silicon-controlled rectifier for ESD protection design in CMOS

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