Thesis Organization

This thesis is divided into six chapters. Experimental verifications is presented in fifth chapter as the circuit implementation, rather than being isolated in a separate chapter.

Chapter 1 introduces the high speed serial link and some of the industrial standards. The applications concerned with SATA are also mentioned. SATA specifications about spread spectrum clocking are introduced. The motivation and goals are described for this thesis. Finally, the structure of this thesis is presented.

Chapter 2 covers the mathematical development of a linear PLL for conventional continuous-time s-domain analysis. The conventional analysis method is divided into closed-loop and open-loop analysis.

Chapter 3 reviews the common modulation mechanisms nowadays. This review

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also shows and compares the corresponding noise trnasfer function among them. A discrete-time open loop approach for analyzing the spread spctrum transient behavior is addressed. The transient response of spread spectrum clocking behavior is then carried out. Finally, the overall process of spread spectrum will be carried out and then the analysis of the quantization noise due to sigma delta modulation is included.

The timing impact involves the cycle-to-cylce jitter is developed in the end of this chapter.

Chapter 4 describes the concept of the proposed SSC and a steady state formula is reviewed first. Then, phase rotation mechnism and design details are covered. The last section introduces the phase rotation with sigma delta modulation method.

Chapter 5 shows the impelemenation of each circuit block, including PLL subblocks and spread spectrum blocks. The behavior simulation is included to obtain the design parameters in PLL at the same time. The measurement setup and experimental results are presented in the final section.

Chapter 6 gives a conclusions and future works are recommended at the end of this thesis.

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Chapter 2

Principles of Phase-Locked Loop

2.1 Introduction to PLL

Phase-locked loop is an electrical control system that generates a signal with a fixed relation to the phase of reference input. A phase-locked loop regulates the phase and frequency of an oscillator until it matches to the reference input in phase and frequency. Additionally, a phase-locked loop is an example of the control system with negative feedback.

Phase-locked loop is used widely in synchronous system, the main applications comprises clock and data recovery, de-skewing, clock generation, spread spectrum, clock distribution and so on.

Clock and data recovery [4]: A serial data is sent without clock signal across the channel to the receiver. A clock is recovered from the incoming data at the receiver end by the way of a clock and data recovery circuit.

De-skewing [5]: A clock signal is amplified or buffered before it can drive the electrical component, such as CPU, MEM and I/O. As a result, the received clock experiences the timing skew among these electrical blocks. To eliminate the delay, a de-skew PLL is included at the receiver side.

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Clock generation [16]: In most electrical system, the operating frequency of each processor is quite different from each other for different purpose. The clock sources from PLL supplies these processors, which multiply the low frequency of crystal oscillator by a multiplication ratio.

Spread spectrum [9]: All electrical system radiate electromagnetic interference.

Many regulatory agencies put the limit on the emitted energy. A circuit designer can adopt a spread spectrum PLL to reduce this interference.

Clock distribution [5]: A PLL drives the clock distribution that is usually balanced and arrive the endpoints simultaneously. A PLL compares one of the endpoints with the reference clock and then changes its phase and frequency to align the incoming reference clock.

Classification of phase-locked loop consists of linear PLL, digital PLL and all digital PLL [6]. A linear PLL is composed of analog input and analog circuit. A digital PLL is formed by a digital input, partial digital circuit and partial analog circuit. An all digital PLL consists of all digital circuits. Our design is based on the digital PLL.

2.2 Analysis of PLL Linear Model

A digital PLL is usually built of phase frequency detector, charge pump, loop filter and voltage control oscillator (VCO) with dividing by N negative feedback. This kind of system is shown conceptually in Fig.2.1. The phase frequency detector compares the phase difference between the reference input and the feedback signal from the VCO dividing by N. The purpose of the charge pump is to convert the logic states of the PFD into analog signals suitable for VCO. Therefore, the phase difference message is sent to the loop filter to establish a control signal on VCO. The

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VCO is an oscillator that generates a periodic output signal depending on the input control voltage from the loop filter. The frequency feedback ratio

ref out

f N = f is

provided by a divider so that PLL’s output signal frequency is an integer multiple of the reference.

Fig.2.1 A General PLL block diagram

The only digital block is the phase detector and the remaining blocks are similar to the linear PLL. A linear model can also be used for analyzing digital PLL by making some assumption. The first assumption describes that the loop bandwidth of the PLL system, which presents the response rate of the PLL, should be about 1/20 of the reference frequency. The continuous-time approximation holds true in such a case.

We also assume that the discrete-time operation of the charge pump can be approximated to its average behavior. The average error current i over one cycle is _e

e p

ref p p e

I T I t

i q

p´

=

´

= 2 where t is the turn-on time of either UP or DN equaling _p

11

to

ref e w

q , T is the input reference clock cycle, _ref I means the charge pump current, _p

and q presents the phase error between the input reference clock f_e ref and feedback clock signal fout/N. A linear model of a digital PLL is shown in Fig.2.2.

Fig.2.2 A equivalent linear model of a digital PLL

2.2.1 Analysis of Closed Loop Transfer Function

We will develop a closed loop transfer function based on [7]. If the average error current i is shown as above, the VCO control voltage can be expressed as _e

) ( ) ( )

(s i s F s V_C = _e

(s) ( )

2I F s

e P q

= p (2.1)

where i_e(s) is the Laplace transformation of i_e and F(s) describes the loop filter transfer function. The VCO output phase is given by

s s K V

s _C ^VCO

out( )= ( )

q (2.2)

These formulas would lead to a loop transfer functions, H(s) as

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Equation (2.3) indicates low-pass filtering characteristic from the PLL input to its output with dc gain equaling to unit. It indicates that the change in the output will be identical to input variation as long as tracking time is long enough and F(0)=¥ .

A steady state phase error q will arises when PLL experiences a frequency _s step Δω. Apply the final value theorem, the steady state phase error can be found to be

Note that the result from (2.5) can be derived regardless of the type of the loop filter.

It is necessary to turn the dc gain of the loop filter into an infinite value for the zero steady state phase error when a frequency offset is existed between the input reference clock and free-running frequency of the VCO. This important property implies that a dc pole is required in the loop filter.

A traditional second order loop PLL which is produced by a series connection of a resistor and a capacitor is shown in Fig.2.3 (a). Fig.2.3 (b) shows the practical circuit with a shunting resistance denoted as RS. The shunt loading is most likely to come from the input resistance of the VCO. The actual steady state phase error shown in (2.5) will be changed to

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Note that in equation (2.6), the steady state phase error is inverse proportional to the shunting resistance, RS. Thus, a large shunting resistive loading or a capacitive loading seen from the VCO input terminal is preferred to guarantee zero steady state phase error. Hence, a bias generator not only provides a bias voltage to VCO but also prevent the shunting resistance seen at the VCO input from connecting with loop filter.

(a) (b)

Fig.2.3 (a) Traditional 2^nd order PLL loop filter and (b) A shunt loading is included in the practical circuit

2.2.2 Analysis of Open Loop Transfer Function

The closed loop analysis usually involves the second order PLL whose loop filter composes of a series resistance and a capacitance. The critical drawback of this second order PLL is that each time a charge pump current is injected into the loop filter, the control voltage experience a large voltage jump. The resulting ripple

C C

S

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severely disturbs the VCO, corrupting the output phase. Therefore, additional pole is required to alleviate the voltage ripple. Another reason for higher order design of a PLL is to eliminate the reference spur due to the periodic operation of PFD, charge pumping circuit and frequency divider. Especially for low cycle-to-cycle jitter design of a SSCG, the reference spur becomes more serious owing to the phase rotation per reference clock cycle. Consequently, for a high order PLL, the natural frequency and damping factor of a second order PLL are no longer suitable for the analysis of the system stability. An open loop analysis is generally used to meet the stability issue of higher order PLL. Here we show the third order PLL analysis in analytic form and express the forth order PLL with rough approximation.

The concept of the phase margin is commonly adopted in the analysis of the open loop control system. Usually, 60 degree of phase margin is adopted and Fig.2.4 represents the loop filter of a third order PLL.

Fig.2.4 Third order charge pump PLL with additional C2

We rewrite the loop filter transfer function C

R

1

C

1

C

₂

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A general derivation of PLL open loop transfer function can be developed as follows

p obtain the amplitude response and phase response of the open loop transfer function

frequency of the open loop transfer function. That is, if we choosew =_t w_c, the third

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order PLL has the maximum phase margin. The corresponding phase margin is

2 ) design parameters shown as below

frequency of the third pole in the loop filter would attenuate frequency spur more but reduce the stability margin. For a third order loop filter, the added attenuation from the R2 and C3 can be approximated as a low-pass filter

Attenuatio w_ref (2.17)

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Fig.2.5 Third order loop with additional R2 and C3

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Chapter3

Analysis of Spread Spectrum Clock Generator

3.1 Spread spectrum Mechanism

With the development of high performance computer and peripheral systems, the operation speed is in GHz range. The high-speed signal interface between transmitter and receiver contributes most of noise in the system. These signals often generate Electric-Magnetic Interference (EMI) that affects the operation of other equipments.

When the operation speed is higher, the EMI problem is more severe. Thus, the popular promising technology like Serial-ATA defines the EMI reduction using spread-spectrum clocking has been explored [8] [9] [10] [11].

This section includes two subsections. The first subsection shows the different modulation mechanism. In the second subsection, we address the issue related to noise transfer function in the SSC. We also refer the effective phase jump of all methods to the input of PLL to do the transient analysis for all different modulation mechanism.

3.1.1 Introduction to Modulation Mechanism

In general, there are four types of modulation mechanism in SSCG, that is,

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modulation on VCO, modulation on input reference clock, modulation on divider and modulation with phase selection method. Fig.3.1 shows that modulating the output clock of a PLL by giving periodic drift on VCO control voltage with another charge pump used is in [8]. This is an analog technique that suffers new jitter source from the analog modulator and the process variation will affect the performance of SSCG.

The SSCG technique with modulation on input reference clock is presented in [9]

and is shown in Fig.3.2. Because of the phase selection using multiplexer, glitch problem is very series. Moreover, the glitch will cause an injected noise and the noise transfer function in that port has very large DC gain. This poor noise transfer function will be shown in the next subsection.

Another SSCG type is to utilize modulation on divider [10] as shown in Fig.3.3.

It has the same noise transfer function as the second method. Moreover, this technique could not achieve high modulation profile precision. Thus, the low jitter requirement cannot be satisfied.

Finally, the phase selection from the coherent multi-phase output of PLL is reported [11] and shown in Fig.3.4. Unfortunately, techniques in [10] and [11] both suffers serious glitch problem because of the operation of multiplexer.

Fig.3.1 Block diagram of a SSCG with modulation on VCO

out

Control Signal

CP

PFD LF VCO

Divider ref

Modulation Signal Generator

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Fig.3.2 Block diagram of a SSCG with modulation on input reference clock

Fig.3.3 Block diagram of a SSCG with modulation on divider

Fig.3.4 Block diagram of a SSCG with phase selection method

CP

PFD LF VCO

Divider

vco Modulation Signal

Generator ref

Clock Multiplexer

CP

PFD LF VCO

Main Divider N1/N2/N3…

ref vco

Modulation Signal Generator Divider

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3.1.2 Noise Transfer Function

We derive the noise transfer function of each modulation mechanism to understand the noise performance of each of them. To do this, we can choose one of them as our basic modulation method to minimize quantization noise due to digital signal processing.

Fig.3.5 illustrates the equivalent linear model of each modulation mechanism.

KPD is the gain of phase detector, F(s) means the transfer function of the loop filter, KVCO is the sensitivity of voltage control oscillator, and 1/N represents the divider ratio. The quantization noise of each method is listed below:

- f presents the output noise due to the quantization noise _out

- f_in models the quantization noise of a SSCG with modulation on input reference clock

- f_c models the quantization noise of a SSCG with modulation on VCO - f_r models the quantization noise of a SSCG with phase selection method - f_d models the quantization noise of a SSCG with modulation on divider The quantization noise and effective phase variation of each modulation method is shown below. The noise transfer function of each modulation method is given by

VCO

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Fig.3.5 Noise transfer function of each modulation mechanism

As shown in the Eqn.(3.1) to (3.4) , all of them reveal the low frequency passing characteristic. Therefore, the sigma-delta modulation is usually adopted to implement the modulation signal generator and the analysis of the quantization noise is almost the same. Although all the noise transfer function presents the same low-pass character, they have different DC gain. This feature makes the quantization noise effect quite different. Inserting s=0 in Eqn.(3.1) to (3.4) , we find the respective DC gain:

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Note that the DC gains are greater than one except the phase selection method.

The quantization noise will be amplified through the PLL loop due to the closed loop gain. To achieve the same noise level at the output of PLL, a higher order of the sigma-delta modulation is required when the DC gain is higher. Thus, our design is based on the phase selection method published in [11].

Due to the same filter attribute, the transient response of spread spectrum behavior of a SSCG will be realized with modulation on input. All the other modulation mechanism can be accomplished with the corresponding input referred signal at the phase detector input. Using the concept, we can begin our transient response analysis with corresponding input referred signal at the phase detector input.

3.2 Discrete-Time Open-Loop Criteria of PLL

At first, we introduce the traditional continuous-time model of a second-order linear PLL based on [12] as shown in Fig.3.6 and then a discrete-time open loop analysis depending on [12]. Here the two tracking path are modeled as the gain of proportional path KP and the gain of integral path KI. The integral path helps to

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suppress the static phase error because it provides infinite gain in the open loop of PLL. However, the integral path might make the loop of PLL unstable as a result of two poles at DC. Hence, a compensating zero or a proportional path is needed to stabilize the loop. As shown in Fig.3.6, the integral path sets one of the VCO frequency term to a time-integral of the past phase error with a gain KI. The proportional path sets the other frequency term of the VCO proportion to the current phase error.

Fig.3.6 Continuous-time model of a second-order linear PLL

Note that we will make a link between open loop transfer function and closed loop transfer function to find the relationship of proportional gain KP and integral gain KI to natural frequency ωn and damping factor ξ. To do this, the open-loop transfer function of the PLL, LPLL(s), defined as ψout(s)/ ψerr(s) , is

) (

) ) (

( s

s s L

err out

PLL f

=f

₂ s

K sK_P + _I

= (3.9)

P

I

f

in

f

^err

f

out

25

We can express the proportional gain KP and integral gain KI with circuit design parameters such as charge pump current IP, sensitivity of VCO KO, C1 in loop filter and R1 in loop filter. From (3.11) and (3.12), KI and KP can be expressed as

C1

K I

K_I = _O´ ^P (3.13)

K_P =I_P ´R₁´K_O (3.14)

Equation (3.13) implies that integral gain is proportional to the voltage slew rate of C1 in the loop filter with a proportional constant KO. The proportional gain is directly proportional to the voltage drop IPR1. From this point of view, we can explain

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the PLL loop characteristic in discrete time.

The above system behavior involves continuous-time quantity. But ψerr is actually a sampled value when phase detector detects the phase error. The phase comparison can occur only once per cycle. Therefore, a PLL shall be described with discrete-time open loop characteristics. Fig.3.7 shows the discrete-time model of a PLL.

Fig.3.7 A discrete-time PLL models the changes in phaseΔΦ and in frequency Δωof each cycle due to the sampled phase error ψerr.

As shown in Fig.3.6, the integral frequency term ωI =KIψerr(s)/s can be regarded as a discrete-time summation

å

=^--¥

T is the input reference clock period. A similar derivation can be carried out ref

about the proportional frequency termωP(s)=KPψerr(s). If the resulting phase ψP =

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Following from equation (3.15) and (3.16), the frequency ωI and the phase ψP

shown in Fig.3.7 were updated the in each cycle. The modified quantities in each models the change in phase and frequency due to each sampled phase error. Since KI

= ωn2 and KP = 2ξωn, (3.17) and (3.18) become

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help us to do transient response of spread spectrum behavior with PLL system parameters such as ωn and ξ.

3.3 Transient response of Spread Spectrum

With the derivation of the discrete-time open-loop criteria of a PLL, we can analyze spread spectrum behavior using digital signal processing. As shown in Fig.3.1, Fig.3.2, Fig.3.3 and Fig.3.4, Modulation Signal Generator is usually a digital processing block clocked by input reference clock of PLL by a specified ratio. Hence, we can develop the difference equation of spread spectrum behavior according to the concept of discrete-time open-loop criteria of a PLL.

The understanding of transient response of spread spectrum behavior can help to express the SSCG design requirement with PLL system parameters. As will be shown later, we will discover that the design consideration of SSCG would be different with different PLL system parameters.

In section 3.3.1, we discuss the behavior of SSC and model it as a equivalent difference equation expressed with PLL system parameters such asωn and ξ. Thus, in section 3.3.2, we will display the transient response with different PLL system parameters and discuss about the design consideration. Finally, we show the effective frequency of spread spectrum clocking.

3.3.1 Equivalent Difference Equation of SSC

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Fig.3.8 A modified discrete-time PLL model

To derive the difference equation of spread spectrum behavior from equation (3.19), we redraw the discrete-time PLL model as shown in Fig.3.8. Where K and _w K^ψ are the open-loop integral gain and open-loop proportional gain, respectively and

To derive the difference equation of spread spectrum behavior from equation (3.19), we redraw the discrete-time PLL model as shown in Fig.3.8. Where K and _w K^ψ are the open-loop integral gain and open-loop proportional gain, respectively and

在文檔中 應用於Serial ATA 6Gb/s 之展頻時脈產生器 (頁 23-0)