應用於Serial ATA 6Gb/s 之展頻時脈產生器

國 立 交 通 大 學

電子工程學系電子研究所

碩 士 論 文

應用於

Serial ATA 6Gb/s

之展頻時脈產生器

A Spread Spectrum

Clock Generator for Serial ATA 6Gb/s

Application

研 究 生：黃 彥 穎

指導教授：周 世 傑

國 立 交 通 大 學

電子工程學系電子研究所

碩 士 論 文

應用於

Serial ATA 6Gb/s

之展頻時脈產生器

A Spread Spectrum

Clock Generator for Serial ATA 6Gb/s

Application

研 究 生：黃 彥 穎

指導教授：周 世 傑

應用於

Serial ATA 6Gb/s 之展頻時脈產生器

A Spread Spectrum Clock Generator for 6 Gb/s Serial ATA

Applications

研 究 生：黃彥穎 Student：Yen-Ying Huang

指導教授：周世傑 Advisor：Prof. Shyh-Jye Jou

國 立 交 通 大 學

電子工程學系 電子研究所碩士班

碩 士 論 文

A Thesis

Submitted to Department of Electronics Engineering & Institute of Electronics

College of Electrical and Computer Engineering National Chiao Tung University

in Partial Fulfillment of the Requirements for the Degree of

Master of Science In

Electronics Engineering December 2007

Hsinchu, Taiwan, Republic of China

I

應用於

Serial ATA 6Gb/s 之展頻時脈產生器

研 究 生 ： 黃 彥 穎 指 導 教 授 ： 周 世 傑 博 士

國立交通大學

電子工程學系 電子研究所碩士班

摘要

展頻技術主要是對時脈信號的頻率做調變，使得信號能量平均分散到較為寬 大的頻譜內。降低其在頻譜上相對應的能量峰值。本論文先簡單的介紹鎖相迴路 的設計觀念，並提出了展頻的穩態以及暫態現象的分析與鎖相迴路系統參數的關 係，使得我們可以得到一個較佳的設計概念。並解決了在多工器操作之下，所造 成不當的信號突波。為了保證電路操作的穩定性，我們同時採取了數位控制的解 決方法，來保證相位變化是單調且一致的。在鎖相迴路中，為了減小時脈抖動， 我們採取錯誤放大器的方式來解決電路操作中電流不匹配的問題，同時採用三階 迴路濾波器濾除鎖相迴路中週期性的突波現象。我們在振盪器中加入被動電阻， 以降低對震盪器輸入端的敏感度並提高線性度；又加入交互偶合電晶體來加速震 盪器震盪轉態的操作。 我們所提出的展頻時脈產生器主要應用於 Serial ATA 6Gbps 中，向下展頻 5000ppm 同時採用三角波調變且調變頻率為 30KHz。此展頻時脈產生器使用和差 調變器及相位旋轉方式完成之。此電路是在 90 奈米互補式金氧半的製程下所製

II

造。展頻時脈最大週期對週期時脈抖動為 1.13ps 並操作在 1.4GHz 時消耗 7.57 毫瓦。能量峰值所能降低的最大數量為 20.6dB。晶片面積分為: 鎖相迴路主要 電路170´80um2，迴路濾波器235´325um2，相位旋轉單位170´20um2。

III

A Spread Spectrum Clock Generator for 6Gb/s

Serial ATA Application

Student：Yen-Ying Huang Advisor：Prof. Shyh-Jye Jou

Department of Electronics Engineering

Institute of Electronics

National Chiao Tung University

ABSTRACT

Spread spectrum is to modulate the frequency of clock and to spread the clock energy in a wider spectrum. This would lead to a reduction of the peak level of the clock energy. In this thesis, we will describe the phase-locked loop (PLL) design considerations first. Then, we will introduce the steady-state and transient analysis of spread spectrum behavior. These can help us to express the SSCG design consideration with PLL parameters. We also use the interpolation technique to avoid the glitch problem due to the operation of multiplexer and provide a thermal code control to guarantee the monotonic behavior in the process of phase rotation.

In the PLL design, we achieve low jitter issue by using error amplifier to resolve the current mismatch in charge pump and a third order loop filter is adopted to reduce the reference spur. A passive resistor is presented in the VCO delay cell to reduce the Kvco gain and an additional cross-couple CMOS is also included to the delay cell to

IV

boost the operation of delay cell. Our spread spectrum clock generator (SSCG) for Serial ATA Specification is down spread 5000ppm with a triangular modulation profile and the modulation frequency is 30 kHz. A spread spectrum technique using PLL with a sigma delta modulator and phase rotation algorithm is proposed. This proposed architecture has been designed in a 90-nm CMOS process. The spread clocking has a peak-to-peak cycle-to-cycle jitter of 1.13ps and consumes 7.57mW at 1.4GHz. The EMI reduction in this circuit is about 20.6dB. The core area includes PLL Main Circuit (_170´80um2_{), Loop Filter (235´325um}2_{) and Phase Rotation}

Block (_170´20um2

V

誌 謝

碩士生涯兩年半即將到一段落，兩年半的時間中受到許多人的幫助才使得我 能夠順利的在今天拿到學位。特別要感謝我的指導教授周世傑老師在這段時間對 我的指導，不只在研究方面給予我指引，同時鞭策我使我能有更為嚴謹的研究態 度，也感謝老師對於散漫的我的諄諄教誨。另外還要感謝一直以來帶著我做研究 的 totoro 學長，能夠不厭其煩的引領我進入這個領域，還有志龍學長，在 modeling 以及 layout 量測部分給予我很大的幫助；另外就是我的研究夥伴 apu， 這段時間的互相討論跟合作，一起熬夜趕 tape-out，我想以後這會是一段想起 來有點痛苦不過又值得回味的回憶。 我也要感謝 316 實驗室的同學們，碩一的時候常常一起熬夜寫作業、吃火 鍋、打電動、打紙棒球的俊男、國光、俊誼、建君、apu、晉欽讓我的碩士生涯 豐富不少，我想我很難忘記那段瘋狂 AOC 的時候，我也是唯一被老闆抓到兩次的 傢伙。另外就是學妹 van、學長庭禎、小胖組成了八卦閒聊組合，雖然很多東西 都是唬爛的，不過卻也充滿歡笑。還有誠文、momo 在研究上及找國防役的時候 給我的建議；蔡 group 的宜興、珦益、茂成在研究上的協助；還有我一大堆的球 友:企鵝、昭安、孟祺、阿國..，讓我在研究所生涯中保持強健的體魄。 另外我還要感謝我女朋友姿君這段時間的陪伴，常常因為研究的事情而被我 忽略。還有我的父母對我的關心，才讓我能夠順利的完成學位。 要感謝的人太多，謝謝大家了。

VI

Contents

Chapter 1 Introduction ... 1

1.1 Introduction to High-Speed Serial Link

... 1

1.2 Timing Specifications and Application Issues

... 2

1.3 Motivation

... 5

1.4 Thesis Organization

... 6

Chapter 2 Principles of Phase-Locked Loop ... 8

2.1 Introduction to PLL ... 8

2.2 Analysis of PLL Linear Model ... 9

2.2.1 Analysis of Closed Loop Transfer Function ... 11

2.2.2 Analysis of Open Loop Transfer Function ... 13

Chapter3 Analysis of Spread Spectrum Clock Generator ... 18

3.1 Spread spectrum Mechanism ... 18

3.1.1 Introduction to Modulation Mechanism ... 18

3.1.2 Noise Transfer Function ... 21

3.2 Discrete-Time Open-Loop Criteria of PLL ... 23

3.3 Transient response of Spread Spectrum ... 28

3.3.1 Equivalent Difference Equation of SSC ... 28

3.3.2 Transient Response of SSC with different PLL system parameters .... 30

3.3.3 Effective Spread Frequency with Different Phase Jump ... 35

3.4 Overall Spread Spectrum Behavior ... 37

3.4.1 Spread Spectrum behavior without Quantization Noise ... 38

3.4.2 Sigma-Delta Modulation with Different Orders ... 42

VII

Chapter 4 Algorithm of the Proposed Spread Spectrum Clock Generator ... 49

4.1 Concept of SSCG Using Phase Rotation ... 49

4.2 Analysis of Quantization Noise ... 52

4.3 Phase Rotation Mechanism ... 58

4.4 ΣΔ Modulator ... 61

Chapter 5 Circuit design of Spread Spectrum Clock Generator ... 64

5.1 Introduction ... 64

5.2 System architecture ... 65

5.3 Behavior Simulation ... 66

5.4 Circuit Implementation ... 68

5.4.1 Phase / Frequency Detector ... 69

5.4.2 Current Matching Charge Pump ... 70

5.4.3 3th Order Loop Filter ... 72

5.4.4 Voltage-Controlled Oscillator ... 73

5.4.5 Multiplexer and Interpolator ... 74

5.4.6 Divider ... 76

5.5 Circuit Simulation ... 77

5.6 Experimental Results ... 85

5.6.1 Layout and Pad Assignment... 85

5.6.2 Measurement setup ... 88

VIII

List of Figures

Fig.1.1 Triangular modulation profile of SSC ... 4

Fig.1.2 Spread spectrum clocking and non-spread mode comparison[3] ... 5

Fig.2.1 A General PLL block diagram ... 10

Fig.2.2 A equivalent linear model of a digital PLL ... 11

Fig.2.3 (a) Traditional 2nd order PLL loop filter and (b) A shunt loading is included in the practical circuit ... 13

Fig.2.4 Third order charge pump PLL with additional C2 ... 14

Fig.2.5 Third order loop with additional R2 and C3 ... 17

Fig.3.1 Block diagram of a SSCG with modulation on VCO ... 19

Fig.3.2 Block diagram of a SSCG with modulation on input reference clock ... 20

Fig.3.3 Block diagram of a SSCG with modulation on divider ... 20

Fig.3.4 Block diagram of a SSCG with phase selection method ... 20

Fig.3.5 Noise transfer function of each modulation mechanism ... 22

Fig.3.6 Continuous-time model of a second-order linear PLL ... 24

Fig.3.7 A discrete-time PLL models the changes in phaseΔΦ and in frequency ... 26

Fig.3.8 A modified discrete-time PLL model ... 29

Fig.3.9 Transient response of phase error j_err[n] with damping factor (a) 0.5, (b) 0.707, (c) 1 and (d) 3 ... 34

Fig.3.10 Transient response of spread frequency deviation with (a) 50ppm ... 36

Fig.3.11 Overall spread spectrum behavior with (a) 20 1 = ref n w w (b) 0 5 1 = ref n w w ... 39

Fig.3.12 Histogram for 0 2 1 = ref n w w (a) under damping case (b) over damping case and 0 5 1 = ref n w w (c) under damping case (d) over damping case ... 41 Fig.3.13 0 2 1 = ref n w w and under damping operation with (a)1st order modulation (b) 2nd order modulation ... 43

IX Fig.3.14 0 2 1 = ref n w w

and over damping operation with (a)1st order

modulation (b) 2nd order modulation ... 44

Fig.3.15 0 5 1 = ref n w w and under damping operation with (a)1st order modulation (b) 2nd order modulation ... 45

Fig.3.16 0 5 1 = ref n w w and over damping operation with (a)1st order modulation (b) 2nd order modulation ... 46

Fig.4.1 The ideal triangular modulation profile ... 50

Fig.4.2 Triangular modulation profile with digital approaches ... 50

Fig.4.3 block diagram of SSCG using phase rotation scheme ... 51

Fig.4.4 Timing diagram of the phase rotation ... 51

Fig.4.5 PSD of Quantization Noise with different modulation order (a) Normal graph (b) Enlarge diagram of (a) in lower frequency band .... 55

Fig.4.6 PSD of Quantization Noise at different orders PLL output with separate unit gain frequency (a1~3) f_t f_ref 0 2 1 = (b1~3) f_t f_ref 0 5 1 = ; (a1,b1) 2nd order PLL (a2,b2) 3rd order PLL (a3,b3) 4th order PLL ... 56

Fig.4.7 Total quantization noise at 4th order PLL output with different orders of modulator as the normalized unit gain frequency as x axis (a) total power vs. ft/fref (b) Relative total noise power level among different order modulators ... 58

Fig.4.8 Block diagram of phase rotation unit and phase rotation control .... 60

Fig.4.9 The phase rotation in progress ... 61

Fig.4.10 Equivalent digital implementation of a sigma delta modulator with (a) first order and (b) second order module ... 62

Fig.5.1 The architecture of SSCG with phase rotation technique ... 65

Fig.5.2 Frequency response of 3rd order and 4th order PLL ... 68

Fig.5.3 Phase frequency detector (a) schematic (b) timing diagram (c) Single to Differential circuit ... 69

Fig.5.4 Charge pump circuit ... 71

Fig.5.5 Charge Pump current matching characteristic (a)Conventional charge pump (b) proposed charge pump ... 72

Fig.5.6 Third order loop filter ... 72

X

Fig.5.8 Operating Frequency with different Vctrl voltage ... 74

Fig.5.9 Multiplexer ... 75

Fig.5.10 Thermal code controlled interpolator ... 76

Fig.5.11 Schematic of divider ... 77

Fig.5.12 Spectrum of VCO output clock with and without spread spectrum modulation(Pre-Layout) ... 78

Fig.5.13 Period of VCO output waveform vs. time(Pre-Layout) ... 78

Fig.5.14 1st order and 2nd order modulation comparison (a) spectrum (b) Period of VCO output waveform vs. time(Pre-Layout) ... 80

Fig.5.15 153 stairs and 20 stairs comparison (a) spectrum (b) Period of VCO output waveform vs. time(Pre-Layout) ... 81

Fig.5.16 Eye diagram of VCO output and Jitter histogram without SSC(Post-Layout) ... 82

Fig.5.17 VCO output waveform(Post-Layout) ... 83

Fig.5.18 Vctrl tracking behavior(Post-Layout) ... 83

Fig.5.19 Chip Layout of SSCG ... 86

XI

List of Tables

Table.1.1 Industrial standard for high speed serial link ... 2

Table.1.2 General Specifications of SATA Gen2 [3] ... 3

Table.1.3 General Specifications and Comparison of SSC in different standards ... 4

Table.3.1 The relative open-loop parameters according to different closed-loop parameters ... 31

Table.5.1 Corresponding system components ... 67

Table.5.2 Design summary of the proposed PLL ... 84

Table.5.3 Design summary of the proposed SSCG ... 84

Table.5.4 Comparison of SSCG ... 85

1

Chapter 1

Introduction

1.1 Introduction to High-Speed Serial Link

The multi-gigabit transmission through wire has been applied extensively. There are two approaches for such high speed applications: parallel buses and serial link buses. The conventional parallel buses would contribute the complexity of routing and additional power consumption. For this reason, the high speed serial link buses become more attractive one for high speed application. Another property of high speed serial link is easy to do port expansion. A new function or capability is added to the PC, a new defined interface addresses the demand.

However, it is unfortunate that off-chip (I/O) bandwidth has not grown up with the increasing operating frequency. Due to the limited bandwidth of transmission line (I/O), there are new challenges in the design of high speed system. Channel, transmitter and receiver should be worked together to achieve low cost and high performance design.

There are high speed serial link standards are defined over short distance in copper cable or longer distance in fiber, such as Serial ATA, IEEE1394b and so on. Table.1.1 makes a list of some industrial standards [1].

2

Table.1.1 Industrial standard for high speed serial link

Standard USB2.0[1] IEEE1394b[2] Serial ATA[3] Parallel ATA Speed 480Mbps 1.6-3.2Gbps 1.5/3/6Gbps 1.33Gbps max

Max. Cable length 5m 4.5m 1m(3Gbps) 0.46m

Hot Swappable Yes Yes Yes No

1.2 Timing Specifications and Application Issues

Serial Advanced Technology Attachment (SATA) [3] is a computer bus for connecting the storage devices and a computer. SATA uses only four signal lines, allowing the more compact cables than PATA. It also offers the new features, including hot swapping as shown in Table.1.1.

The serial ATA 1.0a targeted at the interface between desktop PC motherboard, devices, CD ROMs, and DVD ROMs. Serial SATAⅡ[3]expands the application of serial ATA 1.0a. We will show some potential applications which take advantage of new features in Serial SATAⅡ. The SATAⅡsupports several kinds of connections, including:

A. Internal 1 meter cabled host to device B. Short backplane to device

C. Long backplane to device

D. Internal 4-lane cabled serial ATA disk arrays

E. System to system interconnect-data center application F. System to system interconnects-external desktop applications

3

G. Proprietary serial ATA disk arrays

Serial ATA also offers the use of spread spectrum clocking (SSC). The goal of this modulation is to decrease the peak spectral energy of the clocking to mitigate the interference to peripheral device. The related spread spectrum parameters are shown in Table.1.2. Modulation frequency must locate in the range of 30 to 33 KHz. The modulation frequency deviation is requested to down spread within -5000ppm to 0ppm. The instantaneous frequency of clock should fall into the TUI range.

The f specifies the permissive frequency variation from nominal except the _tol

frequency variation because of jitter, spread spectrum clocking, or phase noise of clock source.

Table.1.2 General Specifications of SATA Gen2 [3]

Parameter Units Limit SATA Usage Model TUI, unit interval ps Min 333.2167 Nom 333.3333 Max 333.1167 tol f ,

Frequency Long term Stability ppm Min -350 Max +350 Spread-Spectrum Modulation Frequency kHz Min 30 Max 33 Spread-Spectrum Modulation Deviation ppm Min -5000 Max 0

Both Serial Attached SCSI-2(SAS-2) and PCI express also adopt the SSC application. Accordingly, the related spread spectrum parameters in different standard

4

are shown in Table.1.3.

Table.1.3 General Specifications and Comparison of SSC in different standards

Standard SATA SAS-2 PCI express

Spread Spectrum Modulation Frequency 30~33kHz 30~33kHz 30~33kHz SSC modulation type Down spreading 0/-5000 ppm Center spreading +2300/-2300 ppm Down spreading 0/-5000 ppm Down spreading 0/-2300 ppm Frequency Long term Stability +-350ppm +-100ppm +-300ppm

We give an example of modulation profile for down spreading illustrated in Fig.1.1 [3]. Where f_nom is the nominal frequency of clock source in non-SSC mode, fm is the

modulation frequency, δis the modulation frequency deviation and t is the time. The EMI reduction of SSC is defined as Δ as shown in Fig.1.2.

5

Fig.1.2 Spread spectrum clocking and non-spread mode comparison[3]

1.3 Motivation

As the higher operation speed is required, the signals pose more stringent timing requirement. Hence, a pure and stable clock source is needed to achieve the skew reduction and improve the overall system timing. With the shrinking tolerance of jitter, the low jitter design of PLL has become a challenge. Besides, the application of PLL has appeared in many domains. For examples, frequency synthesizer, clock and data recovery, frequency multiplication, and clock de-skew are different applications of PLL systems.

Spread spectrum techniques are methods by spreading the signal energy in the frequency domain. These techniques are used for EMI reduction. In real world, the synchronous systems radiate electromagnetic energy in the clock frequency and its

6

harmonics. This electromagnetic interference might cause damage to the peripheral storages and other signal processing unit. To not exceed the regulative limit of electromagnetic interference, the Serial ATA defines the EMI reduction using spread spectrum clocking.

Spread spectrum clocking techniques have been frequently needed in portable device due to faster clock frequency and the highly integrated LCD displays in a small device. On the other hand, heavy metal shielding is not the low-cost option in the lightweight portable device. For active EMI reduction methods such as SSC, some challenges are existed for circuit designer because the modified clock doses not align any more in the synchronous system. The transmitter and receiver run into new difficulties in this SSC system due to the occurrence of the deterministic timing jitter.

1.4 Thesis Organization

This thesis is divided into six chapters. Experimental verifications is presented in fifth chapter as the circuit implementation, rather than being isolated in a separate chapter.

Chapter 1 introduces the high speed serial link and some of the industrial standards. The applications concerned with SATA are also mentioned. SATA specifications about spread spectrum clocking are introduced. The motivation and goals are described for this thesis. Finally, the structure of this thesis is presented.

Chapter 2 covers the mathematical development of a linear PLL for conventional continuous-time s-domain analysis. The conventional analysis method is divided into closed-loop and open-loop analysis.

7

also shows and compares the corresponding noise trnasfer function among them. A discrete-time open loop approach for analyzing the spread spctrum transient behavior is addressed. The transient response of spread spectrum clocking behavior is then carried out. Finally, the overall process of spread spectrum will be carried out and then the analysis of the quantization noise due to sigma delta modulation is included. The timing impact involves the cycle-to-cylce jitter is developed in the end of this chapter.

Chapter 4 describes the concept of the proposed SSC and a steady state formula is reviewed first. Then, phase rotation mechnism and design details are covered. The last section introduces the phase rotation with sigma delta modulation method.

Chapter 5 shows the impelemenation of each circuit block, including PLL subblocks and spread spectrum blocks. The behavior simulation is included to obtain the design parameters in PLL at the same time. The measurement setup and experimental results are presented in the final section.

Chapter 6 gives a conclusions and future works are recommended at the end of this thesis.

8

Chapter 2

Principles of Phase-Locked Loop

2.1 Introduction to PLL

Phase-locked loop is an electrical control system that generates a signal with a fixed relation to the phase of reference input. A phase-locked loop regulates the phase and frequency of an oscillator until it matches to the reference input in phase and frequency. Additionally, a phase-locked loop is an example of the control system with negative feedback.

Phase-locked loop is used widely in synchronous system, the main applications comprises clock and data recovery, de-skewing, clock generation, spread spectrum, clock distribution and so on.

Clock and data recovery [4]: A serial data is sent without clock signal across

the channel to the receiver. A clock is recovered from the incoming data at the receiver end by the way of a clock and data recovery circuit.

De-skewing [5]: A clock signal is amplified or buffered before it can drive the

electrical component, such as CPU, MEM and I/O. As a result, the received clock experiences the timing skew among these electrical blocks. To eliminate the delay, a de-skew PLL is included at the receiver side.

9

Clock generation [16]: In most electrical system, the operating frequency of

each processor is quite different from each other for different purpose. The clock sources from PLL supplies these processors, which multiply the low frequency of crystal oscillator by a multiplication ratio.

Spread spectrum [9]: All electrical system radiate electromagnetic interference.

Many regulatory agencies put the limit on the emitted energy. A circuit designer can adopt a spread spectrum PLL to reduce this interference.

Clock distribution [5]: A PLL drives the clock distribution that is usually

balanced and arrive the endpoints simultaneously. A PLL compares one of the endpoints with the reference clock and then changes its phase and frequency to align the incoming reference clock.

Classification of phase-locked loop consists of linear PLL, digital PLL and all digital PLL [6]. A linear PLL is composed of analog input and analog circuit. A digital PLL is formed by a digital input, partial digital circuit and partial analog circuit. An all digital PLL consists of all digital circuits. Our design is based on the digital PLL.

2.2 Analysis of PLL Linear Model

A digital PLL is usually built of phase frequency detector, charge pump, loop filter and voltage control oscillator (VCO) with dividing by N negative feedback. This kind of system is shown conceptually in Fig.2.1. The phase frequency detector compares the phase difference between the reference input and the feedback signal from the VCO dividing by N. The purpose of the charge pump is to convert the logic states of the PFD into analog signals suitable for VCO. Therefore, the phase difference message is sent to the loop filter to establish a control signal on VCO. The

10

VCO is an oscillator that generates a periodic output signal depending on the input control voltage from the loop filter. The frequency feedback ratio

ref out

f f N = is provided by a divider so that PLL’s output signal frequency is an integer multiple of the reference.

Fig.2.1 A General PLL block diagram

The only digital block is the phase detector and the remaining blocks are similar to the linear PLL. A linear model can also be used for analyzing digital PLL by making some assumption. The first assumption describes that the loop bandwidth of the PLL system, which presents the response rate of the PLL, should be about 1/20 of the reference frequency. The continuous-time approximation holds true in such a case. We also assume that the discrete-time operation of the charge pump can be approximated to its average behavior. The average error current _{i over one cycle is e}

e p ref p p e I T t I i q p´ = ´ =

11 to ref e w q

, T is the input reference clock cycle, _ref I means the charge pump current, _p

and q presents the phase error between the input reference clock f_e ref and feedback

clock signal fout/N. A linear model of a digital PLL is shown in Fig.2.2.

Fig.2.2 A equivalent linear model of a digital PLL

2.2.1

Analysis of Closed Loop Transfer Function

We will develop a closed loop transfer function based on [7]. If the average error current i is shown as above, the VCO control voltage can be expressed as _e

) ( ) ( ) (s i s F s V_C = _e (s) ( ) 2 F s I e P _q p = (2.1)

where i_e(s) is the Laplace transformation of i_e and F(s) describes the loop filter transfer function. The VCO output phase is given by

s K s V s VCO C out( )= ( ) q (2.2)

12 ) ( 2 ) ( ) ( ) ( ) ( s F I K s s F I K s s s H P VCO P VCO in out + = = p q q (2.3) ) ( 2 2 ) ( ) ( ) ( 1 s F I K s s s s s H P VCO in e + = = -p p q q (2.4)

Equation (2.3) indicates low-pass filtering characteristic from the PLL input to its output with dc gain equaling to unit. It indicates that the change in the output will be identical to input variation as long as tracking time is long enough and F(0)=¥ .

A steady state phase error q will arises when PLL experiences a frequency _s step Δω. Apply the final value theorem, the steady state phase error can be found to be rad s F I K_{VCO P S} s 0 ) ( 2 = D = p w q _(2.5)

Note that the result from (2.5) can be derived regardless of the type of the loop filter. It is necessary to turn the dc gain of the loop filter into an infinite value for the zero steady state phase error when a frequency offset is existed between the input reference clock and free-running frequency of the VCO. This important property implies that a dc pole is required in the loop filter.

A traditional second order loop PLL which is produced by a series connection of a resistor and a capacitor is shown in Fig.2.3 (a). Fig.2.3 (b) shows the practical circuit with a shunting resistance denoted as RS. The shunt loading is most likely to

come from the input resistance of the VCO. The actual steady state phase error shown in (2.5) will be changed to rad R I K_{VCO P S} s w p q = 2 D _(2.6)

13

Note that in equation (2.6), the steady state phase error is inverse proportional to the shunting resistance, RS. Thus, a large shunting resistive loading or a capacitive

loading seen from the VCO input terminal is preferred to guarantee zero steady state phase error. Hence, a bias generator not only provides a bias voltage to VCO but also prevent the shunting resistance seen at the VCO input from connecting with loop filter.

(a) (b)

Fig.2.3 (a) Traditional 2nd order PLL loop filter and (b) A shunt loading is included in the practical circuit

2.2.2

Analysis of Open Loop Transfer Function

The closed loop analysis usually involves the second order PLL whose loop filter composes of a series resistance and a capacitance. The critical drawback of this second order PLL is that each time a charge pump current is injected into the loop filter, the control voltage experience a large voltage jump. The resulting ripple

C C

14

severely disturbs the VCO, corrupting the output phase. Therefore, additional pole is required to alleviate the voltage ripple. Another reason for higher order design of a PLL is to eliminate the reference spur due to the periodic operation of PFD, charge pumping circuit and frequency divider. Especially for low cycle-to-cycle jitter design of a SSCG, the reference spur becomes more serious owing to the phase rotation per reference clock cycle. Consequently, for a high order PLL, the natural frequency and damping factor of a second order PLL are no longer suitable for the analysis of the system stability. An open loop analysis is generally used to meet the stability issue of higher order PLL. Here we show the third order PLL analysis in analytic form and express the forth order PLL with rough approximation.

The concept of the phase margin is commonly adopted in the analysis of the open loop control system. Usually, 60 degree of phase margin is adopted and Fig.2.4 represents the loop filter of a third order PLL.

Fig.2.4 Third order charge pump PLL with additional C2

We rewrite the loop filter transfer function

C

R

1

C

1

15 ] 1 || ) 1 [( 2 ) ( ) ( ) ( 2 1 1 sC sC R I s F K s s V _P PD e C _{= = +} p q 1 ) || ( 1 ) ( 2 _{1 1 2} 1 1 2 1 + + ´ + = C C sR C sR C C s I_P p ) || ( 1 ; 1 2 1 1 1 1C R C C R P z = w = w _(2.7)

A general derivation of PLL open loop transfer function can be developed as follows

p z P e C s s C C s I s s V w w p q ₊ + ´ + = 1 1 ) 2 1 ( 2 ) ( ) ( N s K s s V s L VCO e C 1 ) ( ) ( ) ( = ´ ´ q p z P VCO s s C C N s I K w w p ₊ + ´ + = 1 1 ) 2 1 ( 2 2 (2.8)

where L(s) is the open loop gain transfer function, substitute s= jw into (2.8) to obtain the amplitude response and phase response of the open loop transfer function

p z P VCO j s _j j C C N I K s L w w w w pw w + + ´ + -= = 1 1 ) 2 1 ( 2 )| ( _{2 (2.9)} p w w w w w = - -Ð _{( ) tan}-1_{( ) tan}-1_{( )} P z j L _(2.10) 0 ) ( 1 1 ) ( 1 1 | ) ( 2 2 - ₊ = + = Ð p p z x C d j L d w w w w w w w w w p z c w w w w = = Þ 2 1 1 1 1 1 C C C R + = (2.11)

We will find a maximum phase margin as w =w_t where w t is the unit gain

16

order PLL has the maximum phase margin. The corresponding phase margin is

) 2 ) 1 -1 ( ( tan 1 wz wp w w f p z p = -(2.12) ) 2 ( tan 1 2 2 2 2 1 1 C C C C C C + -+ = - (2.13)

Given the unit gain frequency w and the phase margin_t f_p, we obtain the relative

design parameters shown as below

2 2 2 2 ) ( 1 ) ( 1 p t z t t VCO PD p z N K K C w w w w w w w + + = (2.14) ) 1 ( 2 1= -z p C C w w (2.15) 1 1 1 C R z w = _(2.16) 4 1 = = z t t p w w w w

gives a phase margin _{» 60} °

As mentioned above, the forth order PLL with third order loop filter can be illustrated in Fig.2.5. The design consideration is more complicate and a simple analytic equation cannot be derived in the forth order PLL. The lower of the frequency of the third pole in the loop filter would attenuate frequency spur more but reduce the stability margin. For a third order loop filter, the added attenuation from the R2 and C3 can be approximated as a low-pass filter

] 1 ) log[( 20 2 3 2 + = R C n Attenuatio w_ref (2.17)

17

18

Chapter3

Analysis of Spread Spectrum Clock Generator

3.1 Spread spectrum Mechanism

With the development of high performance computer and peripheral systems, the operation speed is inGHz range. The high-speed signal interface between transmitter and receiver contributes most of noise in the system. These signals often generate Electric-Magnetic Interference (EMI) that affects the operation of other equipments. When the operation speed is higher, the EMI problem is more severe. Thus, the popular promising technology like Serial-ATA defines the EMI reduction using spread-spectrum clocking has been explored [8] [9] [10] [11].

This section includes two subsections. The first subsection shows the different modulation mechanism. In the second subsection, we address the issue related to noise transfer function in the SSC. We also refer the effective phase jump of all methods to the input of PLL to do the transient analysis for all different modulation mechanism.

3.1.1 Introduction to Modulation Mechanism

19

modulation on VCO, modulation on input reference clock, modulation on divider and modulation with phase selection method. Fig.3.1 shows that modulating the output clock of a PLL by giving periodic drift on VCO control voltage with another charge pump used is in [8]. This is an analog technique that suffers new jitter source from the analog modulator and the process variation will affect the performance of SSCG.

The SSCG technique with modulation on input reference clock is presented in [9] and is shown in Fig.3.2. Because of the phase selection using multiplexer, glitch problem is very series. Moreover, the glitch will cause an injected noise and the noise transfer function in that port has very large DC gain. This poor noise transfer function will be shown in the next subsection.

Another SSCG type is to utilize modulation on divider [10] as shown in Fig.3.3. It has the same noise transfer function as the second method. Moreover, this technique could not achieve high modulation profile precision. Thus, the low jitter requirement cannot be satisfied.

Finally, the phase selection from the coherent multi-phase output of PLL is reported [11] and shown in Fig.3.4. Unfortunately, techniques in [10] and [11] both suffers serious glitch problem because of the operation of multiplexer.

Fig.3.1 Block diagram of a SSCG with modulation on VCO

out Control Signal CP PFD LF VCO Divider ref Modulation Signal Generator

20

Fig.3.2 Block diagram of a SSCG with modulation on input reference clock

Fig.3.3 Block diagram of a SSCG with modulation on divider

Fig.3.4 Block diagram of a SSCG with phase selection method

CP PFD LF VCO Divider vco Modulation Signal Generator ref C lo ck M ult ip le xe r CP PFD LF VCO Main Divider N1/N2/N3… ref _vco Modulation Signal Generator Divider

21

3.1.2 Noise Transfer Function

We derive the noise transfer function of each modulation mechanism to understand the noise performance of each of them. To do this, we can choose one of them as our basic modulation method to minimize quantization noise due to digital signal processing.

Fig.3.5 illustrates the equivalent linear model of each modulation mechanism. KPD is the gain of phase detector, F(s) means the transfer function of the loop filter,

VCO

K is the sensitivity of voltage control oscillator, and 1/N represents the divider ratio. The quantization noise of each method is listed below:

- f presents the output noise due to the quantization noise _out

- f_in models the quantization noise of a SSCG with modulation on input

reference clock

- f_c models the quantization noise of a SSCG with modulation on VCO

- f_r models the quantization noise of a SSCG with phase selection method

- f_d models the quantization noise of a SSCG with modulation on divider

The quantization noise and effective phase variation of each modulation method is shown below. The noise transfer function of each modulation method is given by

VCO PD VCO PD in out K s F K N s K s F K ) ( 1 ) ( + = f f (3.1) VCO PD VCO C out K s F K N s K s F ) ( 1 ) ( + = f f (3.2)

22 VCO PD VCO PD r out K s F K N s K s F K N ) ( 1 ) ( 1 + -= f f (3.3) VCO PD VCO PD d out K s F K N s K s F K ) ( 1 ) ( + -= f f (3.4)

Fig.3.5 Noise transfer function of each modulation mechanism

As shown in the Eqn.(3.1) to (3.4) , all of them reveal the low frequency passing characteristic. Therefore, the sigma-delta modulation is usually adopted to implement the modulation signal generator and the analysis of the quantization noise is almost the same. Although all the noise transfer function presents the same low-pass character, they have different DC gain. This feature makes the quantization noise effect quite different. Inserting s=0 in Eqn.(3.1) to (3.4) , we find the respective DC gain: N S in out ₌ =0 f f (3.5) c

f

in

f

d

f

out

f

e

f

r

f

23 PD S C out K N = =0 f f (3.6) 1 0 -= = S r out f f (3.7) N S d out ₌ -=0 f f (3.8)

Note that the DC gains are greater than one except the phase selection method. The quantization noise will be amplified through the PLL loop due to the closed loop gain. To achieve the same noise level at the output of PLL, a higher order of the sigma-delta modulation is required when the DC gain is higher. Thus, our design is based on the phase selection method published in [11].

Due to the same filter attribute, the transient response of spread spectrum behavior of a SSCG will be realized with modulation on input. All the other modulation mechanism can be accomplished with the corresponding input referred signal at the phase detector input. Using the concept, we can begin our transient response analysis with corresponding input referred signal at the phase detector input.

3.2 Discrete-Time Open-Loop Criteria of PLL

At first, we introduce the traditional continuous-time model of a second-order linear PLL based on [12] as shown in Fig.3.6 and then a discrete-time open loop analysis depending on [12]. Here the two tracking path are modeled as the gain of proportional path KP and the gain of integral path KI. The integral path helps to

24

suppress the static phase error because it provides infinite gain in the open loop of PLL. However, the integral path might make the loop of PLL unstable as a result of two poles at DC. Hence, a compensating zero or a proportional path is needed to stabilize the loop. As shown in Fig.3.6, the integral path sets one of the VCO frequency term to a time-integral of the past phase error with a gain KI. The

proportional path sets the other frequency term of the VCO proportion to the current phase error.

Fig.3.6 Continuous-time model of a second-order linear PLL

Note that we will make a link between open loop transfer function and closed loop transfer function to find the relationship of proportional gain KP and integral gain

KI to natural frequency ωn and damping factor ξ. To do this, the open-loop transfer

function of the PLL, LPLL(s), defined as ψout(s)/ ψerr(s) , is

) ( ) ( ) ( s s s L err out PLL _f f = ₂ s K sK_P + _I = (3.9) P I in

f

f

err

f

out

25

then, the closed loop transfer function HPLL(s) =ψout(s)/ ψin(s) is

) ( 1 ) ( ) ( s L s L s H PLL PLL PLL = ₊ I P I P K sK s K sK + + + = _{2 2 2} 2 2 2 n n n n s s s w xw w xw + + + = (3.10)

From the derivation above, we can expressωn and ξ in terms of KP and KI

I n = K w (3.11) I P n P K K K 2 2 = = w x (3.12)

We can express the proportional gain KP and integral gain KI with circuit design

parameters such as charge pump current IP, sensitivity of VCO KO, C1 in loop filter

and R1 in loop filter. From (3.11) and (3.12), KI and KP can be expressed as

1 C I K K P O I = ´ (3.13) K_P =I_P ´R₁´K_O (3.14)

Equation (3.13) implies that integral gain is proportional to the voltage slew rate of C1 in the loop filter with a proportional constant KO. The proportional gain is

26

the PLL loop characteristic in discrete time.

The above system behavior involves continuous-time quantity. But ψerr is

actually a sampled value when phase detector detects the phase error. The phase comparison can occur only once per cycle. Therefore, a PLL shall be described with discrete-time open loop characteristics. Fig.3.7 shows the discrete-time model of a PLL.

Fig.3.7 A discrete-time PLL models the changes in phaseΔΦ and in frequency Δωof each cycle due to the sampled phase error ψerr.

As shown in Fig.3.6, the integral frequency term ωI =KIψerr(s)/s can be

regarded as a discrete-time summation

å

--¥ = = = 1 ) ( ) ( ] [ n i I ref err ref I I n w nT K T f iTref w (3.15) ref

T is the input reference clock period. A similar derivation can be carried out

about the proportional frequency termωP(s)=KPψerr(s). If the resulting phase ψP =

ωP(s)/s is considered as the output, the corresponding discrete-time description can

be expressed as ψ ω

Σ

Σ

I

Δω

]

[n

in

f

]

[n

out

f

err

f

p

f

f

D

27

å

--¥ = = = ( ) 1 ( ) ]

[ _{P ref} n_{i P ref err}

P n f nT K T f iTref

f (3.16)

Following from equation (3.15) and (3.16), the frequency ωI and the phase ψP

shown in Fig.3.7 were updated the in each cycle. The modified quantities in each input reference clock cycle will be proportional to the current sampled phase error ψerr. ] 1 [ ] [ - -= Dw w_I n w_I n _err ref I err ref I K T K f w p f =2 = (3.17) ] 1 [ ] [ - -= Df f_P n f_P n _err ref P err ref P K T K f w p f = 2 = (3.18)

Equation (3.17) and (3.18) describes the open-loop dynamic equation that models the change in phase and frequency due to each sampled phase error. Since KI

= ωn2 and KP = 2ξωn, (3.17) and (3.18) become

err ref n err ref n ref

f

w

w

px

f

f

w

w

pw

w

4

)

(

2

2

=

D

=

D

(3.19)

We have derived the discrete-time open-loop criteria of a PLL. The dynamic equation describes change of frequency and phase in each cycle. This property can

28

help us to do transient response of spread spectrum behavior with PLL system parameters such as ωn and ξ.

3.3 Transient response of Spread Spectrum

With the derivation of the discrete-time open-loop criteria of a PLL, we can analyze spread spectrum behavior using digital signal processing. As shown in Fig.3.1, Fig.3.2, Fig.3.3 and Fig.3.4, Modulation Signal Generator is usually a digital processing block clocked by input reference clock of PLL by a specified ratio. Hence, we can develop the difference equation of spread spectrum behavior according to the concept of discrete-time open-loop criteria of a PLL.

The understanding of transient response of spread spectrum behavior can help to express the SSCG design requirement with PLL system parameters. As will be shown later, we will discover that the design consideration of SSCG would be different with different PLL system parameters.

In section 3.3.1, we discuss the behavior of SSC and model it as a equivalent difference equation expressed with PLL system parameters such asωn and ξ. Thus,

in section 3.3.2, we will display the transient response with different PLL system parameters and discuss about the design consideration. Finally, we show the effective frequency of spread spectrum clocking.

29

Fig.3.8 A modified discrete-time PLL model

To derive the difference equation of spread spectrum behavior from equation (3.19), we redraw the discrete-time PLL model as shown in Fig.3.8. Where _{K and w} Kψ are the open-loop integral gain and open-loop proportional gain, respectively and

are as defined as in Eqn.(3.19). _{T is the input reference clock period to present the ref} integration operation. Note that the spread spectrum behavior is performed when the PLL is in lock. Consequently, to produce spread spectrum equivalent frequency in each modulation mechanism, the effective phase jump at different location in the PLL loop can be transferred to input to simplify our analysis. And then the spread spectrum equivalent frequency can be modeled as a phase jump Δθ per reference clock cycle time. We neglect the input reference clock induced phase noise. So ψin[n] equals to

zero for simplifying analysis. Hence, we formulate the block diagram and display the phase error at each sampling time

]

[n

in

f

]

[n

out

f

err

f

f

D

30 q f_err[1]=D q f w f

f_err[2]= _err[1]-(D [1]´T_ref +D [1])+D

ref ref err err[3]=f [2]-(Dw[2]´T +Df[2])+Dq -Dw[1]´T f ]) 2 [ ] 1 [ ( ]) 3 [ ] 3 [ ( ] 3 [ ] 4 [ f w f q w w

f_err = _err - D ´T_ref +D +D -T_ref ´ D +D ... ]) 2 [ .. . ] 1 [ ( ]) 1 [ ] 1 [ ( ] 1 [ ]

[n = _err n- - D n- ´T_ref +D n- +D -T_ref ´ D + +D n

-err f w f q w w

f

We rearrange the equation mentioned above into the following ]) 1 [ .. ] 1 [ ( ] 1 [ ] 1 [ ] [ f q f w w

f_err n = _err n- +D -D n- -T_ref ´ D n- + +D _(3.20) Again, we can express the difference equation of f_err[n] in terms of open-loop gainK , and_w K , effective phase jump q_f D , andT that represents the integration _ref

operation. The new equation of f_err[n] is

q j j j = _j - - ´ _w

å

- +D = 1 1 ] [ ] 1 [ ) K -(1 ] [ n i err ref err err n n T K i (3.21)

We can analyze system response in discrete-time method based on (3.21) with _{K w} and K describing the characteristic of the PLL system. We can also demonstrate the _f

same system response in both open loop and closed loop description.

3.3.2

Transient Response of SSC with different PLL system

parameters

31

spread spectrum behavior. In this section, we will display and discuss the system response with different system parameters. Table.3.1 shows some general settings of PLL system parameters. These includew and ξ and substitute _n w_n and ξ into the open-loop parameters, K and _w K_f to get the relative value.

Table.3.1 The relative open-loop parameters according to different closed-loop parameters 2 1 = x 20 1 = ref n w w 40 1 = ref n w w 50 1 = ref n w w w K T_ref ´ 2 1001 p 2 4001 p 2 6251 p j K _p 10 2 _p 20 2 _p 25 2 1 = x 20 1 = ref n w w 40 1 = ref n w w 50 1 = ref n w w w K T_ref ´ 2 1001 p 2 4001 p 2 6251 p j K p 5 1 _p 10 1 _p 25 2 3 = x 20 1 = ref n w w 40 1 = ref n w w 50 1 = ref n w w w K T_ref ´ 2 1001 p 2 4001 p 2 6251 p j K p 5 3 _p 10 3 _p 25 6

32 5 . 0 = x 20 1 = ref n w w 40 1 = ref n w w 50 1 = ref n w w w K T_ref ´ 2 1001 p 2 4001 p 2 6251 p j K p 10 1 _p 20 1 _p 25 1

We simulate the difference equation (3.21) in Matlab with corresponding coefficient settings in Table.3.1. The test pattern is 5000ppm frequency deviation with effective input referred phase jump= p

100 1

at the phase detector input and the sampling frequency equals the input reference clock frequency. We define the ratio

ref n w w = K. (a)

33

(b)

34

(d)

Fig.3.9 Transient response of phase error j_err[n] with damping factor (a) 0.5, (b) 0.707, (c) 1 and (d) 3

Notice that we make some observations could be made on the results of Fig.3.9 and Table.3.1.

(1) We note that the damping factor x does not affect the open-loop integral gain. (2) Open-loop phase tracking gainK is directly proportional to damping factor_f x .

(3) When the natural frequency to input clock frequency ratio

ref n

w w

is determined, the corresponding frequency tracking gain is also decided.

From the observations above, the four cases all shows that the larger the

ref n

w w

, the faster the system response. It means that the frequency tracking gain increases as

ref n

w w

is increased with phase tracking gain unchanged. Hence, the tracking process is performed more quickly. We also note that for under damping ones, Fig.3.9 (a) and (b),

35

there are oscillations before the settling point is approaching. This shows the same transient behavior as the conventional continuous-time one. With the discrete-time analysis, we have the other exposition about the oscillations before settling. The frequency tracking gain is too large relative to phase tracking gain. Therefore, the frequency tracking would exceed the desired frequency jump and then the phase error will ring because of the wrong frequency tracking direction. Similarly, as shown in Fig.3.9 (d), over damping case will slow down the system response as the conventional one. The phase error tracking would oscillate at the beginning due to the large phase tracking gain. The large phase tracking gain slows down the frequency tracking action because the phase error j could not stay high radians for enough _err time to complete frequency tracking.

3.3.3 Effective Spread Frequency with Different Phase Jump

In fact, the effective spread spectrum frequency tracking is more interested in system behavior. In this section, we will show the frequency tracking behavior to prove that the discussion in section 3.3.2 and examine the effect on the amount of phase jumpDq .

The popular promising technology like Serial-ATA defines the EMI reduction using spread-spectrum clocking with 5000ppm frequency deviation. When the spread spectrum is performed with digital signal processing, the desired triangular modulation profile will like a triangular modulation profile with stairs. The number of stairs and step size of the stair might affect the outcome of spread spectrum behavior. As can be shown from Fig.3.10, the transient response is just like the traditional step response of a PLL system because the phase jumps at each phase detection works

36

equivalent to a frequency step applied to a PLL system.

(a)

(b)

Fig.3.10 Transient response of spread frequency deviation with (a) 50ppm (b) 5000ppm

37

As can be seen in Fig.3.10 (a) and (b), the response behaviors are almost the same except the scale of the vertical axis. The response time of a system is regardless of the spread frequency deviation. This is because in the linear-time invariant system, the output response is scaled by the same factor when the input is scaled by a factor. Therefore, the change of the amount of phase jump will not influence system response.

To reach the specification of spread frequency deviation, we would like to have fewer stairs in our triangular modulation profile when the response time of the system is long.

3.4 Overall Spread Spectrum Behavior

In this section, the overall spread spectrum behavior will be shown with different system parameters. Design consideration to achieve the maximum reduction of clock power and minimum cycle-to-cycle jitter of SSCG will be discussed.

It should be note that quantization noise is induced when the digital signal processing schemes are used. We first describe the overall spread spectrum behavior without quantization noise to survey the response behavior when different design parameters are used. Secondly, suppose we are designing the block of the spread spectrum circuit using digital method. We can anticipate that quantization error is produced through the digital operation. Sigma-delta modulation skill is usually used to push the quantization noise to high frequency band. Consequently, the analysis of the sigma delta modulation is included. First order and second order delta sigma modulation will be introduced.

38

Finally, the jitter concern is critical when the spread spectrum clock is in use in the receiver for data rate of 6Gbps. This means that the jitter performance always shall be carried out, especially the cycle-to-cycle jitter.

3.4.1 Spread Spectrum behavior without Quantization Noise

The overall spread spectrum behaviors are shown in Fig.3.11 (a) and (b) with

ref n w w equals 20 1 and 0 5 1 . (a)

39

(b)

Fig.3.11 Overall spread spectrum behavior with (a)

20 1 = ref n w w (b) 0 5 1 = ref n w w

Fig.3.11 is ideal processing without digital signal processing. The quantization error is neglected to see the relationship between transient behavior and system parameters, such as w_n and ξ. Fig.3.12 shows the histogram distribution of spread frequency deviation. Note again that the histogram does not show the absolute distribution of spread frequency deviation but a relative distribution. Each histogram shows the difference between ideal frequency distribution with perfect triangular modulation profile and spread frequency distribution with different

ref n

w w

and damping factor. Consequently, we determine the PLL system parameters with more uniformly distributed one.

40

(a)

41

(c)

(d) Fig.3.12 Histogram for

0 2 1 = ref n w w

(a) under damping case (b) over damping case and 0 5 1 = ref n w w

42

Fig.3.12 provides several insights to the design and consideration of a SSCG: A. If the transient response of the spread spectrum behavior is more similar to an

ideal triangular modulation profile, the uniform distribution is achieved.

B. The faster the transient response is, the more specific frequency terms are accumulated.

C. The slowest response shown in Fig.3.12 (d) indicates that the desired maximum frequency deviation cannot be reached.

D. More stairs will make the transient response more like an ideal triangular modulation profile in a fast response system.

3.4.2 Sigma-Delta Modulation with Different Orders

Here we highlight the sigma-delta modulation method and the comparison between the 1st order sigma-delta modulation and 2nd order sigma delta modulation will be performed.

From Fig.3.13 to Fig.3.16 we see that the responses of different systems with different order of sigma delta modulation are illustrated. Again, the histograms display the relative distribution of spread frequency deviation and an ideal histogram is shown as reference level. There is one important thing to note is that the loop is a 2nd order system. Supposing that additional pole or zero is inserted into the loop filter, the system analysis will be different. A 3rd or 4th order system analysis and modeling should be carried out and the transient response is quite different to the second order analysis.

43 (a) (b) Fig.3.13 0 2 1 = ref n w w

and under damping operation with (a)1st order modulation (b) 2nd order modulation

44 (a) (b) Fig.3.14 0 2 1 = ref n w w

and over damping operation with (a)1st order modulation (b) 2nd order modulation

45 (a) (b) Fig.3.15 0 5 1 = ref n w w

and under damping operation with (a)1st order modulation (b) 2nd order modulation

46 (a) (b) Fig.3.16 0 5 1 = ref n w w

and over damping operation with (a)1st order modulation (b) 2nd order modulation

47

Some observations and design consideration are summarized below:

A. Compare with that without quantization, the quantization noise is apparent in the waveform of overall spread spectrum behavior, especially in higher open-loop integral gain and higher order sigma-delta modulation.

B. Comparing 0 5 1 = ref n w w cases with 0 2 1 = ref n w w

ones, less quantization noise appears in the 0 5 1 = ref n w w

cases due to the high frequency quantization noise would be filtered by the narrow system bandwidth.

C. The 2nd order modulation method would contribute more quantization noise without additional pole in the loop filter and hence the poor cycle-to-cycle jitter performance.

D. If the additional pole to filter the high frequency term, the better suggestion is to choose the first order modulation to alleviate the quantization error.

3.4.3 Timing Impacts

This section will show intuitive understanding of the low cycle-to-cycle jitter design [13]. Equation (3.22) defines the cycle-to-cycle jitterDT_CC in conventional way 2 1 1 ) ( 1

lim

å

= + ¥ ® -= D N n n n N CC T T N T (3.22)

The nth clock period is defined as Tn. A more general quantification of the jitter is

possible by means of autocorrelation function defined as

å

= + ¥ ® D = N n n m n N T T T N m C 1 ) ( 1 ) (

lim

(3.23)

In order to express the cycle-to-cycle jitter by (3.23), we rewrite (3.22) as

å

= + ¥ ® -= D N n n n N CC T T N T 1 2 1 2 ) ( 1

lim

=2C_DT(0)-2C_DT(1) (3.24)

48

To express the cycle-to-cycle jitter in SSC, we can model the VCO output frequency of SSCG as a sinusoidal wave first for convenience.

Df_m(t)= K_mcosw_mt (3.25) where Km represents the coefficients of Fourier series composed of a frequency term

with frequency ofw . The deviation of the period is _m

o m o f t f f t T 1 ) ( 1 ) ( -D + = D t f K m o m _cosw 2 » _(3.26)

We can obtain the continuous-time autocorrelation function shown below

t w t _m o m f K t T t T cos 2 ) ( ) ( ₄ 2 = D + D (3.27)

If the continuous-time autocorrelation function does not change significantly during one period, the discrete-time autocorrelation function can be approximated by continuous-time autocorrelation function. For Dt =0 and

o f 1 T= = Dt , we can obtain the cycle-to-cycle jitter from (3.24) to (3.27).

) cos( 1 2 o m o m CC _f f K T = - w D _(3.28)

For fm << f we find from (3.28) _o

3 2 _o m m CC f K T » w D _(3.29)

Notice that from (3.28) and (3.29), the design considerations are

A. A real modulation profile can do the Fourier series expansion and the corresponding coefficients can replace coefficients into (3.28) and (3.29) to get the cycle-to-cycle jitter.

B. Once the high frequency term is included in the Fourier series expansion, the cycle-to-cycle jitter will be worse.