Chapter 4 Algorithm of the Proposed Spread Spectrum Clock Generator
4.4 ΣΔ Modulator
As described in section 4.2, values from 0 to 9.6 are required in the phase rotation of the spread spectrum operation. A sigma-delta modulation technique is
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adopted in such applications to carry out the fractional number, such as from 0 to 9.6.
An average concept presents the desired value again on the basis of digital signal second order modulator is used to shape the quantization noise. The first accumulator with input K calculates the average fractional number while the second one performs the phase error spectral shaping.
(a) (b)
Fig.4.10 Equivalent digital implementation of a sigma delta modulator with (a) first order and (b) second order module
The modulation mechanism based on modulation on VCO [8], modulation on input [9], and modulation on divider [10] reveals that DC gain is larger than one and hence the quantization noise is amplified. A higher order sigma delta modulation is accomplished to shape the amplified quantization noise in these modulation
X
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mechanisms. The technique [11] presents that the noise transfer function developed in Chapter 3 is equivalent to unity at DC so extra orders of modulation to shape the quantization noise are not necessary. The higher order modulator in our design would contribute more spikes in the modulation profile because a large input step make the system response with large output step. These high frequency spikes will enlarge the cycle-to-cycle jitter. Accordingly, we adopt the first order sigma delta modulation implementation for our proposed SSCG.
The accumulator should be implemented in a digital approach and we must decide the size of the accumulator. The size of the accumulator gives another design parameter mentioned in section 4.2. It is the number of the stairs in the modulation profile. For our example, a 4-bit accumulator is used so that the desired K in the sigma delta module equals to 24´9.6=153.6 and should be truncated to 153 to promise the maximum frequency deviation not larger than 5000ppm. Therefore, the desired amount of phase rotation, from 0 to 9.6 is accomplished by the accumulator with integer value from 1 to 153 as the input of accumulator.
If the size of accumulator is too large or too small, the EMI reduction and cycle-to-cycle jitter performance become worse. Because a larger size of accumulator means more number of stairs in the modulation profile and vice versa. The impact of number of stairs in the modulation profile impacting on the behavior of SSCG has been discussed in section 4.2.
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Chapter 5
Circuit design of Spread Spectrum Clock Generator
5.1 Introduction
A proposed spread-spectrum clock generator for Serial ATA with phase rotation is presented. To achieve low jitter issue in our design, PLL uses error amplifier to resolve the current mismatch in charge pump and a third order loop filter is adopted to reduce the reference spur. A passive resistor is presented in the VCO delay cell to reduce the Kvco gain and an additional cross-couple CMOS is also included to the delay cell to boost the operation of delay cell. Our spread spectrum clock generator (SSCG) for Serial ATA Specification is down spread 5000ppm with a triangular modulation profile and the modulation frequency is 30 kHz. A spread spectrum technique using PLL with a sigma delta modulator and phase rotation algorithm is proposed. This proposed architecture has been designed in a 90-nm CMOS process.
The non-spread clocking has a peak-to-peak jitter of 3.88ps and consumes 5.87mW at 1.4GHz. The EMI reduction in this circuit is about 18.22dB.
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5.2 System architecture
The building block of the proposed SSCG architecture is shown in Fig.5.1. In our design, a SSCG, controlled by sigma delta modulator and phase rotator with interpolator can enhance the performance of SSCG. The proposed phase rotation mechanism can avoid output glitch of SSCG when the phase select is changed.
The modulation profile unit generates a periodic triangular waveform to feed into the sigma delta modulator. Sigma delta modulator converts the input signal to the desired fractional number which transmits through the phase rotator block to control the amount of phase rotation. Through a proper choice of the amount of the phase rotation by digital control scheme allows exact amount of frequency deviation.
Fig.5.1 The architecture of SSCG with phase rotation technique
CP
PFD LF VCO
5 to 1 Phase multiplexer
5 5
Phase interpolator
1 1
1/12
Modulation profile
Δ-Σ Mux & interpolator control
10 24
Phase Rotator for Spread spectrum
fref
fout
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In order to confirm the SATA specifications, an 4-bits accumulator is adopted and the accumulator input, K runs periodically through 0, 1, 2,…, 152, 153, 152, 151,…, 0. The maximum frequency deviation is 4980ppm with 30 us modulation period.
5.3 Behavior Simulation
The forth order PLL design consideration is covered in Chapter 2 and (2.12) describes the stability of the PLL system. Eqn. (2.12) also shows adequate phase margin and the value of corresponding system components. First, we design our PLL circuit with third order closed form so that we can determine the circuit parameters.
Thus, we put additional third high frequency pole into the loop filter. The location of the third pole should be high enough comparable to the second pole in the loop filter to guarantee the accuracy of the third order PLL analysis. To our experience, it shall at least four times larger than the second pole in the loop filter.
To start with the 60 degree of phase margin, we also set the open loop unit gain frequency equal to one fiftieth input reference frequency (wt wref
50
= 1 ). In order to
ease the effect of leakage current, we choose the charge pump current to be 50 uA.
The sensitivity of VCO output frequency to its input control voltage is defined as KVCO which is obtained from the simulation. Also note that the additional third pole in the loop filter is used to suppress the reference spur due to the periodic operation of PFD and phase rotation mechanism. This is designed based on (2.17) and should be put into higher frequency band mentioned above.
According to the discussion above, we get the design parameters as shown in Table.5.1.
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Table.5.1 Corresponding system components
KVCO 700MHz/V
Ip 50 uA
C1 70pf
C2 4.6pf
R1 4.5kΩ
N(divider ratio) 12
R2 1.8 kΩ
C3 1.8pf
The open loop unit gain frequency is 100MHz divided by 50. Hence, wt =2MHz.
Besides, a 60 degree of phase margin requires the frequency of the second polewp2 in
the loop filter is four times of wt and we havewp2 =8MHz. The third pole should be at least 32MHz to promise the stability of this feedback system. We rewrite (2.17) as shown below indicates that the frequency response of the forth order PLL almost overlaps the third order one for frequency below the open loop unit gain frequency. The extra pole
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works as the frequency exceeds the third pole frequency and the attenuation is about 10dB which conforms (5. 1).
Fig.5.2 Frequency response of 3rd order and 4th order PLL
5.4 Circuit Implementation
In the following, the circuit implementation will be presented, including the major blocks of PLL, and a phase rotation control that enabling the spread spectrum.
The PLL is consist of phase frequency detector (PFD), charge pump (CP), loop filter (LF), voltage-controlled oscillator (VCO), and divider. The circuit implementation and characteristics are illustrated. The simulation results with HSPICE (analog) NERO-SIM (mixed signal) simulation will be shown in the end.
About 10dB Phase Margin = 60 degree
Frequency (rad/s)
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5.4.1 Phase / Frequency Detector
The sequential phase frequency detector (PFD) is illustrated in Fig.5.3 [14]. One of the characteristics of this PFD is the small intrinsic parasitic so that the speed limitation would be overcome. Another attribute is the dead zone reduction. Fig.5.3 (b) shows the timing diagram of PFD. In the case of in-phase, the UP and DOWN create the same width of pulse which is designed for matching the turn-on time of charge pump. The PFD creates the lead and lag information with the width of UP and DOWN pulse, respectively. Fig.5.3 (c) presents the single to differential circuit to produce the differential signal for using in the charge pump.
(b)
(a) (c)
Fig.5.3 Phase frequency detector (a) schematic (b) timing diagram (c) Single to Differential circuit
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5.4.2 Current Matching Charge Pump
The charge pump circuit with error amplifier applied to resolve current mismatch is presented in [15]. Fig.5.4 illustrates this design of charge pump circuit. The conventional CMOS charge pump circuits have some current mismatch due to the channel length modulation effect, especially in deep sub-micron process. Both current mismatch and leakage current generate phase offset in PLL and the corresponding spur is produced. Hence, an additional jitter is displayed at the PLL output clocking.
When the current mismatch or leakage current occur, the amount of the average phase offsets is given by [7]
where q is the average phase offset, b I is the average leakage current or the average b mismatch current per cycle, and I is the charge pump current in design. Eqn. (5. 2) cp can be further formulated as [15]
T amount of charge pump current.
In Fig.5.4, M7~10 is the replica of the charge-pump path made of M1~4. An operational amplifier OP2 is added to let the ref voltage follow the Cpout voltage by a negative feedback loop. Charge current and discharge current can be matched by the
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feedback loop due to the same drain voltage in the charge and discharge current source. As long as gain of OP2 is high, voltage at ref and Cpout are almost the same and in the locking state, they are almost constant. Thus, I2 is also equals to I3 and the feedback loop equalize the ref and Cpout voltage so that the bias condition of M7~10 is the perfect replica of M1~4. As a result, Icp2=I3 and Icp1=I2, and this will force Icp1=Icp2. A current matching is achieved. The proposed charge pump changes the location of the switch, M2~3 with the location of current source, M1 and M4, to reduce the turn-on time [15] of the current source. In this way, we can avoid the additional jitter induced by the long turn-on time of the current source. Fig.5.5 shows the current variations against output voltage (cpout) variations of the charge pump circuit.
Fig.5.4 Charge pump circuit
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(a) (b)
Fig.5.5 Charge Pump current matching characteristic (a)Conventional charge pump (b) proposed charge pump.
5.4.3 3th Order Loop Filter
In order to suppress the additional spur due to the phase rotation mechanism, the usage of the third order loop filter is adopted and shown in Fig.5.6. We implement the resistor with a standard cell P+ Poly resistor without salicide (RNPPO) provided by UMC and choose Mixed Mode MIM capacitor (MM MIMCAPs) as our capacitor design.
Fig.5.6 Third order loop filter
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5.4.4 Voltage-Controlled Oscillator
Our VCO is based on the design published in [16]. The self-biased technique is adopted to track the supply and substrate induced noise. The operational amplifier used in bias replica is also self-biased and tracks the VCO oscillating frequency so that the suppression of the supply and substrate induced jitter remains nearly constant during the full tuning range of PLL.
As shown in Fig.5.7, the delay cell presneted in this design resembles the one in [16]. We make a little modifications about inserting a passive resistor in parallel with the symmetric load composited of M1~2 and M7~8. Another modification is that the CMOS cross-coupled pair is adopted, which is denoted as M3, M6, M5, and M9. The primary function of the inserted passive resistor is to lower the KVCO and to promote the linearity of the symmetric load for low jitter design concern. The lower KVCO
would mitigate the sensitivity of VCO due to the noise contributions in the loop filter.
The linearity of the loading in the delay cell can alleviate the supply and substrate induced noise and the harmonic terms perturbations. The additional cross-coupled pair boosts the transition of the delay cell output waveform. Hence, it helps to keep the high level or low level of the swing of waveform to the saturation level when the oscillating frequency is minimum or maximum of the allowed VCO frequency.
Fig.5.8 shows the operating frequency with different VCO input control voltages. The resulting sensitivity of VCO is about 670MHz/V.
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Fig.5.7 VCO delay cell
Fig.5.8 Operating Frequency with different Vctrl voltage(post-layout)
5.4.5 Multiplexer and Interpolator
Fig.5.9 and Fig.5.10 illustrate the multiplexer and interpolator, respectively. Both
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of them are used in the phase rotator. The multiplexer and interpolator design are also based on the delay cell design [16], which consists of the symmetric load and the differential pair. Additional bias circuit for the multiplexer and interpolator is required to limit the output swing for low jitter purpose. The multiplexer selects the adjacent phase from VCO and send it to the phase interpolator. The proposed interpolator generates the corresponding phase rotation with a specific interpolation ratio. It would produce the correlated frequency deviation in the process of the phase rotation. The interpolator changes its interpolation ratio with a thermal code control for the reason of the monotony of phase rotation.
Fig.5.9 Multiplexer
S0 S1 S4
in0 in1 in4
S0 S1
S4
in0#
in1#
in4#
Out# Out
bp
bn
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Fig.5.10 Thermal code controlled interpolator
5.4.6 Divider
The frequency divider in the feedback path of PLL is to divide by 12 as shown in Fig.5.11. We use the asynchronous circuit blocks in order to overcome the speed limit of divider and to lower the power saving consumption at the same time. The first divide-by-2 block is placed at the first stage of the divider since it experiences the fastest operating frequency from the VCO output. The other divide-by-2 block is adopted behind the divide-by-3 to adjust the duty cycle of the divid3-by-3 output to reach a 50% duty cycle. At the last stage, a D flip-flop re-samples the clock dividing by 12 to align with the input clock. On the other hand, the last stage D flip-flop suppresses the accumulated jitter due to the asynchronous operation. We use the true single phase circuit (TSPC) in the circuit implementation of divider for the purpose of the high speed requirement.
bn
2x 1x 1x 2x 1x 1xin1 in1# in2 in2#
bp
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Fig.5.11 Schematic of divider
5.5 Circuit Simulation
Because the circuit implementation involves the analog and digital design, a mixed-signal simulation tool is requested to simulate the mixed-mode circuit. We simulate the analog circuit behavior with HSPICE and the mixed-signal simulation is carried out by NENO-SIM.
We simulate the modulated clock signal and non-modulated clock signal for the same time such that both have the total signal power. An FFT calculation is adopted to display the frequency domain behavior of the VCO output clock with and without modulation. Fig.5.12 (Pre-Layout) presents the spectrum of the VCO output waveform with and without spread spectrum operation. The VCO output clock is operating at 1.38GHz, the modulated clock is down-spreading 5000 ppm and the corresponding EMI reduction is 20.6dB. The time domain simulation results of the proposed SSC are shown in Fig.5.13. This diagram shows the period of VCO output vs. time. The maximum cycle-to-cycle jitter is about 1.128ps during the spread spectrum operation.
Q
D Q Q
D Q Q
D Q
Q
D Q Q
D Q
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Fig.5.12 Spectrum of VCO output clock with and without spread spectrum modulation(Pre-Layout)
Fig.5.13 Period of VCO output waveform vs. time(Pre-Layout)
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Fig.5.14 presents the spectrum and timing diagram of modulated clock signal with 1st and 2nd order modulator. The spectrum of SSCG with 1st order modulator is marked with solid line and the spectrum of SSCG with 2nd order modulator is marked by + with dashed line. Both of them almost overlap with the each other. This is consistent with the analysis as shown in Fig.3.16 (a). The period of VCO output waveform vs. time is shown in Fig.5.14. The first order one is presented with dot line and the second one is presented with solid line. The cycle-to-cycle jitter performance is better in the 1st order case due to the small input step to the PLL system. Hence, a circuit design with 1st order sigma delta modulator would be adopted.
(a)
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(b)
Fig.5.14 1st order and 2nd order modulation comparison (a) spectrum (b) Period of VCO output waveform vs. time(Pre-Layout)
Fig.5.15 shows the different number of stairs in the modulation profile. We adopt 153 stairs and 20 stairs to verify our analysis in Chapter 3. Fig.5.15 (a) shows a larger spike in 153 stairs case than 20stairs one about 4dB. This is because our design is based on
50
= 1
ref
w t
w which represents a slow response system. The slow response
system might experience an undesired frequency accumulation in high frequency band due to slow response as shown in Fig.3.16 (b). The desired maximum frequency deviation can not be reached as shown in Fig.5.15 (b). The circle marker shown in Fig.5.15 (b) presents the 153 stairs case seems to stop the spread spectrum behavior first. The resolution of phase rotation has been decided by TVCO
160
1 . Hence, too many
stairs in modulation profile would lead to a stop action of spread spectrum behavior due to the insignificant amount of phase rotation.
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(a)
(b)
Fig.5.15 153 stairs and 20 stairs comparison (a) spectrum (b) Period of VCO output waveform vs. time(Pre-Layout)
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A post-layout simulation result of non-spreading clock is shown as Fig.5.16. It presents the RMS jitter is 0.8ps and the peak-to-peak value is up to 3.88ps. The jitter histogram is also shown in Fig.5.16. A jitter distribution is usually Gaussian and centers at the middle the ideal clocking edge. Once mismatches of the circuit occur, this would lead to an unbalanced jitter distribution, such as current mismatch in CP, leakage current. The eye diagram of uniformly distributed multi-phase output waveform of VCO is shown in Fig.5.17. There are ten uniformly distributed phase because five stages of VCO is adopted. Fig.5.18 shows the timing diagram of VCO control voltage during the acquisition process. The VCO control voltage settles until the PLL system is in lock. The settling time is less than 3us as shown below.
Fig.5.16 Eye diagram of VCO output and Jitter histogram without SSC(Post-Layout)
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Fig.5.17 VCO output waveform(Post-Layout)
Fig.5.18 Vctrl tracking behavior(Post-Layout)
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The simulation results of PLL and SSCG are summarized in Table.5.2 and Table.5.3, respectively. The spread spectrum modulation block is inserted into the PLL loop to perform the spread spectrum operation and the original PLL design remains unchanged. The power consumption in SSC mode includes the original PLL power consumption and the phase rotation block, including multiplexer, interpolator and relative buffer. Table.5.4 shows the comparison with other SSCG.
Table.5.2 Design summary of the proposed PLL
Items PLL
Technology UMC 90nm 1P9M
Power Supply 1V
Crystal Frequency 100MHz
VCO tuning frequency 1.3~1.5GHz
KVCO 670MHz/V
Settling time <3us
Jitter performance σRMS 810fs
σp2p 3.88ps
Power consumption 5.87mW
Core Area Main circuit 170´80um2
Loop Filter 235´325um2
Table.5.3 Design summary of the proposed SSCG
Modulation Frequency 30kHz
Max. Frequency Deviation 4983ppm
EMI reduction 20.6dB
Core Area PLL Main circuit 170´80um2
Loop Filter 235´325um2
Phase Rotation Block 170´20um2 Jitter performance Cycle-to-cycle
(P2P)
1.13ps
Power consumption 7.57mW
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Table.5.4 Comparison of SSCG Proposed
1.2GHz 1.5GHz 1.5GHz 27MHz(reference
clock)
EMI Reduction/BW 3.43dB/MHz 1.3 dB/MHz 2.7 dB/MHz Power
5.6.1 Layout and Pad Assignment
The proposed SSCG has been implemented with 90nm CMOS process. Fig.5.19 shows the chip layout of SSCG and the area of the PLL main circuit is 170´80um2.
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supply de-coupling capacitance, bias capacitance and pad.
Table.5.5 Pad Assignment presents the corresponding pad assignment and describes the pad configuration. The high speed inputs/outputs, including EQ
Table.5.5 Pad Assignment presents the corresponding pad assignment and describes the pad configuration. The high speed inputs/outputs, including EQ