Chapter 5 Circuit design of Spread Spectrum Clock Generator
5.5 Circuit Simulation
Because the circuit implementation involves the analog and digital design, a mixed-signal simulation tool is requested to simulate the mixed-mode circuit. We simulate the analog circuit behavior with HSPICE and the mixed-signal simulation is carried out by NENO-SIM.
We simulate the modulated clock signal and non-modulated clock signal for the same time such that both have the total signal power. An FFT calculation is adopted to display the frequency domain behavior of the VCO output clock with and without modulation. Fig.5.12 (Pre-Layout) presents the spectrum of the VCO output waveform with and without spread spectrum operation. The VCO output clock is operating at 1.38GHz, the modulated clock is down-spreading 5000 ppm and the corresponding EMI reduction is 20.6dB. The time domain simulation results of the proposed SSC are shown in Fig.5.13. This diagram shows the period of VCO output vs. time. The maximum cycle-to-cycle jitter is about 1.128ps during the spread spectrum operation.
Q
D Q Q
D Q Q
D Q
Q
D Q Q
D Q
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Fig.5.12 Spectrum of VCO output clock with and without spread spectrum modulation(Pre-Layout)
Fig.5.13 Period of VCO output waveform vs. time(Pre-Layout)
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Fig.5.14 presents the spectrum and timing diagram of modulated clock signal with 1st and 2nd order modulator. The spectrum of SSCG with 1st order modulator is marked with solid line and the spectrum of SSCG with 2nd order modulator is marked by + with dashed line. Both of them almost overlap with the each other. This is consistent with the analysis as shown in Fig.3.16 (a). The period of VCO output waveform vs. time is shown in Fig.5.14. The first order one is presented with dot line and the second one is presented with solid line. The cycle-to-cycle jitter performance is better in the 1st order case due to the small input step to the PLL system. Hence, a circuit design with 1st order sigma delta modulator would be adopted.
(a)
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(b)
Fig.5.14 1st order and 2nd order modulation comparison (a) spectrum (b) Period of VCO output waveform vs. time(Pre-Layout)
Fig.5.15 shows the different number of stairs in the modulation profile. We adopt 153 stairs and 20 stairs to verify our analysis in Chapter 3. Fig.5.15 (a) shows a larger spike in 153 stairs case than 20stairs one about 4dB. This is because our design is based on
50
= 1
ref
w t
w which represents a slow response system. The slow response
system might experience an undesired frequency accumulation in high frequency band due to slow response as shown in Fig.3.16 (b). The desired maximum frequency deviation can not be reached as shown in Fig.5.15 (b). The circle marker shown in Fig.5.15 (b) presents the 153 stairs case seems to stop the spread spectrum behavior first. The resolution of phase rotation has been decided by TVCO
160
1 . Hence, too many
stairs in modulation profile would lead to a stop action of spread spectrum behavior due to the insignificant amount of phase rotation.
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(a)
(b)
Fig.5.15 153 stairs and 20 stairs comparison (a) spectrum (b) Period of VCO output waveform vs. time(Pre-Layout)
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A post-layout simulation result of non-spreading clock is shown as Fig.5.16. It presents the RMS jitter is 0.8ps and the peak-to-peak value is up to 3.88ps. The jitter histogram is also shown in Fig.5.16. A jitter distribution is usually Gaussian and centers at the middle the ideal clocking edge. Once mismatches of the circuit occur, this would lead to an unbalanced jitter distribution, such as current mismatch in CP, leakage current. The eye diagram of uniformly distributed multi-phase output waveform of VCO is shown in Fig.5.17. There are ten uniformly distributed phase because five stages of VCO is adopted. Fig.5.18 shows the timing diagram of VCO control voltage during the acquisition process. The VCO control voltage settles until the PLL system is in lock. The settling time is less than 3us as shown below.
Fig.5.16 Eye diagram of VCO output and Jitter histogram without SSC(Post-Layout)
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Fig.5.17 VCO output waveform(Post-Layout)
Fig.5.18 Vctrl tracking behavior(Post-Layout)
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The simulation results of PLL and SSCG are summarized in Table.5.2 and Table.5.3, respectively. The spread spectrum modulation block is inserted into the PLL loop to perform the spread spectrum operation and the original PLL design remains unchanged. The power consumption in SSC mode includes the original PLL power consumption and the phase rotation block, including multiplexer, interpolator and relative buffer. Table.5.4 shows the comparison with other SSCG.
Table.5.2 Design summary of the proposed PLL
Items PLL
Technology UMC 90nm 1P9M
Power Supply 1V
Crystal Frequency 100MHz
VCO tuning frequency 1.3~1.5GHz
KVCO 670MHz/V
Settling time <3us
Jitter performance σRMS 810fs
σp2p 3.88ps
Power consumption 5.87mW
Core Area Main circuit 170´80um2
Loop Filter 235´325um2
Table.5.3 Design summary of the proposed SSCG
Modulation Frequency 30kHz
Max. Frequency Deviation 4983ppm
EMI reduction 20.6dB
Core Area PLL Main circuit 170´80um2
Loop Filter 235´325um2
Phase Rotation Block 170´20um2 Jitter performance Cycle-to-cycle
(P2P)
1.13ps
Power consumption 7.57mW
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Table.5.4 Comparison of SSCG Proposed
1.2GHz 1.5GHz 1.5GHz 27MHz(reference
clock)
EMI Reduction/BW 3.43dB/MHz 1.3 dB/MHz 2.7 dB/MHz Power
5.6.1 Layout and Pad Assignment
The proposed SSCG has been implemented with 90nm CMOS process. Fig.5.19 shows the chip layout of SSCG and the area of the PLL main circuit is 170´80um2.