Chapter 1 Introduction
1.2 Thesis Organization
Expect for pipelined ADC, we propose a low power CMOS bandgap reference circuit. This bandgap reference circuit is designed by using MOSFETs operated in weak-inversion region instead of BJTs to reduce power consumption. Basically the bandgap reference circuit could provide stable reference voltages and bias voltages to our pipelined ADC. The relationship of bandgap reference circuit and pipelined ADC is shown in Figure 1.1.
Figure 1.1 The relationship of bandgap reference circuit and pipelined ADC
1.2 Thesis Organization
This thesis is organized into six chapters.
In Chapter 1, this thesis is briefly introduced.
Chapter 2 describes the concepts of analog-to-digital conversion and performance parameters used to characterize ADCs. Then, several ADC architectures are introduced and the evolution of the pipelined ADC is presented. Then, the digital error correction technique and the 1.5-bit architecture are described. Finally, the timing of the pipelined ADC is analyzed.
Chapter 3 describes the key circuit blocks used in pipelined ADC. Among them are the operational amplifier, the common mode feedback, the comparator, the bootstrapped switch, the sample-and-hold amplifier (SHA), the 1.5-bit architecture, and the 2-bit flash converter. Then, the transistor level simulated results of each circuit are presented. Finally, the simulation of the whole pipelined ADC and its layout and floor plan are presented.
Chapter 4 presents the testing environment, including the component circuits on the DUT (device under test) board and the instruments. Then, the pipelined ADC described in Chapter 3 is fabricated in a standard TSMC 0.18µm CMOS Mixed-Signal process and the measured results of this chip are summarized.
Chapter 5 described the principle of the new low-power CMOS bandgap reference circuit. Finally, the simulated results of this CMOS bandgap reference circuit are presented with the standard TSMC 0.18µm CMOS Mixed-Signal process.
Finally, the conclusions of this thesis are summarized in Chapter 6.
Chapter 2
General Design Consideration in Pipelined A/D Converters
2.1 Introduction
Many practical integrated circuit realizations of pipelined A/D converters have been successfully implemented over past decade. This Chapter first presents the main performance parameters used to access the static and dynamic behaviors of Nyquist A/D converters and then introduces some of the prominent ADC architectures.
2.2 Performance Parameters In Nyquist A/D Converters
In conventional Nyquist A/D converter the accuracy can be defined by comparing every input sample and the corresponding output sample. Figure 2.1 illustrates the ideal conversion characteristic of a 3-bit ADC. The transition voltage can be written as
2 ,
ref
tn N
V =V ⋅n n∈
{
0,1, 2,..., 2N −1 ,}
(2.1)where N and Vref represent the bit numbers and the applied reference voltage respectively. The quantization step (VLSB) is the difference of two transition voltages and it can be written as
2
ref
LSB N
V =V . (2.2)
Figure 2.1 Ideal conversion characteristic of a 3-bit ADC
2.2.1 Offset and Gain Error
The error of an A/D converter is the difference between the theoretical and the actual input voltage required to produce a particular output code. In most applications the user can calibrate the offset and gain errors by subtracting the offset and dividing by the gain.
Offset error is the difference between the theoretical transition voltage and the actual transition voltage relatively to the quantization step. Gain error indicates the slope difference between the lines connecting the theoretical and actual transitions of the full scale extremes.
Figure 2.2 illustrates Offset and Gain Error. [01]
Figure 2.2 Illustrates Offset and Gain Error
2.2.2 Differential Non-Linearity Error (DNL)
DNL error is defined as the difference between an actual step width and the ideal voltage of 1LSB (1
2
ref N
LSB=V ). For an ideal ADC, in which the differential
nonlinearity coincides with DNL = 0LSB, each analog step equals 1LSB and the transition voltages are spaced exactly 1LSB apart. A DNL error specification of less than or equal to 1LSB guarantees a monotonic transfer function with no missing codes.
DNL is specified after the static gain error has been removed. It is defined as follows:
( )
( 1 ,) ( ), 1 that the ADC is monotonic, which means that the digital output always increases or is kept constant as the input increases. [01] [02]2.2.3 Integral Non-Linearity Error (INL)
INL error is defined as the deviation of each transition voltage of each code from the ideal transition voltage. INL is the difference between the actual finite resolution characteristic and the ideal finite resolution characteristic. INL is also specified after the static gain error has been removed. It is defined as follows:
( )
( ), ( )1
t n actual t n ideal
V V
INL n
LSB
− ,
= . (2.4)
Figure 2.3 displays examples of DNL and INL errors for different codes. [01] [02]
Figure 2.3 Example of DNL and INL errors in a 3-bit ADC
2.2.4 Signal-to-Noise Ratio (SNR)
The signal-to-noise ratio (SNR) is the ratio of the signal power to noise power at
the ADC’s output. It is well known that the theoretical SNR for an N-bit ADC is given by
6.02 1.76
SNR= ⋅ +N dB. (2.5)
2.2.5 Spurious Free Dynamic Range (SFDR)
The spurious free dynamic range is defined as the ratio of rms amplitude of the fundamental (the maximum signal amplitude) to the rms value of the largest distortion component in a specified frequency range. SFDR is important because noise and harmonics restrict converters’ dynamic range.
2.2.6 Signal-to-Noise and Distortion Ratio (SNDR)
For sinusoidal input signals, the signal to noise and distortion ratio is defined as the ratio of the signal power (maximum amplitude of the signal component) to the noise and harmonic distortion power at the ADC’s output.
2.2.7 Effective Number of Bits (ENOB)
For actual ADCs, a specification often used in place of the SNR or SNDR is ENOB, which is a global indication of ADC accuracy at a specific input frequency and sampling rate. ENOB can be defined as follows:
1.76 6.02 ENOB SNDR−
= bits. (2.6)
2.3 Review of ADC Architectures
Analog-to-digital conversion can be separated into two distinct operations:
sampling and quantization. Sampling transforms a continuous time signal into a corresponding discrete time signal. Quantization converts the continuous amplitude distribution into a set of discrete levels, which can be expressed with digital codes.
Figure 2.4 illustrates the principle of A/D conversion.
Figure 2.4 Principle of A/D Conversion
Some A/D converter architectures, such as flash converter, can perform sampling and quantization simultaneously. In high performance ADCs, sampling and quantization are usually separated to make it possible to optimize the circuitry for both tasks without compromises. [02] [03]
2.3.1 Flash ADC
Flash ADC which is the fastest and one of the simplest ADC architecture is shown in Figure 2.5. It consists of 2N-1 comparators and performs 2N-1 level quantization.
The reference voltages of the comparators are generated by using a resistor ladder which is connected between the positive and the negative reference voltage: +Vref and –Vref respectively. The set of 2N-1 comparator outputs is often referred to as thermometer code and is converted to N-bit binary word with a logic circuit. The input signal of the flash ADC is directly connected to the inputs of the comparators thus the speed of the flash ADC is very fast and the speed is only limited by the speed of the comparators. Therefore the flash ADC is capable of high speed.
The drawback of the flash ADC is the fact that the number of the comparators grows exponentially with the number of bits. As the number of comparators increases the chip area and power consumption will also increase. Therefore the flash ADC is not suitable for high resolution application; typical resolutions are seven bits or below.
Another drawback of the flash ADC is that the converter is sensitivity to comparator offset however the offset voltage can be solved by using auto-zeroing comparators.
Figure 2.5 N-bit Flash ADC
2.3.2 Two-Step ADC (or Subranging ADC)
One way to reduce the number of comparators in flash ADC is to perform the quantization in two steps [04]. Therefore, the number of comparators can be reduced form 2N-1 to 2×2N/2. The block diagram of this two-step converter is shown in Figure 2.6. The operation of this converter is described as follows. The fine flash ADC determines the most significant bits then these bits are converted back to an analog signal through the DAC to be subtracted from the input signal. This residual signal is then sent to the coarse flash ADC to determine the least significant bits.
The two-step converter has a longer latency delay than the flash converter but it can allow for higher resolutions than the flash converter because of reducing the number of comparators.
Figure 2.6 Two-step ADC
2.3.3 Pipelined ADC
The block diagram of the pipelined ADC is shown in Figure 2.7. It consists of a cascade of M identical stages in which each stage produce k bits and the last pipelined stage is followed by a flash ADC providing p bits. As a result, the final resolution N is M×k+p.
Figure 2.7 m-bit/stage pipelined ADC
A function block diagram of one stage is shown in the inset of Figure 2.7. The incoming voltage is sampled by the S/H circuit and simultaneously digitized by the sub-ADC. The output signals of the sub-ADC are then converted back to analog forms and will be subtracted form the output signals of the S/H circuit. The resulting residue voltage is amplified by 2k. The S/H circuit, the D/A converter, the subtraction, and the amplification are all performed by a single circuit block which called multiplying analog-to-digital converter (MDAC). The MDAC circuit consists of an opamp and a set of switched capacitors. The sub-ADC is usually performed in fresh architecture and consists of a few comparators and logic gates.
When the input signal is a rapidly-changing signal, the relative timing of the first stage S/H circuit and the sub-ADC is critical but it can be relaxed with a front-end circuit. If the input signal is not a rapidly-changing signal a front-end S/H circuit is not needed, since the pipelined stage already contains an S/H circuit. [05]
2.3.4 Cyclic ADC
A cyclic ADC consisted of a single pipeline stage with the output fed back to the input is shown in Figure 2.8. The operation of a cyclic ADC is the same as a pipelined ADC except that one stage does all the processing. The cyclic ADC completes N bits by reusing the stage multiple times thus it uses very little chip area and dissipates very low power. [06]
Figure 2.8 Cyclic ADC
2.3.5 Time-Interleaved ADC
Figure 2.9 shows the block diagram of an architecture in which four ADCs are used on parallel to achieve four times the sampling rate of a single converter. This method is often known as time-interleaved architecture [07]. The sample-and-hold circuits consecutively sample and apply the input analog signal to their respective ADCs. The digital outputs of the channels are combined with a multiplexer to a single bit-stream. [02]
Figure 2.9 Four-channel time-interleaved ADC and its clock signals
2.4 Digital Error Correction Technique
In the pipelined ADC, the input signal range is the same with the output signal range for each stage. This is done by the gain amplifier which amplifies the residue subtracted from the input signal. The amplified residue must still within the conversion range for the next stage. If there is a deviation such as the amplified residue exceeds the conversion range of the next stage, it may have wrong codes. As illustrated in Figure 2.10, the gain error and comparator offset may lead to over conversion range problems. Digital error correction is the name of the calibration technique that reduces the gain error, keeps the conversion range constant with modified coding and tolerates greater comparator offset.
For example, in a 2-bit pipelined stage there is only a contribution of less than two bits to final output word of the A/D converter and the residue amplification gain used is usually smaller than 4. This will keep the residue within certain boundaries and therefore the extra redundancy can be used to correct in the digital domain the referred non-ideal effects in the Flash Quantizers. Figure 2.11 shows the modified coding transfer curve with digital error correction.
(a) Gain error (b) Comparator offset Figure 2.10 Residue amplification characteristic of a 2-bit/stage with
(a) Gain error (b) Comparator offset
Figure 2.11 Analog residue with digital error correction
In the digital domain the correction is a simple addition, as illustrated in Figure 2.12. On the left is shown how the bits of the final result are obtained by summing the output bits of the stages with one-bit overlap. On the right the same bits are rearranged to show how the correction can be performed with a single adder. [05] [08]
Figure 2.12 RSD correction in digital domain
2.5 1.5-Bit / Stage Architecture
The pipelined ADC uses a pipelined 1.5-bit/stage architecture with 9 stages as shown in Figure 2.13. Each stage resolves 2 bits with a sub-ADC, and subtracts this value form its input and amplifies the resulting residue by a gain of two. The input signal range of the pipelined ADC is from –Vref to +Vref. In the 1.5-bit/stage, we set the threshold voltages of the sub-ADC at –Vref/4 and +Vref/4, therefore the residue transfer function is given as follows
( )
where D is the binary output code for each stage. The transfer function of 1.5-bit/stage is shown in Figure 2.11. Because of using the digital error correction technology, the 1.5-bit/stage has lower (2 instead of 4) inter-stage gain than the 2-bit/stage, but it requires more stages (9 stages instead of 5 stages for 10bits ADC) than the 2-bit/stage.
By reducing the inter-stage gain, the accuracy requirements on the sub-ADCs are
greatly reduced. In this research, a maximum offset voltage of Vref/4 can be tolerated before the bit errors occur.
Figure 2.13 Pipelined ADC with 1.5-bit/stage architecture
The number of bits per stage has a serious impact on the power, speed, and accuracy requirements of each stage. Therefore, the best choice of bit/stage is decided on the overall ADC specifications. For example, for fewer numbers of bits per stage, the comparator requirement is more relaxed, and the inherent speed of each stage is faster. The higher speed gain is because the inter-stage gain is lower allowing higher speed due to the fundamental gain bandwidth tradeoff of amplifiers. If fewer bits per stage are used, more stages are required. Therefore, the noise and gain errors of the later stages would make more inaccuracy to the overall converter because of the low inter-stage gain. Thus, low speed, high resolution specifications tend to favor higher number of bits per stage, where high speed, low resolution specifications favor a lower number of bits per stage.
This 1.5-bit/stage architecture has been shown to be effective in achieving high throughput at low power consumption. The low number of bits per stage combined with digital error correction technology relaxes the limits on the comparator offset voltage and DC gain of op-amp. [08]
2.6 Timing Analysis of The Pipelined ADC
The operation of the pipelined ADC is best understood with a timing diagram.
Figure 2.14 illustrates the timing of the pipelined ADC. The 1.5-bit sub-ADC in each stage is composed of two comparators and performs comparison to get digital output of A/D converter, and then the digital outputs of the 1.5-bit sub-ADC are delivered into registers to store. The register number in stage 1 is 9 and decreases in turn in the following stages. The register array is shown in Figure 2.15.
Figure 2.14 Timing diagram of the pipelined ADC
Stage 1
Register Register Register Register Register Register Register Register Register
Register Register Register Register Register Register Register Register
Register Register Register Register Register Register Register
Register Register Register Register Register Register
Register Register Register Register Register
Figure 2.15 Register array of the pipelined ADC
In Figure 2.15, ø1 and ø2 are two non-overlapping signals, and by passing register array, digital outputs from 9 stages can enter digital error correction block concurrently. The ten registers after digital error correction block make 10 digital outputs come out at the same time.
Chapter 3
Design of Pipelined Analog-to-Digital Converter
3.1 Introduction
Traditional designs of high-speed CMOS analog-to-digital converters have used flash architectures. While flash architectures usually yield the highest throughput rate, they trend to require large silicon area because of the large numbers of comparators required. An important purpose is that the realization of high-speed ADC in smaller area than that required in flash converters so that the A/D interface function can be integrated on the same chip with associated image-processing functions. Multistage conversion architectures reduce the area by reducing the number of comparators.
Using a pipelined architecture allows the stages to operate concurrently and produces the maximum throughput rate. Also, digital error correction technology significantly reduces the sensitivity of the architecture to certain component non-idealities.
The pipelined ADC architecture has been adopted into many high-speed applications such as high-performance digital communication systems and high-quality video systems. The rapid growth in these applications is driven the design of ADCs toward higher sampling rate, lower power consumption, and smaller chip area. The continued scaling of submicron CMOS technology couples with lower power supply voltage. This trend gives a challenge to conventional pipelined ADC designs which rely on high-gain and large-bandwidth operational amplifiers (op-amp)
to produce high-accuracy and high-speed data converters. At low power supply voltage, large open-loop operational amplifier gain is difficult to realize without sacrificing bandwidth or power consumption. As a result, the finite operational amplifier gain is becoming a major problem in achieving both high speed and high accuracy. One way to get a high op-amp gain is usually realized by multistage op-amp structure, gain-boosting technique, and long channel devices.
3.2 Operational Amplifier
Speed and accuracy are two of the most important properties of analog circuits, however optimizing circuits for both aspects lead to contradictory demands. In a wide variety of CMOS analog circuits such as switched-capacitor (SC) circuits, sample-and-hold amplifiers, and pipelined ADC, speed and accuracy are determined by the settling behavior of operational amplifiers. Fast settling requires a high unity-gain frequency, whereas accurate settling requires a high dc gain.
The realization of a CMOS operational amplifier that combines high dc gain with high unity-gain frequency has been a difficult problem. The high-gain requirement leads to multistage designs with long-channel devices, whereas the high unity-gain frequency requirement needs a single-stage design with short-channel devices. One way to overcome this problem is using the cascoding technique. Cascoding technique can enhance the dc gain of an op-amp without degrading the high frequency performance. The dc gain of the op-amp is proportional to the square of the intrinsic MOS transistor gain gm×ro.
The op-amp used in this pipelined ADC is made in the fully-differential
architecture. The advantages of the fully-differential circuit are that it can reduce even-order harmonic distortion, substrate noise, and common-mode disturbances. It also improves the power supply rejection ratio (PSRR) and the common-mode rejection ratio (CMRR). One drawback in the fully-differential circuit is that it needs the common-mode feedback circuit and it will be illustrated in the following sections.
3.2.1 Folded Cascode Operational Amplifier
The op-amp is the most important element in every stage of the pipelined ADC. If we increase the frequency bandwidth of the op-amp, the converting speed of the pipelined ADC can be increased. However, if we increase the dc gain of the op-amp, the resolutions of the pipelined ADC can be increased. In this project, the operational
The op-amp is the most important element in every stage of the pipelined ADC. If we increase the frequency bandwidth of the op-amp, the converting speed of the pipelined ADC can be increased. However, if we increase the dc gain of the op-amp, the resolutions of the pipelined ADC can be increased. In this project, the operational