Chapter 4 Test Setup and Experimental Results
4.3 The Package and Pin Configuration
Figure 4.8 shows the die photomicrograph of the experimental pipelined ADC and Figure 4.9 shows the photograph of the testing DUT board. Figure 4.10 presents the pin configuration and lists the pin assignments of the experimental pipelined ADC.
Figure 4.8 Die photomicrograph of the pipelined ADC
Figure 4.9 The photograph of the experimental pipelined ADC DUT board
Pin Name I/O Describe 7 CLOCK In System clock input 8 DGND In Digital ground 9 DVDD In Digital power supply 10 AGND In Analog ground 11 NC - No connection 12 AVDD In Analog power supply 13 REFP In Reference voltage＞Vcm 27 AGND In Analog ground 28 Vbb4 In Bias voltage 35 AVDD In Analog power supply 36 NC - No connection
Figure 4.10 (a) Pin configuration diagram and (b) Pin assignment
4.4 Experiment Results of Pipelined ADC
The pipelined ADC has fabricated in 0.18µm CMOS process. The chip was powered by the 1.8 V analog and digital circuits supply. A 1 MHz sine wave is applied to the ADC and operates at the 65 Msample/s conversion rate. The output 10-bit streams of the DUT collected by the logic analyzer and the plot chart are shown in Figure 4.11.
(a) Output bit streams
(b) Plot chart
Figure 4.11 Measured results
From the measured results shown in Figure 4.11, the signal to noise ratio is calculated by collecting 16384 samples of the input signal and performing a 16384 point fast Fourier transform shown in Figure 4.12. This result shows that SNR is about 37.2 dB, and the SNDR is about 31.8 dB due to severe harmonic distortions.
The SFDR shown in Figure 4.12 is about 38.1 dB.
Figure 4.12 16384 points FFT at 1MHz input frequency and 65 MHz sampling frequency
These harmonic distortions are caused by the nonlinear of the op-amp and mismatch of the output pairs. The worst reason is that the DC gain of the op-amp at the highest output swing is no longer large enough to meet the required specification.
Furthermore, the charge injection and common mode drift issues both are the possible reasons. In addition, when the sampling rate is large than 65 Msample/s, the plot chart of the ADC doesn’t show the similar sine-wave. Probably the input signal and the sampling rate are coupled each other, thus the input signal is influenced and doesn’t like sine-wave anymore. Figure 4.13 shows the SNDR for different sampling rate.
Table 4.1 summaries the measured results of the pipelined ADC.
0
Figure 4.13 The SNDR against the sampling rate
Table 4.1 Summary of measured results of the pipelined ADC
Parameters Measured Results
Process TSMC 0.18µm CMOS Mixed-Signal
Supply Voltage 1.8 V
Input Range ±0.6V Fully differential Operation Frequency 65 MHz
SNR for a 1 MHz input 37.2 dB SNDR for a 1 MHz input 31.8 dB SFDR for a 1 MHz input 38.1 dB
ENOB 5 bits
Power Dissipation 79 mW Chip Size 1.388mm×1.392mm
Chapter 5
Design of Low-Power CMOS Bandgap Reference Circuit
5.1 Introduction
In most analog integrated circuits, bandgap reference voltage generators become the indispensable circuits in operation amplifiers, digital-to-analog converters, and analog-to-digital converters. The reason bandgap reference circuit becomes so important is that it can generate the stable reference voltage which is insensitive to the variation of the temperature and the supply voltage. With the growth of wireless communication systems and portable devices, low-power consumption and low supply voltage operation have become a popular research.
Recently, research on generating a low-power and low supply voltage reference circuit was based on discussing the properties of MOSFETs operated in the weak inversion. In the traditional bandgap reference, the BJTs can be replaced by the MOSFETs which operated in the weak inversion and these MOSFETs can generate the current which has direct proportion to temperature. With the MOSFETs operated in the weak inversion, the reference circuit consumes less current and further reduces the power consumption. The proposed bandgap reference circuit will be illustrated in the next section.
5.2 Bandgap Reference Circuit Configuration
The proposed bandgap reference circuit is shown in Figure 5.1. The elements M1 and M2 connect in a current mirror and serve for realizing the function of self-biasing.
The MOSFETs M3 and M4 are designed to operate in the weak inversion such that the low-power reference circuit can be achieved. The current mirror of M1 and M2 is designed to make the drain currents of M3 and M4 operate in the weak inversion, then the voltage across R1 is proportional to the absolute temperature (PTAT). Hence, the resistor ratio R2/R1 can be used to compensate for the variation of the gate-source voltage of M4 with respect to the temperature. The detail circuit analysis will be illustrated in the next section. [18] [19] [20]
Figure 5.1 Schematic diagram of bandgap reference circuit
5.3 Bandgap Reference Circuit Analysis
For an n-MOSFET operate in the weak inversion region, its drain current is similar to the current of BJTs and it can be given as follows:
I =D texp GS
= q the thermal voltage, n and C are the constant, and satisfied VDS ≥3VT.
Using equation (5.2) and assuming that the ratio of K1 and K2 is unity which meant that the currents go through M3 and M4 are equal, we can obtain
4 3 ln
( )
GS GS T
V −V =nV N . (5.3) From figure 5.1, we can get a relationship between two gate-source voltages of M3 and M4 and it is given by:
4 3 3
GS GS D
V =V +I R1. (5.4) Substitute equation (5.3) into equation (5.4), we obtain
( )
Equation (5.5) shows that the drain current of M3 is PTAT.
The gate voltage VS of M3 and M4 is given as:
4 2 3
S GS D
V =V + I R2. (5.6)
For an n-MOSFET with a PTAT drain current, the voltage VGS4 with respect to the temperature can be given by
4 0 1 2 ln
VGS =A +AT+A T T , (5.7) where A0, A1 and A2 are the constants and dependent on the process technology.
Substitute equation (5.5) and equation (5.7) into equation (5.6), thus the voltage VS
can be expressed as designed to make the temperature coefficient of VS equal to zero at a selected temperature. Therefore the final output reference voltage Vref can be expressed as
3 Figure 5.2 shows the schematic diagram of bandgap reference and startup circuit.
The startup circuit is composed of several transistors including Ms1, Ms2 and Ms3, where Ms1 and Ms2 form a CMOS inverter. If the circuit is in the undesired zero-current state, the gate-source voltage VS of M4 would be less than a threshold voltage. As a result, Ms1 is turned off and Ms2 operates in the triode region, pulling the gate-source voltage of Ms3 up to Vdd. Therefore Ms3 is turned on and pulls down the voltages on the gates of M1 and M2, and this action causes current to flow in M1 and M2 to avoid the zero-current state.
When the circuit is in the steady state, the voltage of VS is designed to be in the high voltage for the inverter to turn on Ms1. Therefore the gate-source voltage of Ms3 pulls down and Ms3 would be turned off to avoid the current of core circuit flowing into Ms3. Since the startup circuit should not interfere with normal operation of the reference circuit in the steady state, the inverter output should fall low enough to turn Ms3 off in steady state. Therefore this startup circuit can solve the problem of the degeneration and make sure this reference circuit could work normally in the steady state. [20] [21] [22]
Figure 5.2 Schematic diagrams of Bandgap reference and Startup circuit
5.4 Simulation Results
The simulation results of the low-power CMOS bandgap reference will be shown as follows. Figure 5.3 shows the simulation result of the reference voltage Vref against supply voltage at the 60℃. When the supply voltage is larger than 1.5V, the stability of the reference circuit does not have a lot influence.
Figure 5.3 Reference voltage against supply voltage
Figure 5.4 shows the simulation result of reference voltage Vref against temperature T at various supply voltages. Table 5.1 shows the temperature coefficient of reference voltage Vref against temperature T at various supply voltages.
Figure 5.4 Reference voltage against temperature at various supply voltages
Table 5.1 Temperature coefficient of different supply voltages Supply voltage Reference voltage Temperature coefficient
1.5V 601mV 37.8 ppm/℃(2.28mV)
1.8V 605mV 38.4 ppm/℃(2.33mV)
3V 612mV 40.3 ppm/℃(2.47mV)
Figure 5.5 shows the simulation result of the reference voltage against temperature at 1.8V supply voltage of five process corners (TT, FF, FS, SF, SS). Table 5.2 shows the temperature coefficient of reference voltage Vref against temperature T at five process corners.
Figure 5.5 Reference voltages against temperature at five process corners
Table 5.2 Temperature coefficient of different process corners Process Corner Reference voltage Temperature coefficient
TT 605mV 38.4ppm/℃(2.33mV)
FF 575 mV 39.7ppm/℃(2.28mV)
FS 583mV 40.4ppm/℃(2.35mV)
SF 633mV 41.2ppm/℃(2.60mV)
SS 635mV 39.8ppm/℃(2.54mV)
Table 5.3 summaries the simulation results of the low-power CMOS bandgap reference. Layout and floor plan of the experimental prototype chip are shown in Figure 5.6. This low-power CMOS bandgap reference circuit was laid out on a 0.400×0.490mm2 die that including the pad frame.
Table 5.3 Summary of the simulated results of the CMOS bandgap reference
Parameters Simulated Results
Process TSMC 0.18µm CMOS Mixed-Signal
Supply Voltage 1.5V
(a) Layout
(b) Floor plan
Figure 5.6 Layout and floor plan of the CMOS bandgap reference
5.5 Conclusion
A low-power reference circuit with MOSFETs operated in the weak inversion region is described. The reference output voltage is around 600 mV, and the minimum supply voltage is 1.5V. This circuit is easy to design, and suitable for use in low-voltage, low-power applications.
Chapter 6
Conclusions
6.1 Conclusion
Among many types of CMOS ADC architectures, the pipelined ADC is the most popular approach for high speed and medium accuracy. This popularity is due to the fact that pipelined ADC can achieve high sampling rate as flash ADCs as a result of an S/H circuit in each stage of the pipeline. Also, the pipelined ADC require less silicon area, dissipate less power, and the voltages of the comparators in the sub-converter need to resolve are less stringent than the flash equivalents. In this research, the 10-bit、80 MS/s pipelined ADC has been designed and simulated by the program of Hspice using the standard tsmc 0.18µm CMOS process.
The thesis also has designed the low-power CMOS bandgap reference using the tsmc 0.18µm CMOS process. The bandgap reference uses the MOSFETs operated in the weak inversion to generate the proportional to absolute temperature current instead of using BJTs in CMOS process. Thus the power and silicon are could be reduced. The simulated results show that the temperature coefficient is 37.8ppm/℃
(2.28mV) when the output voltage is 600.8mV at supply voltage of 1.5V.
6.2 Future Work
In order to achieve the higher performance of the pipelined ADC, designing an op-amp with both larger signal swing and larger bandwidth for high dynamic range
and high speed respectively will be a challenging. If we continue to research on the same topic, we will try to use the correlated double-sampling architecture to get the higher operating speed. Also, using correlated double-sampling architecture could reduce gain errors and gain sensitivities. In the other hand, low voltage low-power circuit is the popular research for the future work. Thus scaling down the supply voltage without degrading the performance of the op-amp will be a difficult challenging. Thus, the design of high speed and high resolution of ultra low voltage pipelined ADCs will be the most important area for the future work.
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