Chapter 4 Electrical characteristics of Al/Ti/HfO 2 /Si MIS
4.3 Electrical characteristics for HfO 2 with dual plasma treatment for
There are three kinds of plasma treatment with different source gas (i.e. CF4, N2, NH3) and they were treated for different process time (i.e.
10 sec, 20sec, 30sec, 40sec, and 120sec).
4.3.1 Electrical characteristics for HfO2 with N2 plasma
36
treatment 120 sec and CF4 plasma treatment for different process time
Fig. 4-30 reveals the capacitance-voltage (C-V) characteristics of MIS capacitor treated in CF4 for different time and N2 plasma at optimal condition. The capacitor treated in CF4 for 10 sec and N2 for 120 sec shows the maximum capacitance density among these samples with different process times. In addition, other samples which treated in CF4
plasma and N2 plasma all present the larger values than the capacitors without whole plasma process. This phenomenon indicates that dual plasma treatment was workable to improve the capacitance. The factor of improvement might be from that the fluorine and nitrogen can repair defect and dangling bonds.
The J-V characteristics of MIS capacitor treated in CF4 for different time and N2 plasma at optimal condition from 0V to -2V are described in Fig. 4-31. The gate leakage current density treated N2 plasma 120 sec shows the minimum current density among these conditions. The lower leakage shows that the weak structure of interface must be fixed by the plasma nitridaiton. However, there is a non-ideal result that the gate leakage current increased for the sample with CF4 plasma treated longer than 10 sec. The reason for this phenomenon may be plasma damage and resulting in higher leakage current.
The hysteresis of C-V characteristics are shown in Figs. 4-32, 4-33, 4-34, 4-35, and 4-36 for the samples without treatment, and with 30, 60, 90, 120, 150, and 180 sec N2 plasma treatment, respectively. The hysteresis phenomenon of the C-V curves can be observed for all samples,
37
which is caused by the existence of negative charges trapped in the dielectric defect states when the capacitors are stressed. The hysteresis characteristic could be improved by various plasma nitridation process.
It can be observed that the samples which treated in CF4 plasma and N2
plasma all present the smaller values than the leakage current density without whole plasma process. The hysteresis was a slightly reduced after dual plasma treatment because the nitrogen and fluorine incorporation in the HfO2 dielectrics and reduced the interface trap state, thus improving hysteresis. However, these hysteresis voltage are very close to each other and can be acceptable.
4.3.2 Electrical characteristics for HfO2 with NH3 plasma treatment 120 sec and CF4 plasma treatment for different process time
Fig. 4-37 reveals the capacitance-voltage (C-V) characteristics of MIS capacitor treated in CF4 for different time and NH3 plasma at optimal condition. The capacitor treated in CF4 for 10 sec and NH3 for 120 sec shows the maximum capacitance density among these samples with different process times. In addition, other samples which treated in CF4 plasma and NH3 plasma all present the larger values than the capacitors without whole plasma process. This phenomenon indicates that dual plasma treatment was workable to improve the capacitance. The factor of improvement might be from that the fluorine and nitrogen can repair defect and dangling bonds.
38
The J-V characteristics of MIS capacitor treated in CF4 for different times and N2 plasma at optimal condition from 0V to -2V are described in Fig. 4-38. The gate leakage current density treated NH3 plasma 120 sec shows the minimum current density among these conditions. The lower leakage shows that the weak structure of interface must be fixed by the plasma nitridaiton. However, there is a non-ideal result that the gate leakage current increased for the sample with CF4 plasma treated longer than 10 sec. The reason for this phenomenon may be plasma damage and resulting in higher leakage current.
The hysteresis of C-V characteristics are shown in Figs. 4-39, 4-40, 4-41, 4-42, and 4-43 for the samples without treatment, and with 30, 60, 90, 120, 150, and 180 sec NH3 plasma treatment respectively. The hysteresis phenomenon of the C-V curves can be observed for all samples, which is caused by the existence of negative charges trapped in the dielectric defect states when the capacitors are stressed. The hysteresis characteristic could be improved by various plasma nitridation process.
It can be observed that the samples which treated in CF4 plasma and NH3
plasma all present the smaller values than the leakage current density without whole plasma process. The hysteresis was a slightly reduced after dual plasma treatment because the nitrogen and fluorine incorporation in the HfO2 dielectrics and reduced the interface trap state, thus improving hysteresis. However, these hysteresis voltage are very close to each other and can be acceptable.
39
4.3.3 Short summary
Fig. 4-44 shows the capacitance-voltage (C-V) characteristics of MIS capacitors combined CF4 plasma treatment with N2 or NH3 plasma treatment at optimal condition. It is indicated that the capacitance treated in CF4 plasma for 10 sec and NH3 plasma for 120 sec shows the most excellent value among these samples. In addition, these samples which treated in CF4 plasma and NH3 plasma all present the larger values than the capacitors without whole plasma process.
The J-V characteristics of MIS capacitors combined CF4 plasma treatment with N2 or NH3 plasma treatment at optimal condition in Fig.
4-45. It can be observed that the samples which treated in CF4 plasma and NH3 plasma all present the smaller leakage current density than the leakage current density without whole plasma nitridation process. The gate leakage current density treated in CF4 plasma 10 sec and N2 plasma 120 sec shows the minimum current density among these conditions.
Most of the plasma treatment samples can promote the electrical characteristics and reliability until the plasma damage or the growth of interfacial layer happened. Among these treatments, the samples that combined CF4 10 sec plasma treatment with N2 or NH3 plasma treatment represent significantly great improvement, such as good capacitance, reduced leakage current.
40
Chapter 5
Conclusions and future work 5.1 Conclusions
In thesis, characteristics of MIS capacitors that combine CF4 plasma treatment with N2 (or NH3) plasma treatment have been investigated.
These methods could be improved that the quality of HfO2thin film and Si/HfO2 interface. The plasma treatment conditions are N2 and NH3
plasma for 120 sec plus CF4 plasma for 10sec, 20sec, 30sec, and 40 sec respectively. Several important phenomena were observed and summarized as follows.
First, there are three kinds of plasma treatment with different source gas (i.e. N2, N2O, NH3) and they were treated for different process time (i.e. 30 sec, 60sec, 90sec, 120sec, 150sec, and 180sec). It observed that the samples with plasma nitridation all present the better values than the capacitors without whole plasma nitridation process. The reason for this phenomenon might the nitrogen incorporation be the method to reduce the leakage current, and it also can obtain larger capacitance after nitridation plasma. This phenomenon indicates that the plasma nitridation was workable to improve the capacitance and leakage current.
Second, the capacitors treated in CF4 plasma for different times before HfO2 film deposition. It observed that the samples with plasma fluorination all present the better values than the capacitors without whole plasma nitridation process. This phenomenon indicates that the CF4 plasma treatment was workable to improve the capacitance and leakage
41
current. The factor of improvement that fluorinated HfO2 gate dielectrics show thinner effective oxide thickness, smaller C-V- hysteresis, low leakage current density, good distribution of electrical performance, and less charge trapping.
Third, the experiment expects to obtain the advantages that combined plasma fluorination with plasma nitridation. The method that combined plasma fluorination with plasma nitridation calls dual plasma treatment. It observed that the samples with dual plasma treatment all present the better values than the capacitors without whole plasma process.
In summary, the MIS capacitor treated in CF4 plasma for 10 sec and N2 (or NH3) plasma for 120 sec was the optimal condition. It improved the HfO2 film and Si/HfO2 interface quality, result in thinner effective oxide thickness, smaller C-V hysteresis, low gate leakage current density, less charge trapping, and good distribution of electrical performance.
Thus, the improvement on electrical charateristics of HfO2 MIS capacitor with dual plasma treatment is more efficiency than single plasma treatment.
5.2 Future work
1. The mechanism of leakage current :
We might have to understand the mechanism of leakage current of thin film and thick film individually. The mechanism of the generation of the defects in the high-k bulk or interface still needs to be solved.
42
2. Material Analysis :
We can use some material analysis methods such as TEM, SIMS, AFM to know the thin film composition precisely and verify the phenomenon observed from C-V and J-V curve, SILC, CVS etc.
3. Devices fabrication with the above results :
The optimum condition will be used to manufacture MOS or TFT device in the future.
43
Reference
[1] E. P. Gusev, H.-C. Lu, E. L. Garfunkel, T. Gustafsson, M. L. Green.
[2] Suehle, J. S.; Vogel, E. M.; Edelstein, M. D.; Richter, C. A.; Nguyen, N. V.; Levin,I.; Kaiser, D. L.; Wu, H.; Bernstein, J. B., ―Challenges of high-k gate dielectrics for future MOS devices‖, Plasma- and
Process-Induced Damage, 2001 6th International Symposium on , 200.
[3] Max Schulz, ―The end of the road for silicon,‖ Nature, Vol. 399, pp.
729, 1999.
[4] Simon M. Sze, ―Physics of Semiconductor Device, 2nd Edition‖.
[5] The National Technology Roadmap for Semiconductors, Semiconductor Industry Association, San Jose, CA, 1997.
[6] P. Balk, ―Dielectrics for Field Effect Technology,‖ Adv. Mater. 7, 703 (1995).
[7] T. Hori, Gate Dielectrics and MOS ULSI, Springer, Berlin, 1997.
[8] L. Feldman, E. P. Gusev, and E. Garfunkel, ―Ultrathin Dielectrics in Si Microelectronics—An Overview,‖ Fundamental Aspects of Ultrathin Dielectrics on Si-based Devices, E. Garfunkel, E. P. Gusev, and A. Y. Vul’, Eds., Kluwer Academic Publishers, Dordrecht, Netherlands,1998.
[9] B. K. Park, J. Park, M. Cho, C. S. Hwang, K. Oh, Y. Han and D. Y.
Yang: Appl. Phys. Lett. 80 (2002) 2368.
[10] S. W. Huang and J. G. Hwu, ―Lateral nonuniformity of effective oxide charges in MOS capacitors with Al2O3 gate dielectrics,‖ IEEE trans. Electron Devices, vol. 53, no. 7, pp. 1608-1614, Jul 2006.
44
[11] C. S. Lai, W. C. Wu, J. C. Wang and T. S. Chao: Appl. Phys. Lett.
86 (2005) 22905.
[12] L. A. Ragnarsson, V. S. Chang, H. Y. Yu, H. J. Cho, T. Conard, K.
M. Yin, A. Delabie, J. Swerts, T. Schram, S. D. Gendt, and S.
Biesemans, ―Achieving conduction band-edge effective work functions by La2O3 capping of hafnium silicates,‖ IEEE Electron Device Lett., vol. 28, no. 6, pp. 486–488, Jun. 2007.
[13] Z. Ren, M. V. Fischetti, E. P. Gusev, E. A. Cartier, and M. Chudzik,
―Inversion channel mobility in high- high performance MOSFETs,‖
in IEDM Tech. Dig., 2003, pp. 33.2.1–33.2.4.
[14] G. D. Wilk, R. M. Wallace, et. al., ―High-k gate dielectrics: current status and materials properties consideration‖ J. Appl. Phys., Vol. 89, No. 10, pp. 5243,2001.
[15] M. Cassé, L. Thevenod, B. Guillaumot, L. Tosti, F. Martin, J. Mitard, O. Weber, F. Andrieu, T. Ernst, G. Reimbold, T. Billon, M. Mouis, and F. Boulanger, ―Carrier transport in HfO2/metal gate MOSFETs:
Physical insight into critical parameters,‖ IEEE Trans. Electron Devices, vol. 53, no. 4, pp. 759–768, Apr. 2006.
[16] Robert M. Wallace, IRPS Tutorial, IRPS, 2004 .
[17] K. J. Hubbard and D. G. Schlom, J. Mater. Res. 11, 2757(1996).
[18] Baohong Cheng, Min Cao, Ramgopal Rao, Anand Inani, Paul Vande Voorde Wayne M. Greene, Johannes M. C. Stork, Zhiping Yu, Peter M. Zeitzoff, Jason C. S. Woo, ―The Impact of High-k Gate Dielectrics and Metal Gate Electrodes on Sub-100nm MOSFETs‖, IEEE
45
Transactions on Electron Devices, Vol. 46, No. 7, July 1999.
[19] C. T. Liu, ―Circuit Requirement and Integration Challenges of Thin Gate Dielectrics for Ultra Small MOSFETs‖ in IEDM Tech. Dig., p747, 1998 .
[20] S. P. Muraka and C. C. Chang, Appl. Phys. Lett. 37,639 (1980).
[21] M. Balog, M. Schieber,M. Michman, and S. Patai, ―Chemical vapor deposition and characterization of HfO2 films from organo-hafnium compounds,‖ Thin Solid Films, vol. 41, pp. 247–259, 1977.
[22] J. Robertson, ―Band offsets of wide-band-gap oxides and implications for future electronic devices,‖ J. Vac. Sci. Technol. B, vol. 18, pp. 1785–1791, 2000.
[23] K. J. Hubbard and D. G. Schlom, ―Thermodynamic stability of binary oxides in contact with silicon,‖ J. Mat. Res., vol. 11, pp.
2757–2776, 1996.
[24] J. Roberson, J. Vac. Sci. Technol. B 18, pp1785, 2000 .
[25] K. J. Hubbard and D. G. Schlom, ―Thermodynamic stability of binary oxides in contact with silicon,‖ J. Mat. Res., vol. 11, pp.
2757–2776, 1996.
[26] K. Onishi, C. S. Kang, R. Choi, H.-J. Cho, S. Gopalan, R. Nieh, S.
Krishnan, and J. C. Lee, ―Effects of high-temperature forming gas anneal on HfO2 MOSFET performance,‖ in VLSI Tech. Dig, pp.
22–23, 2002.
[27] A. I. Kingon, J. P. Maria, and S. K. Streiffer, ―Alternative dielectrics to silicon dioxide for memory and logic devices,‖ Nature, vol. 406, no.
6799, pp. 1032–1038, 2000.
46
[28] K. J. Hubbard and D. G. Schlom, ―Thermodynamic stability of binary oxides in contact with silicon,‖ J. Mater. Res., vol. 11, no. 11, pp. 2757–2776, 1996.
[29] M. Balog, M. Schieber,M. Michman, and S. Patai, ―Chemical vapor deposition and characterization of HfO films from organo-hafnium compounds,‖ Thin Solid Films, vol. 41, pp. 247–259, 1977.
[30] S. Pidin, Y. Sugita, T. Aoyama, K. Irino, T. Nakamura and T. Sugii : Symp. VLSI Tech. Dig., 2002, p28.
[31] S. Zafar, A. Callegari, E. Gusev and M. V. Fischetti: J. Appl. Phy 93 (2003) 9298 .
[32] L.Pantisano , E.Cartier ― Dynamics of Threshold Voltage Instability in Stacked High-k Dielectrics: Role of the interfacial Oxide‖, VLSI, 2003 .
[33] E. P. Gusev , C, D’Emic, S. Zafar, A. Kumar ―Charge trapping and detrapping in HfO2 high-k gate stacks‖.
[35] Christopher C. Hobbs, Leonardo R. C. Fonseca, ―Fermi-Level Pinning at the Polysilicon/Metal Oxide Interface-Part1‖ , IEEE Electron Device Letters , VOL. 51, NO. 6 June 2004 .
[36] G.D. Wilk, R.M. Wallace, J.M. Anthony, J. Appl. Phys. 89 (2001) 5243.
[37] E.P. Gusev, D.A. Buchanan, E. Cartier, et al., IEDM Tech. Digest (2001) 451.
[38] Chao Sung LAI_, Woei Cherng WU1, Kung Ming FAN, Jer Chyi WANG2 and Shian Jyh LIN2 ,‖ Effects of Post CF4 Plasma Treatment on the HfO2 Thin Film‖.
47
[39] R. J. Carter, E. Cartier, M. Caymax, S. De Gendt, R. Degraeve, G.
Groeseneken, M. Heynes, T. Kauerauf, A. Kerber, S. Kubicek, G.
Lujan, L. Pantisano, W. Tsai, and E. Young, ―Electrical characterization of high-k materials prepared by atomic layer CVD,‖
in Proc. Extended Abstracts IEEE IWGI, 2001, pp. 94–99.
[40] Woei Cherng Wu, Chao-Sung Lai, Tzu-Ming Wang, Jer-Chyi Wang, Chih Wei Hsu, Ming Wen Ma, Wen-Cheng Lo, and Tien Sheng Chao
―Carrier Transportation Mechanism of the TaN/HfO2/IL/Si Structure With Silicon Surface Fluorine Implantation‖, Senior Member, IEEE.
[41] S. M. Sze, Physics of Semiconductor Devices. New York: Wiley, 1981, p. 403.
[42] H.-H Tseng,Y. Jeon, P. Abramowitz, T.-Y. Luo, ―Ultra-Thin Decoupled Plasma Nitridation (DPN) Oxynitride Gate Dielectric for 80-nm Advanced Technology ―, IEEE Electron Device Letters, VOL.
23, NO. 12, December, 2002.
[43] Seiji Inumiya, Katauyuki Sekine, Shoko Niwa, Akio Kaneko, Motoyuki Sato,‖ Fabrication of HFSION Gate Dielectrics by Plasma Oxidation and Nitridation, Optimized for 65 nm node Low Power CMOS Applications ‖, VLSI, 2003.
[44] Satoshi Kamiyama, Tomonori,‖ Improvement in the uniformity and the thermal stability of Hf-silicate gate dielectric by plasma-nitridation‖, IWGI, 2003.
48
[45] Katsuyuki Sekine, Seiji Inumiya, Motoyuki Sato, Yoshitaka Tsunashima, ―Nitrogen Profile Control by Plasma Nitridation Technique for Poly-Si Gate HfSiON CMOSFET with Excellent interface property and Ultra-low Leakage Current‖, IEDM 03-103.
[46] J. C. Lee, H. J. Cho, C. S. Kang, S. Rhee, Y. H. Kim, R. Choi, C. Y.
Kang, C. Choi, and M. Abkar, ―High- dielectrics and MOSFET characteristics,‖ in IEDM Tech. Dig., 2003, pp. 4.4.1–4.4.4 .
[47] H.-H. Tseng, P. J. Tobin, E. A. Hebert, S. Kalpat, M. E. Ramon, . Fonseca, Z. X. Jiang, J. K. Schaeffer, R. I. Hedge, D. H. Triyso, . C.
Capasso, O. Adetutu, D. Sing, J. Conner, E. Luckowski, B.W. Chan, . Haggag, S. Backer, R. Noble, M. Jahanbani, Y. H. Chiu, and B. E.
hite, ―Defect passivation with fluorine in a TaxCy/high- gate stack for nhanced device threshold voltage stability and performance,‖ in IEDM ech. Dig., 2005, pp. 696–699.
[48] M. Inoue, S. Tsujikawa, M. Mizutani, K. Nomura, T. Hayashi, K.
Shiga, . Yugami, J. Tsuchimoto, Y. Ohno, and M. Yoneda, ―Fluorine incorporation nto HfSiON dielectric for Vth control and its impact n reliability for Poly-Si Gate pFET,‖ in IEDM Tech. Dig., 2005, p.
413–416.
[49] Y. Nishioka, K. Ohyu, Y. Ohji, N. Natuaki, K. Mukai, and T. P. Ma, IEEE Electron Device Lett. 10, 141 ~1989.
[50] L. Vishnubhotla, T. P. Ma, H.-H. Tseng, and P. J. Tobin, Appl. Phys.
Lett. 59, 3595 ~1991.
[51] D. Humbird and D. B. Graves, ―Improved interatomic potentials for silicon-fluorine and silicon-chlorine,‖ J. Chem. Phys., vol. 120, no. 5,
49
pp. 2405–2412, Feb. 2004.
[52] C. Hu, S. C. Tam, F. C. Hsu, P.-K. Ko, T. Y. Chan, and K.W. Terrill,
―Hotelectron-induced MOSFET degradation—Model, monitor, and improvement,‖ IEEE Trans. Electron Devices, vol. ED-32, no. 2, pp.
375–385, Feb. 1985.
[53] Katsuyuki Sekine, Seiji Inumiya, Motoyuki Sato, Yoshitaka Tsunashima, ―Nitrogen Profile Control by Plasma Nitridation Technique for Poly-Si Gate HfSiON CMOSFET with Excellent interface property and Ultra-low Leakage Current‖, IEDM 03-103.
[54] R. J. Carter, E. Cartier, M. Caymax, S. De Gendt, R. Degraeve, G.
Groeseneken, M.Heyns, T. Kauerauf, A. Kerber, S. Kubicek, G. Lujan, L. Pantisano, W. Tsai, E. Young, ―Electrical Characterisation of High-K Materials Prepared by Atomic Layer CVD‖, IWGI 2001, Tokyo.
[55] Benjamin Chih-ming Lai, Nan-hui Kung, and Joseph Ya-min Lee, ―A study on the capacitance--voltage characteristics of metal-Ta2O5-silicon capacitors for very large scale integration metal-oxide-semiconductor gate oxide applications‖, J. Appl. Phys.
85, 4087 1999.
[56] Wai Shing Lau, Merinnage Tamara Chandima Perera, Premila Babu, Aik Keong Ow, Taejoon Han, Nathan P. Sandler, Chih Hang Tung, Tan Tsu Sheng and Paul K. Chu, ―The Superiority of N2O Plasma Annealing over O2 Plasma Annealing for Amorphous Tantalum Pentoxide (Ta2O5) Films‖, Jpn. J. Appl. Phys. Vol.37 pp.L435-L437 1998 .
50
[57] Y. Chuo, D. Y. Shu, L. S. Lee, W. Y. Hsieh, M. –J. Tsai, A. Wang, S.
B. Hung, P. J. Tzeng, Y. W. Chou, ―In-Line Inspection on Thickness of Sputtered HfO2 and Hf Metal Ultra-Thin Films by Spectroscopic Ellipsometry‖, 2004 IEEE.
[58] D. K. Schroder, ―Semiconductor material and device characterization,‖ John wiley & Sons, pp. 337-338, 1998.
51
Figure Captions
Fig. 1-1 Illustration of Moore’s law: number of transistors integrated in the different generations of Intel’s microprocessors vs. the production year of these circuits.
Fig. 1-2 Transistor physical gate length will reach ~ 15nm before end of this decade and ~ 10nm early next decade.
52
Fig. 1-3 With the marching of technology nodes, gate dielectric has to be shrunk and five silicon atoms thick of gate dielectric is predicted for 2012[3].
Fig. 1-4 Conduction mechanism in oxide for the MOS structure.
53
Fig. 1-5 Measured and simulated Ig-Vg characteristics under inversion condition for nMOSFETs . The dotted line indicates the 1A/cm2 limit for the leakage current [9].
Fig. 1-6 Power consumption and gate leakage current density comparing to the potential reduction in leakage current by an alternative dielectric exhibiting the same equivalent oxide thickness.
54
Fig. 1-7 Static dielectric constant vs. band gap for candidate gate oxides, after Robertson [8].
55
Fig.1-8 Inner-interface trapping model of hafnium dielectrics for (a) sweeping from inversion (Vg = 0 V) and (b) sweeping from accumulation (Vg = -3.0V) [41].
56
Fig. 2-1 The PECVD system that was used in the experiment.
Fig. 2-2 The E-gun system that was used in this experiment.
57
Fig. 2-3 (1) Si substrate RCA clean (2) Plasma fluorination treatment (3) Annealing by RTA
Fig. 2-4 (1) 4nm HfO2 was deposited on the sub-Si by MOCVD (2) PDA by RTA
58
Fig. 2-5 (1) Plasma nitridation treatment (2) PNA by RTA.
Fig. 2-6 20nm Ti was deposited on the HfO2 layer by E-gun evaporation system.
Fig. 2-7 400nm Al was deposited on the Ti layer as top electrode by E-gun evaporation system.
59
Fig. 2-8 Undefined Al was removed by wet etching.
Fig. 2-9 Undefined Ti was removed by wet etching (1%HF).
Fig. 2-10 Al was depodited on the back side of sub-Si as bottom electrode by E-gun evaporation system .
60 dielectrics treated in N2 phasma for different process time.
-3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0
plasma for different process time from 0V~-2V.
61
Fig. 4-3 The hysteresis of p-type HfO2 gate dielectrics without treatment.
-2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0
62
63
64 dielectrics treated in N2O phasma for different process time.
65 N2O plasma for different process time from 0V~-2V.
-2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0
66
Fig. 4-14 The hysteresis of p-type HfO2 gate dielectrics treated with N2O plasma treatment 90 sec.
67 plasma treatment 150 sec .
68 dielectrics treated in NH3 plasma for different process time.
69 NH3 plasma for different process time from 0V~-2V.
-2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0
Fig. 4-20 The hysteresis of p-type HfO2 gate dielectrics without treatment.
70
71
72 N2O plasma treatment at optimal condition.
73
Fig. 4-27 The J-V characteristics of p-type HfO2 capacitors treated in N2
plasma treatment, NH3 plasma treatment, and N2O plasma treatment at dielectrics treated in CF4 plasma for different process time.
74
Fig. 4-29 The J-V characteristics of p-type HfO2 capacitors treated in CF4
plasma treatment from 0V~-2V.
Fig. 4-30 The capacitance-voltage (C-V) characteristics of MIS capacitors treated in N2 plasma 120 sec and CF4 plasma for different process time.
75
Fig. 4-31 The J-V characteristics of MIS capacitors treated in N2 plasma 120 sec and CF4 plasma for different process time from 0V~-2V.
-2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0
Fig. 4-32 The hysteresis of MIS capacitors without treatment.
76
Fig. 4-33 The hysteresis of MIS capacitors treated in N2 plasma 120 sec CF4 plasma 10 sec.
Fig. 4-34 The hysteresis of MIS capacitors treated in N2 plasma 120 sec and CF4 plasma 20 sec.
77
Fig. 4-35 The hysteresis of MIS capacitors treated in N2 plasma 120 sec and CF4 plasma 30 sec.
Fig. 4-36 The hysteresis of MIS capacitors treated in N2 plasma 120 sec and CF4 plasma 40 sec.
78
Fig. 4-37 The capacitance-voltage (C-V) characteristics of MIS capacitors treated in NH3 plasma 120 sec and CF4 plasma for different
CF4 20W 10s+NH3 40W 120s CF4 20W 20s+NH3 40W 120s CF4 20W 30s+NH3 40W 120s CF4 20W 40s+NH3 40W 120s NH3 40W 120s
|J| (A/cm2 )
BIAS (V)
Fig. 4-38 The J-V characteristics of p-type MIS capacitors treated in N2
plasma 120 sec and CF4 plasma for different process time from 0V~-2V.
79
Fig. 4-39 The hysteresis of MIS capacitors without treatment.
-2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0
Fig. 4-40 The hysteresis of MIS capacitors treated in NH3 plasma 120 sec and CF4 plasma 10 sec.