Chapter 5 Conclusions and future work
5.2 Future work
1. The mechanism of leakage current :
We might have to understand the mechanism of leakage current of thin film and thick film individually. The mechanism of the generation of the defects in the high-k bulk or interface still needs to be solved.
42
2. Material Analysis :
We can use some material analysis methods such as TEM, SIMS, AFM to know the thin film composition precisely and verify the phenomenon observed from C-V and J-V curve, SILC, CVS etc.
3. Devices fabrication with the above results :
The optimum condition will be used to manufacture MOS or TFT device in the future.
43
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51
Figure Captions
Fig. 1-1 Illustration of Moore’s law: number of transistors integrated in the different generations of Intel’s microprocessors vs. the production year of these circuits.
Fig. 1-2 Transistor physical gate length will reach ~ 15nm before end of this decade and ~ 10nm early next decade.
52
Fig. 1-3 With the marching of technology nodes, gate dielectric has to be shrunk and five silicon atoms thick of gate dielectric is predicted for 2012[3].
Fig. 1-4 Conduction mechanism in oxide for the MOS structure.
53
Fig. 1-5 Measured and simulated Ig-Vg characteristics under inversion condition for nMOSFETs . The dotted line indicates the 1A/cm2 limit for the leakage current [9].
Fig. 1-6 Power consumption and gate leakage current density comparing to the potential reduction in leakage current by an alternative dielectric exhibiting the same equivalent oxide thickness.
54
Fig. 1-7 Static dielectric constant vs. band gap for candidate gate oxides, after Robertson [8].
55
Fig.1-8 Inner-interface trapping model of hafnium dielectrics for (a) sweeping from inversion (Vg = 0 V) and (b) sweeping from accumulation (Vg = -3.0V) [41].
56
Fig. 2-1 The PECVD system that was used in the experiment.
Fig. 2-2 The E-gun system that was used in this experiment.
57
Fig. 2-3 (1) Si substrate RCA clean (2) Plasma fluorination treatment (3) Annealing by RTA
Fig. 2-4 (1) 4nm HfO2 was deposited on the sub-Si by MOCVD (2) PDA by RTA
58
Fig. 2-5 (1) Plasma nitridation treatment (2) PNA by RTA.
Fig. 2-6 20nm Ti was deposited on the HfO2 layer by E-gun evaporation system.
Fig. 2-7 400nm Al was deposited on the Ti layer as top electrode by E-gun evaporation system.
59
Fig. 2-8 Undefined Al was removed by wet etching.
Fig. 2-9 Undefined Ti was removed by wet etching (1%HF).
Fig. 2-10 Al was depodited on the back side of sub-Si as bottom electrode by E-gun evaporation system .
60 dielectrics treated in N2 phasma for different process time.
-3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0
plasma for different process time from 0V~-2V.
61
Fig. 4-3 The hysteresis of p-type HfO2 gate dielectrics without treatment.
-2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0
62
63
64 dielectrics treated in N2O phasma for different process time.
65 N2O plasma for different process time from 0V~-2V.
-2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0
66
Fig. 4-14 The hysteresis of p-type HfO2 gate dielectrics treated with N2O plasma treatment 90 sec.
67 plasma treatment 150 sec .
68 dielectrics treated in NH3 plasma for different process time.
69 NH3 plasma for different process time from 0V~-2V.
-2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0
Fig. 4-20 The hysteresis of p-type HfO2 gate dielectrics without treatment.
70
71
72 N2O plasma treatment at optimal condition.
73
Fig. 4-27 The J-V characteristics of p-type HfO2 capacitors treated in N2
plasma treatment, NH3 plasma treatment, and N2O plasma treatment at dielectrics treated in CF4 plasma for different process time.
74
Fig. 4-29 The J-V characteristics of p-type HfO2 capacitors treated in CF4
plasma treatment from 0V~-2V.
Fig. 4-30 The capacitance-voltage (C-V) characteristics of MIS capacitors treated in N2 plasma 120 sec and CF4 plasma for different process time.
75
Fig. 4-31 The J-V characteristics of MIS capacitors treated in N2 plasma 120 sec and CF4 plasma for different process time from 0V~-2V.
-2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0
Fig. 4-32 The hysteresis of MIS capacitors without treatment.
76
Fig. 4-33 The hysteresis of MIS capacitors treated in N2 plasma 120 sec CF4 plasma 10 sec.
Fig. 4-34 The hysteresis of MIS capacitors treated in N2 plasma 120 sec and CF4 plasma 20 sec.
77
Fig. 4-35 The hysteresis of MIS capacitors treated in N2 plasma 120 sec and CF4 plasma 30 sec.
Fig. 4-36 The hysteresis of MIS capacitors treated in N2 plasma 120 sec and CF4 plasma 40 sec.
78
Fig. 4-37 The capacitance-voltage (C-V) characteristics of MIS capacitors treated in NH3 plasma 120 sec and CF4 plasma for different
CF4 20W 10s+NH3 40W 120s CF4 20W 20s+NH3 40W 120s CF4 20W 30s+NH3 40W 120s CF4 20W 40s+NH3 40W 120s NH3 40W 120s
|J| (A/cm2 )
BIAS (V)
Fig. 4-38 The J-V characteristics of p-type MIS capacitors treated in N2
plasma 120 sec and CF4 plasma for different process time from 0V~-2V.
79
Fig. 4-39 The hysteresis of MIS capacitors without treatment.
-2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0
Fig. 4-40 The hysteresis of MIS capacitors treated in NH3 plasma 120 sec and CF4 plasma 10 sec.
80
1.2x10-6 CF4 20W 20s+NH3 40W 120s
Forward Reverse
C (F/cm2 )
BIAS (V)
hysteresis = 21.23mV
Fig. 4-41 The hysteresis of MIS capacitors treated in NH3 plasma 120 sec and CF4 plasma 20 sec.
Fig. 4-42 The hysteresis of MIS capacitors treated in NH3 plasma 120 sec and CF4 plasma 30 sec.
81
Fig. 4-43 The hysteresis of MIS capacitors treated in NH3 plasma 120 sec and CF4 plasma 40 sec.
Fig. 4-44 The capacitance-voltage (C-V) characteristics of MIS capacitors combined CF4 plasma treatment with N2 or NH3 plasma treatment at optimal condition.
82
-3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 1E-8
1E-7 1E-6 1E-5 1E-4 1E-3 0.01 0.1 1 10
|J| (A/cm2 )
BIAS (V)
Fresh
CF4 20W 10s+N2 50W 120s CF4 20W 10s+NH3 40W 120s
Fig. 4-45 The J-V characteristics of MIS capacitors combined CF4 plasma treatment with N2 or NH3 plasma treatment at optimal condition from 0V~-2V.
83
Table
Reliability Difficult Challenges Difficult
Challenges
Summary of Issues
High-k Gate Dielectrics
1. Dielectric breakdown characteristics(hard and soft breakdown)
2. Influence of charge trapping and NBTI on thresholk voltage stability
3. Stability and number of fixed charges
Metal Gate 1. Impact of metal-ion drift and/or diffusion on gate dielectric reliability . 2. Work function control and stability
3. Metal susceptibility to oxidation
4. Thremo-mechanical issues due to large thermal expansion mismatch
5. Impact of omplantation
Copper/Low-k Interconnets
1. Stress migration of Cu vias and lines
2. Cu via and line electromigration performance
3. Thermal-mechanical stability of the interfaces between metals , barriers
and interlevel dielectrics and resulting line-to-line leakage
4. Time Dependent Dielectric Breakdown(TDDB) of the Cu/low-k SYSTEM
5. Reliability impact of lower thermal conductivity of low-k dielectric
6. Reliability issues due to the porous mature of the low-k dielectrics and
moisture
Table 1-1 Reliability difficult challenges. (ITRS : 2004 update)
84
Table 1-2 Basic characteristics of various high-k materials.
85
Table 2-1 Comparison of deposition techniques : PVD , ALCVD and MOCVD.