Chapter 3 How to Design Basic Switch
3.4 Asymmetric-LDD MOS transistor for RF Circuit Design
The rapid technology evolution of Si MOSFET is beneficial for IC design with higher device speed and cost reduction. However, the low drain breakdown voltage of CMOS transistors restricts the use of CMOS for power amplifiers. This limitation for high voltage operation significantly reduces the maximum output power and efficiency for CMOS devices.
To overcome the low breakdown voltage issue and improve the RF power performance, we use asymmetric-lightly-doped-drain (LDD) MOS transistor for high frequency RF power application.
This new asymmetric MOSFET is fully embedded in the conventional foundry logic process without any additional process step or extra cost. As technology evolution and down-scaling the Si MOSFET into sub-100 nm region, the performance of RF gain, cut-off frequency (ft), maximum oscillation frequency (fmax) and RF noise figure improve continuously but not the RF output power. This is originated from the lower source-drain breakdown voltage than that GaAs MESFET due to the smaller bandgap of 1.1eV than that of GaAs (1.42eV). The asymmetric-LDD MOS transistor that has higher drain breakdown voltage but also preserve high RF gain, ft and fmax for high frequency operation.
The structure comparison of (a) the new asymmetric-LDD MOS transistor and (b) conventional MOS transistor are shown schematically in Fig. 3.7. The LDD region at the drain size was removed that is the major difference to conventional MOS. This large
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improvement of breakdown voltage is due to the designed wide depletion region beneath the spacer region and between the drain and substrate. In contrast the existing n+-LDD in conventional CMOS transistor just provides an electrically short path between inversion channel and drain. Such wide depletion region in the new design can support significantly larger reverse-biased drain voltage than conventional case. Figure 3.8 shows the comparison of DC drain breakdown voltage for conventional and asymmetric-LDD MOS transistor. For conventional MOS, the breakdown voltage is 3.6V. In sharp contrast, the breakdown voltage of asymmetric-LDD MOS is increased to 7.0V. So we can use the asymmetric-LDD MOS in our switch design to improve power-handling capability. [12]
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(a)
(b)
Fig. 3.7 Device structure of (a) an asymmetric-LDD MOS transistor and (b) a conventional MOS transistor.
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0 1 2 3 4 5 6 7 8
0.00 0.02 0.04 0.06 0.08 0.10
Drain Current (µA/µm)
Drain Voltage (V)
C onven tional A sym m etric-LD D
Fig. 3.8 Comparison of drain breakdown voltage for conventional and asymmetric-LDD MOS transistor.
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Chapter 4
SPDT Circuit1 Design 4.1 Circuit1 Topology
Fig. 4.1 shows the circuit schematic. This circuit was designed with Agilent Advanced Design System (ADS), and implemented in TSMC’s 0.18µm RF CMOS technology. Due to the different requirements in the receive mode and the transmit mode, the SPDT switch is designed to be asymmetric. The T/R switch was designed by series-shunt topology using body-floating technique and asymmetric-LDD MOS transistor.
The devices of M1、M2、M3 are series transistors, and M4、M5、M6、M7 are shunt transistors which can improve the isolation of T/R switch. The signal is from ANT node to TX node or to RX node. Cbypass is on-chip bypass capacitor which is chosen to be as large as possible to provide ideal ac ground. It can isolate DC to avoid DC power consumption. The on-state transistor can be equivalent to a small resistor and the off-state transistor can be equivalent to a capacitor which is shown in Fig.4.2. The on-state and off-state of transistors are shown as Table 4.1. On-state transistor is biased at 1.8V and off-state transistor is biased at 0V. M4、M5、M6 use asymmetric-lightly-doped-drain (LDD) MOS which is our LAB developed MOS, see section 3-4. This large improvement of breakdown voltage is due to the designed wide depletion region beneath the spacer region and between the drain and substrate.
Asymmetric-LDD MOS transistor can endure high voltage. The key point is the large bias
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region on the transmitter path to improve the power linearity. Therefore, the higher drain breakdown voltage of asymmetric-LDD MOS transistor is used for the transmitter path. In this circuit, TX node is biased at 2.8V more than 1.8V in conventional MOS transistor. It can increase voltage swing, therefore improving the power-handling capability of T/R switch.
Besides, the shunt transistors M4、M5、M6 and the series transistors M2、M3 use the body-floating technique. The body-floating technique is to keep the parasitic diodes from being forward bias under large input signals, hence, improving the linearity and power-handling capability of CMOS T/R switch, introduced in section 3-3. M2、M3 utilize stacked transistor configuration to improve the power-handling capability. But it will also make the insertion loss increasing on the receive mode. Due to the trade-off between the power-handling capability and the insertion loss, the two stacked transistors are selected to approach the optimum.
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Transistor Mode TX on RX on
M1 On Off
M2 Off On
M3 Off On
M4 Off On
M5 Off On
M6 Off On
M7 On Off
Table 4.1 The state of transistor on the circuit.
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Fig. 4.1 The complete circuit schematic of the chip.
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G
S D
R C
On-state Off-state
Fig 4.2 Simplified models for on-state and off-state transistor.
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4.2 Simulation and Measurement Result
The RF performance of the UWB CMOS T/R switch has been measured by using network analyzer and on-wafer probing system. The other path is terminated with 50ohm when on-state and off-state characteristics are measured for one path. The control voltage is 1.8V for on-state and 0V for off-state.
4.2.1 TX Mode
The signal from antenna to transmit mode is TX mode. Figure 4.3 shows the simulated and measured isolation of the SPDT switch on TX mode. The red line is simulation and the blue line is measurement result. The measured isolation of SPDT switch achieves 31.4dB.
Figure4.4 shows the simulated and measured insertion loss on TX mode. The measured maximum insertion loss is 1.8dB. The return loss S11 and S22 on TX mode is small than -10dB, showed in Fig. 4.5 and Fig. 4.6. The power-handling capability achieves 28.7dBm, showed in Fig 4.7.
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Fig. 4.3 Simulated and measured isolation on the TX mode.
Fig. 4.4 Simulated and measured insertion loss on the TX mode.
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Fig. 4.5 Simulated and measured S11 on the TX mode.
Fig. 4.6 Simulated and measured S22 on the TX mode.
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Fig. 4.7 Measured power on the TX mode.
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4.2.2 RX Mode
The signal from antenna to receive mode is RX mode. Figure 4.8 shows the simulated and measured isolation of the SPDT switch on RX mode. The measured isolation of SPDT switch achieves 20.0dB. Figure4.9 shows the simulated and measured insertion loss on RX mode. The measured maximum insertion loss is 4.1dB. The return loss S11 and S22 on RX mode is small than -10dB, showed in Fig. 4.10 and Fig. 4.11. The die micrograph of the asymmetric T/R switch using 0.18um standard CMOS process is shown in Fig. 4.12. The chip size is 0.325mm2. The effective circuit area without pads is only 0.11mm2.
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Fig. 4.8 Simulated and measured isolation on the RX mode.
Fig. 4.9 Simulated and measured insertion loss on the RX mode.
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Fig. 4.10 Simulated and measured S11 on the RX mode
Fig. 4.11 Simulated and measured S22 on the RX mode.
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Fig. 4.12 The die photo.
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4.3 Summary
By the asymmetry series-shunt structure, an asymmetric-LDD MOS transistor, a body-floating technique, a high power-handling capability T/R switch is developed for UWB system application. Table 4.2 is the comparison of T/R switch performance. It shows highest power-handling capability by using asymmetric-LDD MOS transistor in this table. However, the disadvantage of this circuit is the higher insertion loss on RX mode. In the chapter5, the circuit2 has been redesigned to improve the insertion loss issue.
Reference Process Frequency
(GHz) Loss(dB) Isolation (dB) P1dB
(dBm) Technology Chip area (mm2)
Table 4.2 Comparison of T/R switch performance. *Effective chip area
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Chapter 5
SPDT Circuit2 Design 5.1 Circuit2 Topology
Fig. 5.1 shows the circuit2 schematic. The circuit2 was designed by series-shunt type using body-floating and asymmetric-LDD MOS technique. This work used four transistors.
The devices of M1、M2 are series transistors, and M3、M4 are shunt transistors which can improve the isolation of T/R switch. The signal is from ANT node to TX node or to RX node.
Cbypass is on-chip bypass capacitor to provide ideal ac ground. It can isolate DC to avoid DC power consumption. The on-state and off-state of transistors are shown as Table 5.1. The higher drain breakdown voltage of asymmetric-LDD MOS transistor M3 is used for the transmitter path. It can increase voltage swing, therefore improving the power-handling capability of T/R switch. Besides, the shunt transistor M3 uses the body-floating technique to improve power-handling capability. The body-floating technique was introduced in section 3-3.
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Transistor Mode TX on RX on
M1 On Off
M2 Off On
M3 Off On
M4 Off On
Table 5.1 The state of transistor on the circuit2.
Fig. 5.1 The complete circuit schematic of the chip2.
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5.2 Simulation Result
The signal from antenna to transmit mode is TX mode. Figure 5.2 shows the simulated the isolation of the SPDT switch on TX mode. The simulated isolation of SPDT switch achieves 26.2dB. Figure5.3 shows the simulated the insertion loss on TX mode. The simulated maximum insertion loss is 0.94dB. The return loss S11 and S22 on TX mode is small than -10dB, showed in Fig. 5.4. The power-handling capability achieves 30.1dBm, showed in Fig 5.5.
The signal from antenna to receive mode is RX mode. Figure 5.6 shows the simulated isolation of the SPDT switch on RX mode. The simulated isolation of circuit2 achieves 25.6dB. Figure5.7 shows the simulated insertion loss on RX mode. The measured maximum insertion loss is 1.29dB. The return loss S11 and S22 on RX mode is higher than -10dB, showed in Fig. 5.8. The layout diagram of the asymmetric T/R switch using 0.18um standard CMOS process is shown in Fig. 5.9. The chip size is 0.21mm2. The effective circuit area without pads is only 0.055mm2. Table 5.2 represents the simulated performance.
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Fig. 5.2 Simulated isolation on the TX mode.
0 4 8 12 16
Fig. 5.3 Simulated insertion loss on the TX mode.
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Fig. 5.4 Simulated input and output return loss on the TX mode.
Fig. 5.5 Simulated power-handling capability on the TX mode.
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Fig. 5.6 Simulated isolation on the RX mode.
0 4 8 12 16
Insertion loss=0.844 dB Frequency=10.6 GHz Insertion loss=1.291 dB
Fig. 5.7 Simulated insertion loss on the RX mode.
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Fig. 5.8 Simulated input and output return loss on the RX mode.
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Fig. 5.9 The layout diagram of circuit2.
TX“on”，RX“off” TX“off”，RX“on”
Insertion loss
(dB)
Isolation (dB)
P1dB
(dBm)
Insertion loss (dB)
Isolation (dB) Post-sim ＜0.944 ＞26.215 30.1 ＜1.291 ＞25.691
Table 5.2 The specification of circuit2.
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5.3 Summary
By the series-shunt structure, an asymmetric-LDD MOS transistor, a body-floating technique, a high power-handling capability T/R switch is developed for UWB system application. Table 5.3 is the comparison of T/R switch performance.
This work has highest power-handling capability in this table. This simulated result can prove that this circuit topology is useful for UWB system application.
Reference Process Frequency
(GHz) Loss(dB) Isolation (dB)
10~18 0.7-1.0 25-32 22.6-25.4 [16] 0.18um
RX＜1.291 RX＞25.691 30.1 Asymmetry
MOS 0.21/0.055*
Table 5.3 The comparison of T/R switch performance. *Effective chip area
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Chapter 6 Conclusion
A new fully integrated 0.18-um CMOS T/R power switch has been developed by asymmetric-LDD MOS transistor. By raising the drain operation voltage beyond conventional CMOS device, the RF power linearity of this new transistor is improved according to measurement and simulation results. Measurement result shows the highest P1dB compression point around 28.7dBm for UWB application .Moreover, this new asymmetric MOSFET is fully embedded in the conventional foundry logic process without any additional process step or extra cost. From the modified chip design simulation results, it shows low insertion loss and high-power handling capability. Therefore, asymmetric-LDD MOS transistor technique will be candidate in design T/R switch in the future.
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Vita
姓名：李佩諭 性別：女
出生年月日：民國71年3月30日 籍貫：台灣省新竹市
住址：新竹市明湖路980號之2 學歷：私立逢甲大學電機工程學系 (90年9月~94年6月)
國立交通大學微電子奈米科技產業研發碩士班 (95年2月入學)
論文題目：
非對稱性 LDD 金氧半元件之單刀雙擲開關應用於超寬頻 3.1~10.6GHz 之研究 (Asymmetric-LDD MOS of SPDT switch for Ultra wideband 3.1~10.6GHz)