Impedance Matching - Basic Concept in Switch Design

Chapter 2 Basic Concept in Switch Design

2.2 Impedance Matching

Consider the RF system shown in Figure 2.4. Here the source and load are 50Ω (a very popular impedance), as are the transmission lines leading up to the IC. For optimum power transfer, prevention of ringing and radiation, and good noise behavior, we need the circuit input and output impedances matched to the system. In general, some matching circuit must almost always be added to the circuit, as shown in Fig. 2.5. Figure 2.6 illustrates a typical situation in which a transistor, in order to deliver maximum power to 50Ω load, must have the terminations Zs and ZL. The input matching network is designed to transform the generator impedance (show as 50Ω) to the source impedance Zs, and the output matching network transforms the 50Ω termination to the load impedance ZL.

Fig. 2.4 Circuit embedded in a 50-Ω system.

Fig. 2.5 Circuit embedded in a 50-Ω system with matching circuit.

Fig.2.6 Circuit embedded in a 50-Ω system with matching circuit.

Typically, reactive matching circuits are used because they are lossless and because they do not add noise to the circuit. However, using reactive matching components means that the circuit will only be matched over a range of frequencies and not at others. If a broadband match is required, then other techniques may need to be used. An example of matching a transistor amplifier with a capacitive input is shown in Figure 2.7. The series inductance adds an impedance of jωL to cancel the input capacitive impedance. Note that, in general, when an impedance is complex (R+jX), then to match it, the impedance must be driven from its complex conjugate (R-jX).

A more general matching circuit is required if the real part is not 50Ω. For example, if the real part of Zin is less than 50Ω, then the circuit can be matched using the circuit in Figure 2.8.

Series components will move the impedance along a constant resistance circle on the Smith chart. Parallel components will move the admittance along a constant conductance circle on the Smith chart. The input impedance of a circuit can be any values. In order to have the best power transfer into the circuit, it is necessary to match this impedance to the impedance of the source driving the circuit. The output impedance must be similarly matched.

It is very common to use reactive components to achieve this impedance transformation, because they do not absorb any power or add noise. Thus, series or parallel inductance or capacitance can be added to the circuit to provide an impedance transformation.

With the proper choice of two reactive components, any impedance can be moved to a desired point on the Smith chart. There are eight possible two-component matching networks, also known as ell networks, as shown in Figure 2.9. Each will have a region in which a match is possible and a region in which a match is not possible.

In any particular region on the Smith chart, several matching circuits will work and others will not. This is illustrated in Figure 2.10, which shows what matching networks will work in which regions. Since more than one matching network will work in any given region, how does one choose? There are a number of popular reasons for choosing one over another.

1. Sometimes matching components can be used as dc blocks (capacitors) or to provide bias currents (inductors).

2. Some circuits may result in more reasonable component values.

3. Personal preference. Not to be underestimated, sometimes when all paths look equal, you just have to shoot from the hip and pick one.

4. Stability. Since transistor gain is higher at lower frequencies, there may be a low-frequency stability problem. In such a case, sometimes a high-pass network (series capacitor, parallel inductor) at the input may be more stable.

5. Harmonic filtering can be done with a lowpass matching network (series inductor, parallel capacitor). This may be important, for example, for power amplifiers. [2]

Fig.2.7 Example of a very simple matching network.

Fig.2.8 A possible impedance matching network.

Fig.2.9 The eight possible impedance-matching networks with two reactive components.

Fig. 2.10 Which ell matching networks will work in which regions.

Chapter 3 How to Design Basic Switch 3.1 Introduction

In recent years, wireless communication systems have undergone explosive growth that is largely unanticipated. In time-division duplexing (TDD) communication systems, transmit-receive (T/R) switch plays an important role to control the RF signal flow to transmitter (TX) or receiver (RX). In the receive mode, T/R switch will receive the signal from antenna. Because the switch is in front of the low noise amplifier, insertion loss will influence noise figure of receive path directly. In the transmit mode, T/R switch need to handle the great power signal from transmitter in order to avoid signal distortion.

Simultaneously, isolation can determine whether both signals may influence each other or not.

Therefore, the key parameters of single pole double throw (SPDT) switch are insertion loss, power-handling capability and isolation.

Silicon-based CMOS technology has fast become one of the most favorable processes for RFICs due to its low cost and highly integrative capacity. Owing to low mobility, high substrate conductivity, low breakdown voltage, and various parasitic parameters of CMOS processes, it has many challenges to design CMOS switches to achieve low insertion loss, high isolation, wide bandwidth, and high power-handling capability.

3.2 Basic Concept

Some basic circuits of switch will introduce in this chapter. Traditional typology of T/R switch is a series type, see Fig.3.1. The equivalent circuit model of an on-state transistor is a small resistor. For the off-state transistor, it is represented as a small capacitor. When operating frequency increases, equivalent impedance will become smaller, see eq.3.1.

Isolation will become worse between transmit and receive end.

C Z j

ω

= 1

（3.1）

There are many references to improve isolation of switch such as resonant with shunt inductor [5], series-shunt type [6], T-shaped R-C-R circuit [7]. When resonant type operates in the center frequency, inductor and“off-state＂transistor, which equivalent circuit is capacitor, become resonant circuit, see Fig3.2. This structure needs to use inductor as the same number as transistor. It will use large layout area to realize this circuit. Therefore, it is unsuitable to be realized.

Series–shunt type is shown in Fig.3.3, the function of shunt transistor is insert signal to ground. For this reason, it can improve isolation definitely. Therefore, this structure is used widely in designing T/R switch. When operating frequency increases, series-shunt type has the same problem with traditional series type. Signal loss on off-state path will become worse as frequency increasing.

To consider power-handling capability, series-shunt type is limited to characteristic of

shunt transistor. There are many ways to solve the power-handling capability issue. From the paper [8], it used stacked series transistors to share power, so power-handling capability can be improved.

The switch uses an LC-tuned substrate biasing technique to dramatically improve the power-handling capability [9]. The body of transistor is series a resonant circuit with capacitance shunt inductance, see Fig. 3.4. It can improve power-handling capability in the specific frequency range. On the other hand, it can be used only on narrow band.

Body-floating technique is body series a large resistor about 5kΩ, see Fig.3.5. It has the same operating mode with LC-tuned substrate biasing technique, but it can improve power-handling capability in a wide band. Besides, it can also decrease insertion loss for on-state switch [10][11].

A 15-GHz T/R switch is reported in [13], the impedance matching network was employed to improve the linearity, while the isolation performance is degraded. The linearity can also be improved by using differential architectures [17], 3-dB linearity improvement can be obtained.

Fig.3.1 The series type of switch.

Fig.3.2 The resonant type with transistor shunt inductance.

Fig. 3.3 The series-shunt type of switch.

Fig. 3.4 The resonant type of body-floating.

Fig. 3.5 The body series large resistor type

3.3 Body-Floating Technique

The goals of SPDT performance are low insertion loss, high isolation and high power-handling capability.To improve the insertion loss, the substrate resistance RB should be either extremely large or close to zero. However, it is impossible to make RB zero due to the parasitic effect. Therefore, it is important to let RB be large enough. By using body-floating technique can reduce the parasitic effect.

In order to improve the power-handling capability of the CMOS switch, it can use the body-floating technique [10]. The circuit schematic of a shunt transistor is shown as Fig.

3.6(a). For the off-state transistor, it is represented as a small capacitor. Body to source and body to drain can be equivalent to the two back-to-back parasitic diodes. The equivalent circuit model on off-state is shown in Fig. 3.6(b).

In general, body connect to source type, the high input power signal will turn on the diode between body and drain. The diode can be equivalent to a small resistor. A small resistor will cause the current from ground to drain increasing quickly. The high current will change the input impedance of the transistor, and degrade the power-handling capability as shown in Fig. 3.6(c).

The equivalent circuit model of the off-state transistor with the body-floating technique , is shown in Fig. 3.6(d). The body of the transistor is connected to ground with a large resistor by using body-floating technique. The high input power signal will still turn on the diode

between body and drain. The diode also can be equivalent to a small resistor. But the resistor between body and ground is very large, the current from ground to drain will increase smoothly. For this reason, power-handling capability can be improved by using body-floating technique.

(a) (b)

Fig.3.6. (a) Circuit schematic of shunt transistor, (b) the equivalent model in the off-state, (c) without body-floating technique, (d) with body-floating technique

3.4 Asymmetric-LDD MOS transistor for RF Circuit Design

The rapid technology evolution of Si MOSFET is beneficial for IC design with higher device speed and cost reduction. However, the low drain breakdown voltage of CMOS transistors restricts the use of CMOS for power amplifiers. This limitation for high voltage operation significantly reduces the maximum output power and efficiency for CMOS devices.

To overcome the low breakdown voltage issue and improve the RF power performance, we use asymmetric-lightly-doped-drain (LDD) MOS transistor for high frequency RF power application.

This new asymmetric MOSFET is fully embedded in the conventional foundry logic process without any additional process step or extra cost. As technology evolution and down-scaling the Si MOSFET into sub-100 nm region, the performance of RF gain, cut-off frequency (ft), maximum oscillation frequency (fmax) and RF noise figure improve continuously but not the RF output power. This is originated from the lower source-drain breakdown voltage than that GaAs MESFET due to the smaller bandgap of 1.1eV than that of GaAs (1.42eV). The asymmetric-LDD MOS transistor that has higher drain breakdown voltage but also preserve high RF gain, ft and fmax for high frequency operation.

The structure comparison of (a) the new asymmetric-LDD MOS transistor and (b) conventional MOS transistor are shown schematically in Fig. 3.7. The LDD region at the drain size was removed that is the major difference to conventional MOS. This large

improvement of breakdown voltage is due to the designed wide depletion region beneath the spacer region and between the drain and substrate. In contrast the existing n⁺-LDD in conventional CMOS transistor just provides an electrically short path between inversion channel and drain. Such wide depletion region in the new design can support significantly larger reverse-biased drain voltage than conventional case. Figure 3.8 shows the comparison of DC drain breakdown voltage for conventional and asymmetric-LDD MOS transistor. For conventional MOS, the breakdown voltage is 3.6V. In sharp contrast, the breakdown voltage of asymmetric-LDD MOS is increased to 7.0V. So we can use the asymmetric-LDD MOS in our switch design to improve power-handling capability. [12]

(a)

(b)

Fig. 3.7 Device structure of (a) an asymmetric-LDD MOS transistor and (b) a conventional MOS transistor.

0 1 2 3 4 5 6 7 8

0.00 0.02 0.04 0.06 0.08 0.10

Drain Current (µA/µm)

Drain Voltage (V)

C onven tional A sym m etric-LD D

Fig. 3.8 Comparison of drain breakdown voltage for conventional and asymmetric-LDD MOS transistor.

Chapter 4 SPDT Circuit1 Design 4.1 Circuit1 Topology

Fig. 4.1 shows the circuit schematic. This circuit was designed with Agilent Advanced Design System (ADS), and implemented in TSMC’s 0.18µm RF CMOS technology. Due to the different requirements in the receive mode and the transmit mode, the SPDT switch is designed to be asymmetric. The T/R switch was designed by series-shunt topology using body-floating technique and asymmetric-LDD MOS transistor.

The devices of M1、M2、M3 are series transistors, and M4、M5、M6、M7 are shunt transistors which can improve the isolation of T/R switch. The signal is from ANT node to TX node or to RX node. Cbypass is on-chip bypass capacitor which is chosen to be as large as possible to provide ideal ac ground. It can isolate DC to avoid DC power consumption. The on-state transistor can be equivalent to a small resistor and the off-state transistor can be equivalent to a capacitor which is shown in Fig.4.2. The on-state and off-state of transistors are shown as Table 4.1. On-state transistor is biased at 1.8V and off-state transistor is biased at 0V. M4、M5、M6 use asymmetric-lightly-doped-drain (LDD) MOS which is our LAB developed MOS, see section 3-4. This large improvement of breakdown voltage is due to the designed wide depletion region beneath the spacer region and between the drain and substrate.

Asymmetric-LDD MOS transistor can endure high voltage. The key point is the large bias

region on the transmitter path to improve the power linearity. Therefore, the higher drain breakdown voltage of asymmetric-LDD MOS transistor is used for the transmitter path. In this circuit, TX node is biased at 2.8V more than 1.8V in conventional MOS transistor. It can increase voltage swing, therefore improving the power-handling capability of T/R switch.

Besides, the shunt transistors M4、M5、M6 and the series transistors M2、M3 use the body-floating technique. The body-floating technique is to keep the parasitic diodes from being forward bias under large input signals, hence, improving the linearity and power-handling capability of CMOS T/R switch, introduced in section 3-3. M2、M3 utilize stacked transistor configuration to improve the power-handling capability. But it will also make the insertion loss increasing on the receive mode. Due to the trade-off between the power-handling capability and the insertion loss, the two stacked transistors are selected to approach the optimum.

Transistor Mode TX on RX on

M1 On Off

M2 Off On

M3 Off On

M4 Off On

M5 Off On

M6 Off On

M7 On Off

Table 4.1 The state of transistor on the circuit.

Fig. 4.1 The complete circuit schematic of the chip.

G

S D

R C

On-state Off-state

Fig 4.2 Simplified models for on-state and off-state transistor.

4.2 Simulation and Measurement Result

The RF performance of the UWB CMOS T/R switch has been measured by using network analyzer and on-wafer probing system. The other path is terminated with 50ohm when on-state and off-state characteristics are measured for one path. The control voltage is 1.8V for on-state and 0V for off-state.

4.2.1 TX Mode

The signal from antenna to transmit mode is TX mode. Figure 4.3 shows the simulated and measured isolation of the SPDT switch on TX mode. The red line is simulation and the blue line is measurement result. The measured isolation of SPDT switch achieves 31.4dB.

Figure4.4 shows the simulated and measured insertion loss on TX mode. The measured maximum insertion loss is 1.8dB. The return loss S11 and S22 on TX mode is small than -10dB, showed in Fig. 4.5 and Fig. 4.6. The power-handling capability achieves 28.7dBm, showed in Fig 4.7.

Fig. 4.3 Simulated and measured isolation on the TX mode.

Fig. 4.4 Simulated and measured insertion loss on the TX mode.

Fig. 4.5 Simulated and measured S11 on the TX mode.

Fig. 4.6 Simulated and measured S22 on the TX mode.

Fig. 4.7 Measured power on the TX mode.

4.2.2 RX Mode

The signal from antenna to receive mode is RX mode. Figure 4.8 shows the simulated and measured isolation of the SPDT switch on RX mode. The measured isolation of SPDT switch achieves 20.0dB. Figure4.9 shows the simulated and measured insertion loss on RX mode. The measured maximum insertion loss is 4.1dB. The return loss S11 and S22 on RX mode is small than -10dB, showed in Fig. 4.10 and Fig. 4.11. The die micrograph of the asymmetric T/R switch using 0.18um standard CMOS process is shown in Fig. 4.12. The chip size is 0.325mm². The effective circuit area without pads is only 0.11mm².

Fig. 4.8 Simulated and measured isolation on the RX mode.

Fig. 4.9 Simulated and measured insertion loss on the RX mode.

Fig. 4.10 Simulated and measured S11 on the RX mode

Fig. 4.11 Simulated and measured S22 on the RX mode.

Fig. 4.12 The die photo.

4.3 Summary

By the asymmetry series-shunt structure, an asymmetric-LDD MOS transistor, a body-floating technique, a high power-handling capability T/R switch is developed for UWB system application. Table 4.2 is the comparison of T/R switch performance. It shows highest power-handling capability by using asymmetric-LDD MOS transistor in this table. However, the disadvantage of this circuit is the higher insertion loss on RX mode. In the chapter5, the circuit2 has been redesigned to improve the insertion loss issue.

Reference Process Frequency

(GHz) Loss(dB) Isolation (dB) P1dB

(dBm) Technology Chip area (mm²)

Table 4.2 Comparison of T/R switch performance. *Effective chip area

Chapter 5 SPDT Circuit2 Design 5.1 Circuit2 Topology

Fig. 5.1 shows the circuit2 schematic. The circuit2 was designed by series-shunt type using body-floating and asymmetric-LDD MOS technique. This work used four transistors.

The devices of M1、M2 are series transistors, and M3、M4 are shunt transistors which can improve the isolation of T/R switch. The signal is from ANT node to TX node or to RX node.

Cbypass is on-chip bypass capacitor to provide ideal ac ground. It can isolate DC to avoid DC power consumption. The on-state and off-state of transistors are shown as Table 5.1. The higher drain breakdown voltage of asymmetric-LDD MOS transistor M3 is used for the transmitter path. It can increase voltage swing, therefore improving the power-handling capability of T/R switch. Besides, the shunt transistor M3 uses the body-floating technique to improve power-handling capability. The body-floating technique was introduced in section 3-3.

Transistor Mode TX on RX on

M1 On Off

M2 Off On

M3 Off On

M4 Off On

Table 5.1 The state of transistor on the circuit2.

Fig. 5.1 The complete circuit schematic of the chip2.

5.2 Simulation Result

The signal from antenna to transmit mode is TX mode. Figure 5.2 shows the simulated the isolation of the SPDT switch on TX mode. The simulated isolation of SPDT switch achieves 26.2dB. Figure5.3 shows the simulated the insertion loss on TX mode. The simulated maximum insertion loss is 0.94dB. The return loss S11 and S22 on TX mode is small than -10dB, showed in Fig. 5.4. The power-handling capability achieves 30.1dBm, showed in Fig 5.5.

The signal from antenna to receive mode is RX mode. Figure 5.6 shows the simulated isolation of the SPDT switch on RX mode. The simulated isolation of circuit2 achieves 25.6dB. Figure5.7 shows the simulated insertion loss on RX mode. The measured maximum insertion loss is 1.29dB. The return loss S11 and S22 on RX mode is higher than -10dB, showed in Fig. 5.8. The layout diagram of the asymmetric T/R switch using 0.18um standard CMOS process is shown in Fig. 5.9. The chip size is 0.21mm². The effective circuit area without pads

在文檔中非對稱性LDD金氧半元件之單刀雙擲開關應用於超寬頻3.1~10.6GHz之研究 (頁 24-0)