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Chapter 3 Fundamentals of Analog Front-End

3.2 Low-Offset and Low-noise Technique

3.2.1 Auto-zero technique

(a)

(b)

Fig. 3.2.1-1 Principle of Auto-zero technique (a) Phase 1, ϕ=1 (b) Phase 2, ϕ=0

The principle of auto-zero technique is depicted in Fig. 3.2.1-1 [15]. The offset cancellation is done in two phases. First, as shown in Fig. 3.2.1-1(a), when ϕ=1 (sampling phase), S1,2 is closed and S3 is open. The amplifier is configured in negative feedback structure, and the amplifier’s offset is stored on capacitor. The voltage over the auto-zero capacitor C can be expressed as:

Second, as shown in Fig. 3.2.1-1(b), during ϕ=0(signal phase), S1,2 is open and S3 is closed. The sampled offset is subtracted from the input signal and amplified. The output voltage can be expressed as:

-(3.5)

A channel charge of switch S2 will feed into the auto-zero capacitor. This effect is called charge injection. Therefore, the overall residual offset can be expressed as:

-(3.6)

Because input offset voltage can be divided by the voltage gain, the residual offset is then dominated by the charge injection. The influence of the charge injection caused by switch S2 on the residual offset can be reduced by increasing the size of the capacitor. In addition, the leakage of the capacitor C during the amplification phase can cause residual offset. These two effects cannot be divided by the voltage gain because the auto-zero capacitor is already at the input.

Besides the offset, the auto-zero technique can also minimize the flicker noise of the amplifier if the sampling frequency fs is chosen higher than the noise corner frequency fcorner, as shown in Fig. 3.2.1-2. However, auto-zero technique has the problem of noise-folded at the frequency lower than sampling frequency fs.

Intuitively, it can be assumed that when the amplifier depicted in Fig. 3.2.1-1 is auto-zeroed, the broadband noise of the amplifier is projected onto the capacitor C. At the end of the sampling phase the input offset and noise voltage are held on the

Chapter 3 Fundamentals of Analog Front-End

capacitor, which means that all components of noise above the auto-zeroing frequency will fold back due to aliasing. Fig. 3.2.1-2 shows that the noise at frequency lower than fs is about a•Vn,th, which is slightly higher than thermal noise.

Fig. 3.2.1-2 Noise spectrum of auto-zero technique

3.2.2 Chopper technique

In chopper amplifiers the signal of interest and the offset signal are shifted to different frequencies. In Fig. 3.2.2-1, a chopper amplifier is shown [14]. This amplifier consists of a frequency modulator (or chopper CH1), a voltage amplifier, another chopper CH2, and a low-pass filter (LPF). The chopper switch is driven by a square wave φ with a chopping frequency fc.

Fig. 3.2.2-1 Principle of Chopper technique and its operation in Frequency/Time domain

From Fig. 3.2.2-1, we can know the method of operation of chopper technique both in frequency and time domain. The input signal is modulated to the chopping frequency at first. After amplify by an operational amplifier, the signal will be modulated back to the baseband. The offset and flicker noise is modulated only once and appears at the chopping frequency and its odd harmonics. At last, these frequency components can be removed through a low-pass filter.

The effect of chopper modulation can be analyzed from Fig. 3.2.2-2. Where Vin

is the input signal and m(t) is the carrier signal taking values of +1 and -1 with frequency of chopping frequency fc. It can be realized by two pairs of switch and complementary square wave φ and φ .

Chapter 3 Fundamentals of Analog Front-End

Fig. 3.2.2-2 Chopper modulation

The input signal Vin is multiplied by the square wave modulation signal m(t).

After this modulation, the output signal Vout is transposed around the odd harmonic frequencies of the modulation signal and is given by the following Fourier series:

-(3.5)

with -(3.6)

Therefore,

-(3.7)

According to (3.7), we can note that chopper modulation will shift offset and noise to the odd harmonic frequencies.

When a low-pass filter is used after the chopper amplifier, the chopper ripple and low-frequency noise can be filtered. CMOS amplifiers usually have a high DC input offset voltage and flicker noise. To reduce the flicker noise, the chopper frequency

From Fig. 3.2.2-1, this analysis can be concluded that the chopper technique completely reduces the 1/f noise when the chopper frequency is higher than the corner frequency of the 1/f noise. In practice the noise level of a chopper amplifier is slightly higher than the thermal noise level. Fig. 3.2.2-3 shows the noise spectrum of chopper technique. In contrast to the auto-zero technique, we can observe that the baseband noise of chopper amplifier is almost equal to the wideband thermal noise. Thus chopper technique is adopted to suppress the dc offset and low frequency in this thesis.

Fig. 3.2.2-3 Noise spectrum of auto-chopper technique

Although chopper technique has better performance on noise suppression than auto-zero technique, it still has some non-ideal effect. The ideal and non-ideal waveforms are depicted in time domain in Fig. 3.2.2-4. The gray line shows the ideal waveform and the black line shows the actual waveform. The limited bandwidth of the amplifier is a fundamental cause of switching glitches, so the square wave at the output of amplifier would not be like a perfect square wave. Therefore after

Chapter 3 Fundamentals of Analog Front-End

demodulation the actual waveform would include part of the chopper ripple, just as Fig. 3.2.2-4(b) depicts.

Fig. 3.2.2-4 Ideal and non-ideal waveforms of chopper amplifier in time domain (a) Amplifier output (b) Demodulated amplifier output

Another non-ideal effect is the residual offset caused by charge injection, which is generated by chopper modulator. Fig. 3.2.2-5 shows the basic concept of charge injection.

Fig. 3.2.2-5 Basic concept of charge injection

The gate voltage changes from high to low, transitioning the switch from closed to open state. When the gate of the NMOS transistor is high and the transistor is on, the voltage on the voltage source is sampled on the capacitor. When the gate of the NMOS transistor is low and the transistor is off, the voltage on the capacitor should

from the MOS switch create an error in the sampled voltage. When the transistor turns off, channel charge is dispersed into the source and drain so that charge injection occurs. This effect will cause channel charge entering the source or drain and introduces an error voltage.

Fig. 3.2.2-6 Charge injection model of a chopper modulator

Fig. 3.2.2-7 Residual offset caused by spike (a) Spike signal (b) Demodulation signal (c) Demodulated spike

Chapter 3 Fundamentals of Analog Front-End

Fig.3.2.2-6 is the charge injection model of a chopper modulator, where RS is the input resistor. C1 and C2 are the parasitic capacitors [33]. The effect of the mismatch between C1and C2 will be analyzed. When both lines are loaded with identical capacitors, no residual offset will occur since it will be a common-mode spike.

However, if there is a slight mismatch between the two capacitors, a differential component will also appear at Vout, which will translate into a residual offset, because these spikes are actually demodulated by the input chopper towards the input.

This effect is illustrated in Fig. 3.2.2-7 [33]. Therefore, each time the chopper clock switches charge is being injected into the input, this differential charge can be expressed by:

qinj=(C1-C2)Vspike-(3.8)

Where Vspike is the spike voltage generated by chopper modulator. This charge is applied two times the per clock period. This means that a current will run through the resistor RS. So the residual offset can be expressed by:

VOS=2(RS)(C1-C2)Vspikefc -(3.9)

Where fc is the chopping frequency. Since the time constant of these parasitic spikes is generally much smaller than the half chopper period, most of the spike appears at frequencies higher than chopper frequencies [3].

Transmission gate can reduces charge injection effect. As Fig. 3.2.2-8 depict, since the charge carriers in the NMOS and PMOS have inversed polarity. The

Fig. 3.2.2-8 Reduce charge injection effect by using transmission gate

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