Differential difference amplifier with resistive feedback

Fig. 3.5.2-1 Schematic of the differential difference amplifier (DDA)

Fig. 3.5.2-1 shows schematic of the differential difference amplifier (DDA).

Since the current feedback instrumentation amplifier (CBIA) is a fully differential architecture, it requires common-mode feedback (CMFB) circuit, which means that CBIA needs extra power dissipation to realize CMFB circuit. Besides, CMFB circuit would limit the output swing of the CBIA because the output sees a voltage VGS from the input of CMFB circuit. For low supply voltage, a voltage drop of VGS severely decreases the output swing of the amplifier and reduces the resolution of the signal.

By implementing differential difference amplifier, the problems mentioned above can be solved.

Fig. 3.5.2-2 Differential difference amplifier with resistive feedback

Fig. 3.5.2-2 shows a differential difference amplifier with resistive feedback. The voltage gain of the circuit can be written as:

(

+ − −

)

⎟⎟⎠

⎞

⎜⎜⎝

⎛ +

= _{in in}

out V V

R V R

1

1 2 －(3.19)

The ratio of the two resistors defines the voltage gain of the amplifier. Compare with traditional three opamp instrumentation amplifier, it doesn’t need for resistor matching. More details about the circuit will be discussed in chapter 5.

Chapter 4 A CBIA with a PGA for ECG signal Detecting

Chapter 4

A Current Feedback IA with a

Programmable Gain Amplifier for ECG signal Detecting

4.1 Introduction

Some principles about current feedback instrumentation amplifier (CBIA) has introduced in Chapter 3. To realize a low-power and low-noise analog front-end for ECG signal detecting, we will introduce a complete system based on CBIA in this chapter. The circuit includes a pair of high pass filter (HPF) at the front, a CBIA incorporates with chopper technique and negative feedback resistors R1 and R2, a low pass filter, and a programmable gain amplifier. Furthermore, both simulation result and measurement result are provided in this chapter to show that the performance of

4.2 Circuits Architecture

Fig. 4.2-1 Architecture of the CBIA with PGA

Fig. 4.2-1 represents the architecture of the current feedback instrumentation amplifier with programmable gain amplifier [6]. The chopper technique is used in this circuit. In order to benefit from the advantages of the chopper modulation technique for biomedical application, AC coupling must be introduced to prevent the readout circuit saturation. As Fig. 4.2-2 shows, AC coupling acts like a high pass filter and provides the common mode voltage through a large resistor R to insure the input voltage of CBIA is operating at Vcm. Besides, high pass filter can lower the input offset voltage so that the bio-signals would not saturate after being amplified by CBIA.

Fig. 4.2-2 AC coupling circuit (HPF)

Chapter 4 A CBIA with a PGA for ECG signal Detecting

Fig. 4.2-3 Concept of the analog front-end with chopper technique

After AC coupling circuits, the bio-signal enters the analog front-end circuit. We can use Fig. 4.2-3 to analyze the signal and noise of the analog front-end with chopper technique [33]. The differential ECG signal is modulated by chopper switch (Chopper 1) and the modulated signal at the input pair can be written as:

－(4.1)

Where VN1 contributes the DC offset and flicker noise to the input pairs, and m(t) is the chopping signal taking values of +1 and -1 at the chopping frequency fc. Because of the operation of input chopper modulator, the input signal is modulated to odd harmonics of chopping frequency fc while the undesired component of VN1 resides at the baseband spectrum. After amplifying by CBIA, we obtain the equation below:

V_m1= V_in⋅ m(t) +V_N1

After the demodulator (Chopper 2), the signal of Vm2 is demodulated back to the baseband spectrum, and the undesired component VN1 is modulated to the odd harmonics of chopping frequency fc. Now we can obtain this equation:

－(4.3)

Therefore equation (4.4) can be modified like this:

－(4.5)

When the signal enters to the last stage of the programmable gain amplifier (PGA), having a gain of A2 and noise of VN2, Vout can be expressed as:

－(4.6)

According to equation (4.6), the analysis shows that the DC offset and flicker noise of input pairs are removed by using chopper technique. Moreover, in order to suppress the offset and flicker noise of VN2, the gain of A1Vin>> VN2 must be attained.

V_m3= m(t)[A₁⋅V_in⋅ m(t) + A₁⋅V_N1] = A₁⋅V_in⋅ m(t)⋅ m(t) + A₁⋅V_N1⋅ m(t)

V_m3= A₁⋅V_in⋅ m(t)⋅ m(t) + A₁⋅V_N1⋅ m(t) = A₁⋅V_in+ A₁⋅V_N1⋅ m(t)

V_{m 4}= A₁⋅V_in

V_out = A₂[A₁⋅V_in+V_{N 2}] = A₁A₂⋅V_in+ A₂⋅V_{N 2}

Chapter 4 A CBIA with a PGA for ECG signal Detecting

4.3 Circuits Implementation

In this section, we will introduce about the building blocks of the analog-front end system, including current feedback instrumentation amplifier (CBIA), common mode feedback circuit (CMFB), low pass filter (LPF), programmable gain amplifier (PGA), and clock generator.

4.3.1 Current feedback instrumentation amplifier (CBIA)

Fig. 4.3.1-1 Simplified schematic of CBIA

The main power-consuming block of the analog front-end is CBIA. Fig.4.3.1-1 shows the simplified schematic of the implemented CBIA structure [6]. It consists of

4 parallel branches and the need for opamp as in the case of traditional three-opamp instrumentation amplifier is eliminated. Thus, the power dissipation can be reduced.

The voltage gain of the CBIA can be calculated from the small signal half-circuit model. Fig. 4.3.1-2 depicts the small signal half-circuit of the simplified CBIA [6].

Fig. 4.3.1-2 Small signal half-circuit model of the simplified CBIA

Where gm1 is the transconductance value and ro1 is the output resistance of transistor M1. gm2 is the transconductance value and ro2 is the output resistance of transistor M2. Rout1, Rout2, and Rout3 are the output resistances of the current source I1, I2, I3, respectively.

Chapter 4 A CBIA with a PGA for ECG signal Detecting

Assuming that ro1 and ro2 are much larger than R1/2 and R2/2, the voltage gain of the CBIA structure can be derived as:

⎟⎟ defined by only two resistors. Therefore, there’s no need for the matched resistors.

Fig. 4.3.1-3 shows the complete schematic of CBIA [6]. The transistors ML5, ML6 and MR5, MR6 serve as a level shifter in order to maximize the input-output voltage swing of the CBIA. For the purpose of increase the CMRR value, we use cascade structure for current source I1. Besides, due to the fully differential structure of the CBIA, a CMFB circuit is implemented. The CMFB circuit of the CBIA will be introduced in the next section.

4.3.2 Common mode feedback circuit (CMFB)

Fig. 4.3.2-1 Concept of CMFB with resistive sensing

As we have mentioned CBIA in the last section, it is a fully differential structure and its output common mode voltage cannot be stabilized by means of differential feedback. It needs a common mode feedback circuit (CMFB) to control the common mode component of the output signal.

Chapter 4 A CBIA with a PGA for ECG signal Detecting

Fig. 4.3.2-1 shows the traditional concept of CMFB with resistive sensing. In differential amplifiers, the output common mode level is quite sensitive to the mismatch of the components [25]. Thus, a CMFB network must be added to sense the common mode level of the two outputs and accordingly adjust one of the bias currents in the amplifier. In order to sense the output common mode level, we can employ a resistive divider to serve as a common mode level detector, just as shown in Fig.

4.3.2-1. The common mode level voltage can be written as:

V_out,CM =(R₊V_out++ R₋V_out−)

However, R+ and R- must be much greater than the output impedance of the opamp to avoid reducing the open-loop gain. It is difficult for such large resistors to occupy the chip area. Moreover, the mismatch of the two resistors is also a big problem.

In order to avoid such problems mentioned above, a current based CMFB is adopted. Fig. 4.3.2-2 depicts the schematic of current based CMFB. In this case, one of the input terminals of both differential pairs is connected to reference voltage Vcm

and the outputs of the differential amplifier are connected to the other two input terminals of the pairs. A signal current is generated and gives rise to control voltage

as a common mode level detector. Besides, a resistor divider suffers from the poor linearity because of the mismatch problem. Improved linearity is achieved due to the differential structure and operation of the common mode level detector [25].

Fig. 4.3.2-2 Schematic of current based CMFB

4.3.3 Low pass filter (LPF) [4]

The main purpose of the low pass filter (LPF) is filtering the noise which is chopped to the chopping frequency fc in analog front-end. In order to reduce the effect of the noise, we implement second-order low pass filter in the analog front-end.

There are two topologies for second-order low pass filter. They are the Multiple Feedback topology and the Sallen-Key topology. The former topology is commonly used in filters that have high Qs and require a high gain. The latter is usually applied

Chapter 4 A CBIA with a PGA for ECG signal Detecting

in unity gain filter design. In this thesis, we adopt the Sallen-Key topology as our low pass filter. Fig. 4.3.3-1 shows the structure of unity gain Sallen-Key low pass filter

Fig. 4.3.3-1 Unity gain Sallen-Key low pass filter

The basic transfer function of the second-order low pass filter can be written as:

1 2

For the unity gain Sallen-Key low pass filter in Fig. 4.3.3-1, the transfer function can be written as:

The coefficient comparing between (4.12) and (4.13) yields:

⎪⎩

Given C1 and C2, the resistor values for R1 and R2 are calculated through:

 Butterworth Low-pass filter:

This filter provides maximum passband flatness. Therefore, it is usually used when the precise signal levels are required across the entire passband.

 Tschebyscheff Low-pass filter:

This filter has a steeper roll-off and more passband ripple than Butterworth filter.

It minimizes the error between the idealized and the actual filter characteristic, but with ripples in the passband.

 Bessel Low-pass filter:

The passband gain of a Bessel filter is not as flat as that of the Butterworth filter, and the transition from passband to stopband is by far not as sharp as that of a Tschebyscheff filter.

Chapter 4 A CBIA with a PGA for ECG signal Detecting

  57  

Comparison of gain responses of the three types low pass filter is shown in Fig.

4.3.3-2. For the reason that Butterworth filter has maximum passband and has a moderate slope of transition from passband to stopband, we choose Butterworth type to realize our low pass filter in this thesis.

Fig. 4.3.3-2 Comparison of gain responses of the three types low pass filter

Table 4.3.3-1 Second-order filter coefficients

Second-order Butterworth Tschebyscheff Bessel

a1 1.4142 1.065 1.3617

Figure 16–9. Comparison of Gain Responses of Fourth-Order Low-Pass Filters

16.2.4 Quality Factor Q

The quality factor Q is an equivalent design parameter to the filter order n. Instead of de-signing an n^th order Tschebyscheff low-pass, the problem can be expressed as designing a Tschebyscheff low-pass filter with a certain Q.

For band-pass filters, Q is defined as the ratio of the mid frequency, f_m, to the bandwidth at the two –3 dB points:

Q ! fm

(f₂" f₁)

For low-pass and high-pass filters, Q represents the pole quality and is defined as:

Q !

#

b_i a_i

High Qs can be graphically presented as the distance between the 0-dB line and the peak

Table 4.3.3-1 lists the coefficients of a second-order filter type. From this table we can find out that the a1 and b1 coefficients of Butterworth filter are 1.4142 and 1, respectively. Assuming C1 = 15pF, we can calculate equation (4.16):

C₂ ≥ C₁4b₁

a₁² = C₁⋅ 4 ⋅ 1

1.414² = 15⋅10⁻¹²pF ⋅ 2 = 30 pF －(4.17)

Inserting a1 and b1 into the resistor equation (4.15) results in:

R_1,2=

For ECG signal detecting, we know that the characteristic frequency of ECG signal is about 0.5Hz~250Hz. Therefore, it is reasonable to set 3-dB frequency at 500Hz in low pass filter. Inserting fc = 500 into equation (4.18) results in:

R_1,2 = 0.707

Fig. 4.3.3-3 Butterworth low pass filter

Chapter 4 A CBIA with a PGA for ECG signal Detecting

4.3.4 Programmable gain amplifier (PGA)

Fig. 4.3.4-1 Programmable gain amplifier

The programmable gain amplifier is depicted in Fig.4.3.4-1. The programmable gain amplifier includes a differential difference amplifier (DDA), a poly resistor string of R1-R4, and three transmission gate switches of SW1-SW3. The variable gain is obtained by poly resistor string of R1-R4 along with three transmission gate switches of SW1-SW3 and the gain setting is selected according to the digital controller. Based on the variable resistances controlled by the CMOS switches, programmable gain is defined as:

(

+ − −

)

Fig. 4.3.4-2 Differential difference operational transconductance amplifier

Fig. 4.3.4-2 is a differential difference operational transconductance amplifier [18]. By implementing the differential difference structure, the output signal of CBIA would not see the finite feedback resistor but the high input impedance stage so that the signal would not decay. The operational transconductance amplifier (OTA) is a device that converts an input voltage into an output current. It is primarily voltage-to-current amplifiers. The gm stage of the OTA can be written as:

I_out

V_in = (g_{m 4,5}+ g_m3,6)g_m16

g_m8 －(4.22)

The open-loop gain of the amplifier in Fig. 4.3.4-2 is:

V_out V_out =I_out

V_in ⋅V_out

I_out =(g_{m 4,5}+ g_m3,6)

g_m8 ⋅ g_m16⋅[(g_m15r_o15r_o16) / /(g_m14r_o14r_o13)] －(4.23)

Chapter 4 A CBIA with a PGA for ECG signal Detecting

Although the programmable gain can be defined by equation (4.20), there’s some intrinsic problems exist in the amplifier. To understand it, we can use the circuit depicted in Fig. 4.3.4-3 (a) and (b) to explain this problem.

Fig. 4.3.4-3 (a) Non-inverting amplifier (b) Non-inverting amplifier equivalent circuit

Fig. 4.3.4-3 (a) shows a non-inverting amplifier. We all know that the ideal closed-loop gain can be written as 1+(R2/R1). However, the amplifier is not that ideal in reality. Fig. 4.3.4-3 (b) shows the equivalent circuit of the non-inverting amplifier.

The non-zero resistor Rout and the infinite resistor Rin have non-ideal effect on circuit.

Writing a KCL equation at output node yields:

A_VV_d−V_out

Solving the equation (4.24) and (4.25), then we have:

V_out

V = A_V

A R + R －(4.26)

By multiplying

From equation (4.27), we can observe that if the non-inverting amplifier is an ideal amplifier, for Av =∞and Rout = 0. The ideal closed-loop gain can be written as 1+(R2/R1). Since the Rout term is not zero in (4.27), it severely affects the closed-loop gain of the amplifier. As we can see in Fig. 4.3.4-2, the output resistance Rout can be written as:

R_out = (g_m15r_o15r_o16) / /(g_m14r_o14r_o13) －(4.28)

Because the output impedance of the operational transconductance amplifier is high, the OTA must implement a buffer for driving resistive loads. To analyze the output resistance of the buffer, we can use Fig.4.3.4-4 to calculate the value of Rout.

Fig. 4.3.4-4 (a) Buffer (b) Small signal model of the buffer

Chapter 4 A CBIA with a PGA for ECG signal Detecting

As Fig. 4.3.4-3(b) illustrates, Rout can be expressed by:

⎟⎟⎠

In general, ro is big enough that we can simplify equation (4.29) and (4.30) into:

mp

Compare the Rout value in (4.28) to (4.31), with the implementation of the buffer we can reduce the output resistance to

gmp

2 . Therefore, the resistive feedback can be well

defined since Rout is small in equation (4.27). Fig. 4.3.4-5 shows the overall programmable gain amplifier that used differential difference operational transconductance amplifier with a buffer stage.

4.3.5 Clock generator [33]

Fig. 4.3.5-1 Problem of clock overlapping

Chopper modulator needs two clock signals that are 180 degree of phase difference. If we just add an inverter to generate another path to obtain φ and φ , φ may have time delay comparing with the φ and results in the problem of clock overlapping, just as Fig. 4.3.5-1 depicts. The problem of clock overlapping may cause chopper modulator malfunction. To prevent it, we use non-overlapping clock generator.

Fig. 4.3.5-2 Non-overlapping clock generator

Chapter 4 A CBIA with a PGA for ECG signal Detecting

Fig. 4.3.5-2 shows a non-overlapping clock generator. Non-overlapping clock generator can be used to insure that no signals can propagate through more than one latch at a time. It can synchronize φ and φ by latch so that there is no time delay between two clock. Thus, chopper modulator can be correctly operation.

4.4 Simulation

Fig. 4.4-1 shows the AC response simulation result of the CBIA. The ft is at 70k Hz, the gain is 20dB, and the phase margin is 50°˚. Fig. 4.4-2 shows the AC response simulation result of the DDA. The ft is at 50k Hz, the gain is 90dB, and the phase margin is 70°˚. Fig. 4.4-3 shows the AC response simulation result of the second-order Butterworth low-pass filter. The f3dB is about 650Hz, and the gain is 0. The overall CBIA with PGA simulation result is shown in Fig. 4.4-4 with the gain of 36dB, 42dB, 48dB, and 54dB. The simulation result of the CMRR is about 86dB in this AFE system, as shown in Fig. 4.4-5. The simulation result of the PSRR is about 75dB in this AFE system, as shown in Fig. 4.4-6. The overall AFE system only consumes 6uA with 1V supply voltage (VDD).

Fig. 4.4-1 AC response simulation of CBIA

Fig. 4.4-2 AC response simulation of DDA

Chapter 4 A CBIA with a PGA for ECG signal Detecting

Fig. 4.4-3 AC response simulation of Low-pass filter

Fig. 4.4-4 AC response simulation of CBIA with PGA

Fig. 4.4-5 CMRR Simulation of CBIA with PGA

Fig. 4.4-6 PSRR Simulation of CBIA with PGA

Chapter 4 A CBIA with a PGA for ECG signal Detecting

Fig. 4.4-7 shows the input-referred-noise simulation result of the CBIA. From this figure we can observe that flicker noise is quite a large non-ideal effect at the baseband. As we know, chopper modulation is a low-noise technique that would modulate the noise to the chopping frequency fc. In order to efficiently reduce the flicker noise with chopper technique, the chopping frequency should be larger than 1/f noise corner. Here we choose chopping frequency fc = 10k Hz. Fig. 4.4-8 shows that the noise will be chopped to 10k Hz. Fig. 4.4-9 shows the noise simulation result after the noise is removed by the low-pass filter. Compare with Fig. 4.4-7, the noise at the baseband has been reduced due to the chopper technique.

Fig. 4.4-7 Noise response simulation of CBIA

Fig. 4.4-8 Noise response simulation of CBIA with chopper modulation

Fig. 4.4-9 Noise response simulation at the output of LPF

Chapter 4 A CBIA with a PGA for ECG signal Detecting

Fig. 4.4-10 to Fig. 4.4-13 illustrates the chopper modulation technique in time domain. Fig. 4.4-10 shows the transient response simulation at input modulation. The red line is the input sine wave signal, and the black line is the modulation signal with the chopping frequency 10k Hz. After amplifying by the CBIA, the amplified signal is as the red line that shown in Fig. 4.4-11. Follow with the demodulation, the signal will be modulated back to the baseband. The black line in Fig. 4.4-11 shows the demodulated signal, and its partial enlarged detail is shown in Fig. 4.4-12. We can observe that the waveform includes lots of chopper ripples. With the low-pass filter, the chopper ripples will be removed and the simulation result is shown in Fig. 4.4-13.

The red line shows the signal waveform at the output of low-pass filter, and the black line show the signal waveform at the output of PGA.

Fig. 4.4-10 Transient response simulation at the input modulation

Fig. 4.4-11 Transient response simulation at the output modulation

Fig. 4.4-12 Transient response simulation at the output modulation (Partial enlarged detail)

Chapter 4 A CBIA with a PGA for ECG signal Detecting

Fig. 4.4-13 Transient response simulation at the output of LPF, and the output of PGA

Fig. 4.4-14 Transient response simulation of non-overlapping clock

Fig. 4.4-14 shows the transient response simulation of non-overlapping clock. In this figure we can observe that the transition between two clocks will be synchronized.

Table 4.4-1 Summary of simulation result

Features Performance

Power supply 1V

Power 6uW

Chopper frequency 10k Hz

Programmable gain selection 36dB, 42dB, 48dB, 54dB

3dB frequency 650Hz

Input-referred noise density 83.7nV/ Hz

CMRR 86dB

PSRR 75dB

Chapter 4 A CBIA with a PGA for ECG signal Detecting

4.5 Layout

Fig. 4.5-1 Layout of ECG monitoring system (Ver.1)

Fig. 4.5-2 Layout floor plain of ECG monitoring system (Ver.1)

Fig. 4.5-1 and Fig. 4.5-2 show the layout and the layout floor plain of the ECG monitoring system. The analog-front end is integrated in this system.

4.6 Measurement

4.6.1 Die photo and PCB design

Fig. 4.6.1-1 Die photo of ECG monitoring system (Ver.1)

Fig. 4.6.1-2 PCB design of ECG monitoring system (Ver.1)

The die photograph and corresponding PCB design of the ECG monitoring system chip are shown in Fig. 4.6.1-1 and Fig. 4.6.1-2.

在文檔中 應用於生醫訊號偵測系統之低功耗前端電路 (頁 71-0)