A Wireless ECG Monitoring System

Fig. 2.2-1 Block diagram of the wireless ECG monitoring system

Fig. 2.2-1 shows the block diagram of the wireless ECG monitoring system. This system is composed by an analog front-end (AFE), an analog-to-digital converter (ADC), a digital signal processing circuit (DSP), an OOK transmitter (TX), and an OOK receiver (RX). The brief introduction of these circuits will be introduced below.

Chapter 2 ECG Signal and System Requirement

2.2.1 Analog front-end (AFE)

Fig. 2.2.1-1 Architecture of the analog front-end

Analog front-end is the beginning building block of the overall ECG monitoring system. It directly contacts with the ECG signal at the front and acts as an analog signal processor to amplify and filter the bio-signal. Typically, the amplitude of the ECG signal ranges between 100uV and 5mV, and the frequency ranges between 0.5 Hz and 250Hz. It means that the ECG signal has characteristics of low-level and low frequency so that it is easy to be interfered with noise and offset. By implementing analog front-end, we can use low-noise technique to lower the noise effect and amplify the bio-signal at the same time. The amplifier is the most critical building block of the analog front-end in terms of the signal quality and clarity. Hence, it is generally the most power consuming building block of an analog front-end. In view of this, in this thesis, the design effort focuses on implementing a low-power and low-noise amplifier. Fig. 2.2.1-1 shows the architecture of the analog front-end.

2.2.2 Analog-to-digital converter (ADC) [24][34]

Fig. 2.2.2-1 Architecture of the analog-to-digital converter

Since the limitation of the low voltage supply and low power consumption, we choose the successive approximation register (SAR) ADC as the analog-to-digital converter in this system. ADC is the key to mixed signal SoCs in that it provides the interface between the physical world and digital processing. Speed, resolution, and power consumption are three critical parameters of an ADC. As a result, the SAR ADC is usually preferred in biomedical applications due to its high power efficiency at low and medium data rates. In this design, low power consumption and small chip area are preferred, so the single-ended architecture is employed. The primary sources of power consumption in the SAR ADC are the comparator and charge/discharge of the capacitor array. To reduce power, we use dynamic comparator to avoid the static power dissipation and MOM capacitor to reduce the power consumption in DAC.

In this application, ADCs with a sampling rate 360Hz which is the same as the clock of sensor interface front-end circuits and a resolution of 10 bits or greater are well suited. The fundamental building blocks of a SAR ADC are: a sampling switch,

Chapter 2 ECG Signal and System Requirement

a digital-to-analog converter (DAC), a dynamic comparator including latch, and a successive approximation logic. Fig. 2.2.2-1 shows our proposed single-ended SAR ADC.

2.2.3 Digital signal processing circuit (DSP) [35]

Fig. 2.2.3-1 Architecture of the digital signal processing circuit

Common filtering methods are often affected by ECG waveform variety, and they may lead to signal distortion. Thus, it is necessary to study new ECG signal noise reduction method. “Discrete Wavelet transform” can be thought of as an extension of

multi-scale basis. The main advantage of wavelet transform is that it has a varying window size, which is broad at low frequencies and narrow at high frequencies. It leads to an optimal time-frequency resolution in all frequency ranges, and the signal can be analyzed in different frequency sub-bands. Therefore, it is more suitable than traditional analyzing method for ECG signal processing. Based on the multi-resolution analysis, we can apply soft thresholding for removing various noise and artifacts, and then extract R-wave feature at multi-scale to increase accuracy of detection. Fig. 2.2.3-1 shows the architecture of the digital signal processing circuit.

2.2.4 OOK transmitter (TX) [36][37]

Fig. 2.2.4-1 Architecture of the OOK transmitter

To realize a wireless ECG monitoring system, a transmitter and a receiver are needed. Fig. 2.2.4-1 shows the architecture of the OOK transmitter, which includes a voltage-controlled oscillator (VCO) and a power amplifier (PA). The voltage-controlled oscillator generates 403MHz carrier and OOK modulation is achieved by turning voltage-controlled oscillator on and off. Amplitude-shift keying (ASK) is a form of modulation that represents digital data as variations in

Chapter 2 ECG Signal and System Requirement

the amplitude of a carrier wave. On-off keying (OOK) modulation is a special case of ASK modulation. Fig. 2.2.4-2 shows the difference between ASK modulation and OOK modulation. In the case of OOK modulation, the RF signal is only transmitted when the logic of data is one and does not transmits RF signal when the logic of data is 0. In this way, we can save half of the power so that it is more suitable for wireless ECG monitoring system application.

According to the Federal Communications Commission (FCC), Medical Implant Communication Service (MICS) is the name of a specification for using a frequency band between 402 and 405 MHz in communication with medical implants. Therefore, in this system, we choose 420~205 MHz as our carrier frequency.

Fig. 2.2.4-2 (a) ASK modulation (b) OOK modulation

2.2.5 OOK receiver (RX) [38]

Fig. 2.2.5-1 Architecture of the OOK receiver

In this section, we will introduce an OOK receiver, which is also applied in MICS band system. A highly integrated receiver with low-voltage operation and low-power consumption is important for MICS communication systems. In the past, receivers are usually composed of low-noise amplifiers, down-conversion mixers, voltage-controlled oscillators, and baseband circuits. For low-IF receiver configuration, two mixers and one poly-phase filter with large chip area are necessary.

For the homodyne topology, in addition to two mixers, a large amount of analog circuits are required to handle the DC offset. These receiver architectures not only need a large chip area but also consume huge power. Hence, they are not suitable for system integration. In this work, we proposed an OOK (on-off keying) receiver without mixers and VCO, etc. Fig. 2.2.5-1 shows the architecture of the OOK receiver.

We adopt a pair of differential envelope detector in this circuit. By using this structure, we do not need additional reference voltage and can obtain a higher sensitivity.

Chapter 2 ECG Signal and System Requirement