Table 5 lists the bootloader versions of the STM32F10xxx devices.
Table 5. STM32F10xxx bootloader versions
Bootloader version number Description
V2.0 Initial bootloader version.
V2.1
– Updated Go Command to initialize the main stack pointer – Updated Go command to return NACK when jump address is in
the Option byte area or System memory area
– Updated Get ID command to return the device ID on two bytes – Update the bootloader version to V2.1
V2.2
– Updated Read Memory, Write Memory and Go commands to deny access with a NACK response to the first 0x200 bytes of RAM memory used by the bootloader
– Updated Readout Unprotect command to initialize the whole RAM content to 0x0 before ROP disable operation
5 STM32F105xx and STM32F107xx device bootloader
5.1 Bootloader configuration
The bootloader embedded in the STM32F105xx and STM32F107xx devices supports four serial peripherals: USART1, USART2, CAN2, and DFU (USB). This means that four serial peripherals are supported: USART1, USART2, CAN2 and DFU (USB).
The following table shows the hardware resources required by STM32F105xx and STM32F107xx devices used by the bootloader in System memory boot mode.
Table 6. STM32F105xx/107xx configuration in System memory boot mode
Bootloader Feature/Peripheral State Comment
The system clock frequency is 24 MHz using the PLL.
This is used only for USART1 and USART2 bootloaders and during CAN2, USB detection for CAN and DFU bootloaders (Once CAN or DFU bootloader is selected, the clock source will be derived from external crystal).
HSE enabled
The external clock is mandatory only for DFU and CAN bootloaders and it must provide one of the following frequencies: 8 MHz, 14.7456 MHz or 25 MHz.
For CAN bootloader, the PLL is used only to generate 48 MHz when 14.7456 MHz is used as HSE.
For DFU bootloader, the PLL is used to generate a 48 MHz system clock from all supported external clock frequencies.
-The clock security system (CSS) interrupt is enabled for the CAN and DFU bootloaders. Any failure (or removal) of the external clock will generate system reset.
IWDG
-The independent watchdog (IWDG) prescaler is configured to its maximum value and is periodically refreshed to prevent watchdog reset (in case the hardware IWDG option was previously enabled by the user).
System memory - 18 Kbytes starting from address 0x1FFF B000 contain the bootloader firmware.
RAM - 4 Kbytes starting from address 0x2000 0000 are used
by the bootloader firmware.
USART1 bootloader
USART1 Enabled Once initialized, the USART1 configuration is: 8 bits, even parity and 1 Stop bit.
USART1_RX pin Input PA10 pin: USART1 receives.
USART1_TX pin Output push-pull PA9 pin: USART1 transmits.
USART2_RX (PD6), CAN2_RX (PB5), OTG_FS_DM (PA11) and OTG_FS_DP (PA12) pins must be kept at a high or low level during the detection phase.
STM32F105xx and STM32F107xx device bootloader AN2606
The system clock is derived from the embedded internal high-speed RC for USARTx bootloader. This internal clock is used also for DFU and CAN bootloaders but only for the selection phase. An external clock (8 MHz, 14.7456 MHz or 25 MHz.) is required for DFU and CAN bootloader execution after the selection phase.
After downloading the application binary, if you choose to execute the Go command, all peripheral registers used by the bootloader (shown in the above table) will be initialized to their default reset values before jumping to the user application.
If the user application uses the IWDG, the IWDG prescaler value has to be adapted to meet the requirements of the application (since the prescaler was set to its maximum value by the bootloader).
USART1 and USART2 bootloaders
SysTick timer Enabled Used to automatically detect the serial baud rate from the host for USARTx bootloader.
USART2 bootloader
USART2 Enabled
Once initialized, the USART2 configuration is: 8 bits, even parity and 1 Stop bit. The USART2 uses its remapped pins.
USART2_RX pin Input PD6 pin: USART2 receive (remapped pin) USART2_TX pin Output push-pull PD5 pin: USART2 transmit (remapped pin)
USART1_RX (PA10), CAN2_RX (PB5), OTG_FS_DM (PA11) and OTG_FS_DP (PA12) pins must be kept at a high or low level during the detection phase.
CAN2 bootloader
CAN2 Enabled
Once initialized, the CAN2 configuration is: Baudrate 125 kbps, 11-bit identifier.
Note: CAN1 is clocked during the CAN bootloader execution because in STM32F105xx and
STM32F107xx devices, CAN1 manages the communication between CAN2 and SRAM.
CAN2_RX pin Input PB5 pin: CAN2 receives (remapped pin).
CAN2_TX pin Output push-pull PB6 pin: CAN2 transmits (remapped pin).
USART1_RX (PA10), USART2_RX (PD6), OTG_FS_DM (PA11) and OTG_FS_DP (PA12) pins must be kept at a high or low level during the detection phase.
DFU bootloader
USB OTG FS Enabled USB OTG FS configured in Forced Device mode OTG_FS_VBUS pin Input or alternate
function, automatically controlled by the USB OTG FS controller
PA9: Power supply voltage line
OTG_FS_DM pin PA11: USB Send-Receive data line
OTG_FS_DP pin PA12: USB Send-Receive data line
Interrupts Enabled USB_OTG_FS interrupt vector is enabled and used for USB DFU communication.
USART1_RX (PA10), USART2_RX (PD6) and CAN2_RX (PB5) pins must be kept at a high or low level during the detection phase.
Table 6. STM32F105xx/107xx configuration in System memory boot mode (continued)
Bootloader Feature/Peripheral State Comment
5.2 Bootloader hardware requirements
The hardware required to put the STM32F105xx and STM32F107xx into System memory boot mode consists of any circuitry, switch or jumper, capable of holding the BOOT0 pin high and the BOOT1 pin low during reset.
To connect to the STM32F105xx and STM32F107xx during System memory boot mode, the following conditions have to be verified:
● The RX pins of the unused peripherals in this bootloader have to be kept at a known (low or high) level, and should not be left floating during the detection phase as described below:
– If USART1 is used to connect to the bootloader: the USART2_RX (PD6),
CAN2_RX (PB5), OTG_FS_DM (PA11) and OTG_FS_DP (PA12) pins have to be kept at a high or low level and must not be left floating during the detection phase.
– If USART2 is used to connect to the bootloader: the USART1_RX (PA10), CAN2_RX (PB5), OTG_FS_DM (PA11) and OTG_FS_DP (PA12) pins have to be kept at a high or low level and must not be left floating during the detection phase.
– If CAN2 is used to connect to the bootloader: the USART1_RX (PA10),
USART2_RX (PD6), OTG_FS_DM (PA11) and OTG_FS_DP (PA12) pins have to be kept at a high or low level and must not be left floating during the detection phase.
– If DFU is used to connect to the bootloader: the USART1_RX (PA10),
USART2_RX (PD6) and CAN2_RX (PB5) pins have to be kept at a high or low level and must not be left floating during the detection phase.
● Connection to the peripheral to be performed through:
– an RS232 serial interface (example, ST3232 RS232 transceiver) has to be directly connected to the USART1_RX (PA10) and USART1_TX (PA9) pins when
USART1 is used, or to the USART2_RX (PD6) and USART2_TX (PD5) pins when USART2 is used
– a CAN interface (CAN transceiver) has to be directly connected to the CAN2_RX (PB5) and CAN2_TX (PB6) pins
– a certified USB cable has to be connected to the microcontroller (optionally an ESD protection circuitry can be used)
The USART1_CK, USART1_CTS and USART1_RTS pins are not used, therefore the application can use these pins for other peripherals or GPIOs. The same note is applicable for USART2.
Once the USB Device is enabled, all its related pins are dedicated to USB communication only, and cannot be used for other application purposes.
The user can control the BOOT0 and Reset pins from a PC serial applet using the RS232 serial interface which controls BOOT0 through the CTS line and Reset through the DCD line. The user must use a full null modem cable. The necessary hardware to implement for this control exists in the STM3210C-EVAL board. For more details about this, refer to document: “STM3210C-EVAL board user manual”, available from the STMicroelectronics website: http://www.st.com.
STM32F105xx and STM32F107xx device bootloader AN2606
5.3 Bootloader selection
The STM32F105xx and STM32F107xx embedded bootloader supports four peripherals interfaces: USART1, USART2, CAN2 and DFU (USB). Any one of these peripheral interfaces can be used to communicate with the bootloader and download the application code to the internal Flash.
The embedded bootloader firmware is able to auto-detect the peripheral interface to be used. In an infinite loop, it detects any communication on the supported bootloader interfaces.
Note: The RX pins of the peripherals not used in this bootloader must be kept at a known (low or high) level and should not be left floating during the detection phase as described below.
Refer to Section 5.2: Bootloader hardware requirements for more information.
To use the USART bootloader on USART1 or USART2, connect the serial cable to the desired interface. Once the bootloader detects the data byte 0x7F on this interface, the bootloader firmware executes the auto-baud rate sequence and then enters a loop, waiting for any USART bootloader command.
To use the CAN2 interface, connect the CAN cable to CAN2. Once the bootloader detects a frame on the CAN2_RX pin (PB5), the bootloader firmware enters a CAN loop and starts to check the external clock frequency value, if the HSE is 8 MHz, 14.7456 MHz or 25 MHz CAN bootloader firmware enters an infinite loop and waits until it receives a message, otherwise a system reset is generated.
If a USB cable is plugged into the microcontroller’s USB interface at any time during the bootloader firmware selection sequence, the bootloader then enters the DFU bootloader loop waiting for any DFU bootloader command.
To use the USART or the CAN bootloader, it is mandatory that no USB cable is connected to the USB peripheral during the selection phase. Once the USART or CAN bootloader is selected, the user can plug a USB cable without impacting the selected bootloader execution except commands which generate a system reset.
Once one interface is selected for the bootloader, all other interfaces are disabled.
The figure below shows the bootloader detection mechanism. More details are provided in the sections corresponding to each peripheral bootloader.
Figure 2. Bootloader selection for STM32F105xx and STM32F107xx devices
MS32103V1
System Reset
System Init (Clock, GPIOs, IWDG, SysTick) USB clock to 48 MHz
Execute DFU
STM32F105xx and STM32F107xx device bootloader AN2606
5.4 Bootloader version
The table below lists the bootloader versions and the changes between all versions of the STM32F105xx and STM32F107xx devices.
Table 7. STM32F105xx and STM32F107xx bootloader versions
5.4.1 How to identify STM32F105xx/107xx bootloader versions
Bootloader V1.0 is implemented on devices which date code is below 937 (refer to
STM32F105xx and STM32F107xx datasheet for where to find the date code on the device marking). Bootloader V2.0 and V2.1 are implemented on devices with a date code higher or equal to 937.
There are two ways to distinguish between bootloader versions:
● When using the USART bootloader, the Get-Version command defined in AN2606 and AN3155 has been corrected in V2.1 version. It returns 0x22 instead of 0x20 as in bootloader V2.0.
Bootloader version
number Description
V1.0 Initial bootloader version.
V2.0
– Bootloader detection mechanism updated to fix the issue when GPIOs of unused peripherals in this bootloader are connected to low level or left floating during the detection phase.
For more details please refer to Section 5.4.2.
– Vector table set to 0x1FFF B000 instead of 0x0000 0000
– Go command updated (for all bootloaders): USART1, USART2, CAN2, GPIOA, GPIOB, GPIOD and SysTick peripheral registers are set to their default reset values
– DFU bootloader: USB pending interrupt cleared before executing the Leave DFU command
– DFU subprotocol version changed from V1.0 to V1.2 – Bootloader version updated to V2.0
V2.1
– Fixed PA9 excessive consumption described in Section 5.4.4.
– Get-Version command (defined in AN3155) corrected. It returns 0x22 instead of 0x20 in bootloader V2.0. Refer to Section 5.4.3 for more details.
– Bootloader version updated to V2.1
V2.2
– Fixed DFU option bytes descriptor (set to ‘e’ instead of ‘g’ because it is read/write and not erasable).
– Fixed DFU polling timings for Flash Read/Write/Erase operations.
– Robustness enhancements for DFU bootloader interface.
– Updated bootloader version to V2.2.
● The values of the vector table at the beginning of the bootloader code are different. The user software (or via JTAG/SWD) reads 0x1FFFE945 at address 0x1FFFB004 for bootloader V2.0 0x1FFFE9A1 for bootloader V2.1, and 0x1FFFE9C1 for bootloader V2.2.
● The DFU version is the following:
– V2.1 in bootloader V2.1 – V2.2 in bootloader V2.2.
It can be read through the bcdDevice field of the DFU Device Descriptor.
5.4.2 Bootloader unavailability on STM32F105xx/STM32F107xx devices with a date code below 937
Description
The bootloader cannot be used if the USART1_RX (PA10), USART2_RX (PD6, remapped), CAN2_Rx (PB5, remapped), OTG_FS_DM (PA11), and/or OTG_FS_DP (PA12) pin(s) are held low or left floating during the bootloader activation phase.
The bootloader cannot be connected through CAN2 (remapped), DFU (OTG FS in Device mode), USART1 or USART2 (remapped).
On 64-pin packages, the USART2_RX signal remapped PD6 pin is not available and it is internally grounded. In this case, the bootloader cannot be used at all.
Workaround
● For 64-pin packages
None. The bootloader cannot be used.
● For 100-pin packages
Depending on the used peripheral, the pins for the unused peripherals have to be kept at a high level during the bootloader activation phase as described below:
– If USART1 is used to connect to the bootloader, PD6 and PB5 have to be kept at a high level.
– If USART2 is used to connect to the bootloader, PA10, PB5, PA11 and PA12 have to be kept at a high level.
– If CAN2 is used to connect to the bootloader, PA10, PD6, PA11 and PA12 have to be kept at a high level.
– If DFU is used to connect to the bootloader, PA10, PB5 and PD6 have to be kept at a high level.
Note: This limitation applies only to STM32F105xx and STM32F107xx devices with a date code below 937. STM32F105xx and STM32F107xx devices with a date code higher or equal to 937 are not impacted. See STM32F105xx and STM32F107xx datasheet for where to find the date code on the device marking.
STM32F105xx and STM32F107xx device bootloader AN2606
5.4.3 USART bootloader Get-Version command returns 0x20 instead of 0x22
Description
In USART mode, the Get-Version command (defined in AN3155) returns 0x20 instead of 0x20.
This limitation is present on bootloader versions V1.0 and V2.0, while it is fixed in bootloader version 2.1.
Workaround None.
5.4.4 PA9 excessive power consumption when USB cable is plugged in bootloader V2.0
Description
When connecting an USB cable after booting from System-Memory mode, PA9 pin
(connected to VBUS=5 V) is also shared with USART TX pin which is configured as alternate push-pull and forced to 0 since the USART peripheral is not yet clocked. As a consequence, a current higher than 25 mA is drained by PA9 I/O and may affect the I/O pad reliability.
This limitation is fixed in bootloader version 2.1 by configuring PA9 as alternate function push-pull when a correct 0x7F is received on RX pin and the USART is clocked. Otherwise, PA9 is configured as alternate input floating.
Workaround None.
6 STM32F101xx and STM32F103xx XL-density device bootloader
Throughout this section, STM32F10xxx XL-density is used to refer to XL-density STM32F101xx and STM32F103xx devices.