The bootloader of the medium-density ultralow power devices has some specific features that should be taken into consideration, as described below:
● In addition to standard memories (internal Flash, internal SRAM, option bytes and System memory), the STM32L100xx value line and STM32L15xxx medium-density device bootloader firmware supports Data Memory (4 Kbytes from 0x08080000 to 0x08080FFF). Refer to the PM0062 Programming manual for more information.
● Flash memory write operations are performed through a program memory half page write operation. The bootloader firmware manages half page write operations at non-aligned addresses. Consequently, all write operations must only be Word-non-aligned (the address should be a multiple of 4). The number of data to be written must also be a multiple of 4 (non-aligned half page write addresses are accepted). Be aware of the duration needed for a write operation by referring to the product datasheet.
● Data memory can be read and written but cannot be erased using the Erase
Command. When writing in a Data memory location, the bootloader firmware manages the erase operation of this location before any write. A write to Data memory must be Word-aligned (address to be written should be a multiple of 4) and the number of data must also be a multiple of 4. To erase a Data memory location, you can write zeros at this location.
● Option byte
Address is 0x1FF80000. They allow three levels of protection:
– Level 0 – Level 1 – Level 2
Refer to PM0062 programming manual for more details about protection levels.
● Read protect command corresponds to the Level 1 protection.
● Read unprotect command corresponds to the Level 0 protection.
● Mass erase command is not supported by STM32L15xxx medium-density device bootloader firmware. To perform a mass erase operation, two options are available:
– Erase all sectors one by one using the Erase command
– Set protection level to Level 1. Then, set it to Level 0 (using the Read protect command and then the Read Unprotect command). This operation results in a mass erase of the internal Flash memory (refer to Programming Manual PM0062 for more details).
STM32L151xx, STM32L152xx and STM32L100xx medium-density ultralow power device
bootload-7.5 Bootloader version
The following table lists the STM32L100xx value line and STM32L15xxx medium-density bootloader versions.
Table 12. STM32L100xx value line and STM32L15xxx medium-density bootloader versions
Bootloader version number
Description Known limitations
V2.0 Initial bootloader version.
When a Read Memory command or Write Memory command is issued with an unsupported memory address and a correct address checksum (ie. address 0x6000 0000), the command is aborted by the bootloader device, but the NACK (0x1F) is not sent to the host. As a result, the next 2 bytes (which are the number of bytes to be read/written and its checksum) are considered as a new command and its checksum.(1)
1. If the “number of data - 1” (N-1) to be read/written is not equal to a valid command code (0x00, 0x01, 0x02, 0x11, 0x21, 0x31, 0x43, 0x44, 0x63, 0x73, 0x82 or 0x92), then the limitation is not perceived from the host since the command is NACKed anyway (as an unsupported new command).
8 STM32L151xx and STM32L152xx medium-density plus ultralow power device bootloader
Throughout this section, STM32L15xxx medium-density plus is used to refer to the STM32L151xx and STM32L152xx medium-density plus ultralow power devices.
8.1 Bootloader configuration
The bootloader embedded in the STM32L15xxx medium-density plus devices supports three serial interfaces: USART1, USART2 and DFU (USB).
Table 13 shows the required hardware resources of STM32L15xxx medium-density plus devices used by the bootloader in System memory boot mode.
Table 13. STM32L15xxx medium-density plus configuration in System memory boot mode
Bootloader Feature/Peripheral State Comment
Common to all bootloaders
RCC
HSI enabled
The system clock frequency is 16 MHz using the HSI. This is used only for USART1 and USART2 bootloaders and during USB detection for DFU bootloader (once the DFU bootloader is selected, the clock source is derived from the external crystal).
HSE enabled
The external clock is mandatory only for the DFU bootloader and must be in the following range:
[24, 16, 12, 8, 6, 4, 3, 2] MHz.
The PLL is used to generate the USB 48 MHz clock and the 32 MHz clock for the system clock.
-The clock security system (CSS) interrupt is enabled for the DFU bootloader. Any failure (or removal) of the external clock generates a system reset.
IWDG
-The independent watchdog (IWDG) prescaler is configured to its maximum value and is periodically refreshed to prevent watchdog resets (in case the hardware IWDG option was previously enabled by the user).
Power Voltage range is set to Voltage Range 1.
System memory - 8 Kbytes starting from address 0x1FF0 0000.
This area contains the bootloader firmware.
RAM - 4 Kbytes starting from address 0x2000 0000
are used by the bootloader firmware.
STM32L151xx and STM32L152xx medium-density plus ultralow power device bootloader AN2606
Note: For the DFU interface, the external clock source (HSE) is required for USB operations. The detection of the HSE value is done by the bootloader firmware and is based on the internal oscillator clock (HSI, MSI). Thus, when due to temperature or other conditions, the internal oscillator precision is altered above the tolerance band (1% around the theoretical value), the bootloader might calculate a wrong HSE frequency value. In this case, the bootloader DFU interface might dysfunction or might not work at all.
The system clock is derived from the embedded internal high-speed RC for the USARTx bootloader. This internal clock is also used the for DFU bootloader but only for the selection phase. An external clock in the range of [24, 16, 12, 8, 6, 4, 3, 2] MHz is required for the execution of the DFU bootloader after the selection phase.
After downloading the application binary, if you choose to execute the Go command, all peripheral registers used by the bootloader (shown in the above table) are initialized to their default reset values before jumping to the user application.
If the user application uses the IWDG, the IWDG prescaler value has to be adapted to meet the requirements of the application (since the prescaler was set to its maximum value by the bootloader).
USART1 bootloader
USART1 Enabled Once initialized, the USART1 configuration is 8 bits, even parity and 1 stop bit.
USART1_RX pin Input PA10 pin: USART1 in reception mode USART1_TX pin Output PA9 pin: USART1 in transmission mode USART2_RX (PD6), USB_DM (PA11) and USB_DP (PA12) pins must be kept at a high or low level during the detection phase.
USART1 and USART2 bootloaders
SysTick timer Enabled Used to automatically detect the serial baud rate from the host for the USARTx bootloader.
USART2 bootloader
USART2 Enabled
Once initialized, the USART2 configuration is 8 bits, even parity and 1 stop bit. The USART2 uses its remapped pins.
USART2_RX pin Input PD6 pin: USART2 in reception mode USART2_TX pin Output PD5 pin: USART2 in transmission mode USART1_RX (PA10), USB_DM (PA11) and USB_DP (PA12) pins must be kept at a high or low level during the detection phase.
DFU bootloader
USB_DM pin Input or alternate function,
automatically controlled by the USB
PA11: USB send-receive data line
USB_DP pin PA12: USB send-receive data line
Interrupts Enabled USB low priority interrupt vector is enabled and used for USB DFU communication.
USART1_RX (PA10) and USART2_RX (PD6) pins must be kept at a high or low level during the detection phase.
Table 13. STM32L15xxx medium-density plus configuration in System memory boot mode (continued)
Bootloader Feature/Peripheral State Comment
8.2 Bootloader hardware requirements
The hardware required to put the STM32L15xxx medium-density plus devices into System memory boot mode consists of any circuitry, switch or jumper, capable of holding the BOOT0 pin high and the BOOT1 pin low during reset.
To connect to the STM32L15xxx medium-density plus devices during System memory boot mode, the following conditions have to be verified.
● The RX pin of the peripherals that are not used in this bootloader have to be kept at a known (low or high) level, and should not be left floating during the detection phase as described below.
– If USART1 is used to connect to the bootloader: the USART2_RX (PD6), USB_DM (PA11) and USB_DP (PA12) pins have to be kept at a high or low level and must not be left floating during the detection phase.
– If USART2 is used to connect to the bootloader: the USART1_RX (PA10), USB_DM (PA11) and USB_DP (PA12) pins have to be kept at a high or low level and must not be left floating during the detection phase.
– If DFU (USB) is used to connect to the bootloader: the USART1_RX (PA10) and USART2_RX (PD6) pins have to be kept at a high or low level and must not be left floating during the detection phase.
● Connection to the peripheral.
– An RS-232 serial interface (example, ST3232 RS-232 transceiver) has to be directly connected to the USART1_RX (PA10) and USART1_TX (PA9) pins when USART1 is used, or to the USART2_RX (PD6) and USART2_TX (PD5) pins when USART2 is used.
– A certified USB cable has to be connected to the microcontroller (optionally an ESD protection circuitry can be used).
The USART1_CK, USART1_CTS and USART1_RTS pins are not used. As a result, the application can use these pins for other peripherals or GPIOs. This is also applicable for USART2.
8.3 Bootloader selection
The STM32L15xxx medium-density plus embedded bootloader supports three serial interfaces: USART1, USART2 and DFU (USB). Any one of these peripheral interfaces can be used to communicate with the bootloader and download the application code to the internal Flash.
The embedded bootloader firmware is able to auto-detect the peripheral interface to be used. In an infinite loop, it detects any communication on the supported bootloader interfaces.
Note: The RX pins of the peripherals not used in this bootloader must be kept at a known (low or high) level and should not be left floating during the detection phase as described below.
Refer to Section 8.2: Bootloader hardware requirements for more information.
To use the USART bootloader on USART1 or USART2, connect the serial cable to the desired interface. Once the bootloader detects the data byte 0x7F on this interface, the bootloader firmware executes the auto-baudrate sequence and then enters a loop, waiting for any USART bootloader command.
STM32L151xx and STM32L152xx medium-density plus ultralow power device bootloader AN2606
If a USB cable is plugged into the microcontroller’s USB interface at any time during the bootloader firmware selection sequence, the bootloader enters DFU bootloader loop waiting for any DFU bootloader command.
To use the USART bootloader, it is mandatory that no USB Host be connected to the USB peripheral during the selection phase. Once the USART bootloader is selected, the user can plug a USB cable without impacting the selected bootloader execution except for the commands which generate a system reset.
Once an interface is selected for the bootloader, the other interface is disabled.
Figure 5 shows the bootloader detection mechanism. More details are provided in the sections corresponding to each peripheral bootloader.
Figure 5. Bootloader selection for STM32L15xxx medium-density plus devices
System Reset
System Init (clock, GPIOs, IWDG, SysTick)
HSE = 24, 16, 12, 8, 6, 4, 3, 2 MHz 0x7F received on
USART_1
0x7F received on USART_2
Configure USART2
Execute BL_USART_Loop
for USART2 Configure USB
Configure USART1
Execute BL_USART_Loop
for USART1
Reconfigure system clock to 48 MHz and USB clock to 48 MHz
Execute DFU bootloader using USB
interrupts No
No No
Yes
Yes
Generate system reset No
Disable all interrupt sources
Yes
Disable all interrupt sources Yes
USB cable Detected
MS30868V1
STM32L151xx and STM32L152xx medium-density plus ultralow power device bootloader AN2606
8.4 Important considerations
The bootloader of the STM32L15xxx medium-density plus devices has some specific features that should be taken into consideration, as described below.
● In addition to standard memories (internal Flash, internal SRAM, option bytes and system memory), the STM32L15xxx medium-density plus devices bootloader firmware supports Data Memory (8 Kbytes from 0x08080000 to 0x08081FFF). Refer to the PM0062 Programming manual for more information.
● Flash memory write operations are performed through a program memory half page write operation. The bootloader firmware manages half page write operations at non-aligned addresses. Consequently, all write operations must only be word-non-aligned (the address should be a multiple of 4). The number of data to be written must also be a multiple of 4 (non-aligned half page write addresses are accepted). Be aware of the duration needed for a write operation by referring to the product datasheet.
● Data memory can be read and written but cannot be erased using the Erase
Command. When writing in a Data memory location, the bootloader firmware manages the erase operation of this location before any write. A write to Data memory must be word-aligned (address to be written should be a multiple of 4) and the number of data must also be a multiple of 4. To erase a Data memory location, you can write zeros at this location.
● Option byte
Address is 0x1FF80000. They allow three levels of protection:
– Level 0 – Level 1 – Level 2
Refer to the PM0062 programming manual for more details about protection levels.
● Read protect commands correspond to the Level 1 protection.
● Read unprotect commands corresponds to the Level 0 protection.
● Mass erase commands are not supported by the STM32L15xxx medium-density plus devices bootloader firmware. To perform a mass erase operation, two options are available.
– Erase all sectors one by one using the Erase command.
– Set the protection level to Level 1. Then, set it to Level 0 (using the Read protect command and then the Read Unprotect command). This operation results in a mass erase of the internal Flash memory (refer to the Programming Manual PM0062 for more details).
If the application is loaded into the Flash memory at an address different to 0x08000000, the vector table has to be relocated to start from the address where the application is loaded.
8.5 Bootloader version
Table 14 lists the bootloader versions for the STM32L15xxx medium-density plus devices.
Table 14. STM32L15xxx medium-density plus bootloader versions Bootloader version
number Description Known limitations
V4.0 Initial bootloader version
For the USART interface, two consecutive NACKs instead of 1 NACK are sent when a Read Memory or Write Memory command is sent and the RDP level is active.
STM32L151xx, STM32L152xx and STM32L162xx high-density ultralow power device bootloader
9 STM32L151xx, STM32L152xx and STM32L162xx high-density ultralow power device bootloader
Throughout this section, STM32L1xxxx high-density is used to refer to STM32L151xx, STM32L152xx and STM32L162xx high-density ultralow power devices.
9.1 Dual bank boot feature
The STM32L1xxxx high-density devices have two Flash memory banks: Bank 1 and Bank 2.
They feature an additional boot mechanism which allows booting from Bank 2 or Bank 1 depending on BFB2 bit status (bit 7 in the user option bytes located at 0x1FF8 0004).
● When the BFB2 bit is reset and the boot pins are configured to boot from Flash memory (BOOT0 = 0 and BOOT1 = x), after reset the device boots from the System memory and executes the embedded bootloader code which implements the dual bank Boot mode:
a) The code first checks Bank 2. If it contains a valid code (see note below), it jumps to the application code located in Bank 2 and leaves the bootloader.
b) If the Bank 2 code is not valid, it checks Bank 1 code. If it is valid (see note below), it jumps to the application located in Bank 1.
c) If both Bank 2 and Bank 1 do not contain valid code (see note below), the normal bootloader operations are executed as described in the following sections and no jump to Flash banks is performed. Refer to Figure 6: Bootloader selection for STM32L1xxxx high-density devices for more details.
3. When BFB2 bit is set (default state), the dual bank boot mechanism is not performed.
Note: The code is considered as valid when the first data (at the bank start address, which should be the stack pointer) points to a valid address into the internal SRAM memory (stack top address). If the first address points to any other location (out of the internal SRAM) the code is considered not valid.
A dual bank Boot mode example (FLASH\Dual_Boot) is provided within the STM32L1xxxx Standard Peripheral Library available from http://www.st.Com.
For the STM32L1xxxx high-density devices, the Flash memory, system memory or SRAM is selected as the boot space, as shown in Table 15 below.
Table 15 shows that the STM32L1xxxx high-density devices enter System memory boot mode in three cases:
● If the BOOT pins are configured as follows:
BOOT0 = 1 and BOOT1 = 0
● If the BFB2 bit is reset and protection Level2 is enabled
● If the BFB2 bit is reset and boot pins are configured as follows:
BOOT0 = 0 and BOOT1 = x Table 15. Boot pin and BFB2 bit configuration
BFB2
User Flash memory Bank1 is selected as the boot space
0 1 No X X System memory System memory is selected as the
boot space
0 1 Yes X X User Flash
memory
User Flash memory Bank1 is selected as the boot space
1 1 No X X Embedded SRAM Embedded SRAM is selected as the
boot space
1 1 Yes X X User Flash
memory
User Flash memory Bank1 is selected as the boot space
0
X 0
X
Yes X System memory User Flash memory Bank2 is selected as the boot space No Yes System memory User Flash memory Bank1 is
selected as the boot space No No No System memory System memory is selected as the
boot space
Yes No No System memory CPU blocked (halted)
0 1 No X X System memory System memory is selected as the
boot space
1 1 No X X Embedded SRAM Embedded SRAM is selected as the
boot space
X 1 Yes
Yes X System memory User Flash memory Bank2 is selected as the boot space No Yes System memory User Flash memory Bank1 is
selected as the boot space No No System memory CPU blocked (halted)
STM32L151xx, STM32L152xx and STM32L162xx high-density ultralow power device bootloader
Note: When the conditions a, b, and c described below are fulfilled, it is equivalent to configuring boot pins for system memory boot (BOOT0 = 1 and BOOT1 = 0). In this case normal bootloader operations are executed.
a) BFB2 bit is reset
b) Both banks don’t contain valid code
c) Boot pins configured as follows: BOOT0 = 0 and BOOT1 = x
When the BFB2 bit is cleared, and Bank 2 and/or Bank 1 contain valid user application code, the Dual Bank Boot is always performed (bootloader always jumps to the user code and never continues normal operations).
Consequently, if you have cleared the BFB2 bit (to boot from Bank 2) then, to be able to execute the bootloader code, you have to either:
- program the content of address 0x0808 0000 (base address of Bank2) and 0x0800 0000 (base address of Bank1) to 0x0, or
- set the BFB2 bit to 1, BOOT0 = 1 and BOOT1 = 0.
9.2 Bootloader configuration
The bootloader embedded in STM32L1xxxx high-density devices supports three serial interfaces: USART1, USART2 and DFU (USB)
The following table shows the required hardware resources of STM32L1xxxx high-density devices used by the bootloader in System memory boot mode.
Table 16. STM32L1xxxx high-density configuration in System memory boot mode
Bootloader Feature/Peripheral State Comment
Common to all bootloaders
RCC
HSI enabled
The system clock frequency is 16 MHz using the HSI. This is used only for USART1 and USART2 bootloaders and during USB detection for DFU bootloader (once the DFU bootloader is selected, the clock source will be derived from the external crystal).
HSE enabled
The external clock is mandatory only for DFU bootloader and it must be in the following range: [24, 16, 12, 8, 6, 4, 3, 2]
MHz.
The PLL is used to generate the USB 48 MHz clock and the 32 MHz clock for the system clock.
-The clock security system (CSS) interrupt is enabled for the DFU bootloader. Any failure (or removal) of the external clock generates system reset.
IWDG
-The independent watchdog (IWDG) prescaler is configured to its maximum value and is periodically refreshed to
-The independent watchdog (IWDG) prescaler is configured to its maximum value and is periodically refreshed to