For STM32F101xx and STM32F103xx XL-density devices (these devices have two Flash memory banks: Bank 1 and Bank 2), an additional boot mechanism is available which allows booting from Bank 2 or Bank 1 (depending on the BFB2 bit status (bit 19 in the user option bytes @ 0x1FFFF800)).
1. When the BFB2 bit is reset, and the boot pins are configured to boot from the Flash memory (BOOT0 = 0 and BOOT1 = x) then, after reset, the device boots from the System memory and executes the embedded bootloader code which implements the dual bank Boot mode:
a) First, the code checks Bank 2. If it contains a valid code (see Note: below), it jumps to application located in Bank 2 and leaves the bootloader.
b) If the Bank 2 code is not valid, it checks Bank 1 code. If it is valid (see “note”
below), it jumps to the application located in Bank 1.
c) If both Bank 2 and Bank 1 do not contain valid code (see “note” below), the normal bootloader operations are executed as described in the following sections (no jump to Flash banks is executed). Refer to Figure 3: Bootloader selection for STM32F10xxx XL-density devices for more details.
2. When the bit BFB2 is set (default state), the dual bank boot mechanism is not performed.
Note: The code is considered as valid when the first data (at the bank start address, which should be the stack pointer) points to a valid address into the internal SRAM memory (stack top address). If the first address points to any other location (out of the internal SRAM) the code is considered not valid.
A dual bank boot mode example (FLASH\Dual_Boot) is provided within the STM32F10x Standard Peripheral Library available on http://www.st.com.
STM32F101xx and STM32F103xx XL-density device bootloader AN2606
For the STM32F101xx and STM32F103xx XL-density devices, the Flash memory, system memory or SRAM is selected as the boot space, as shown in Table 8 below.
Table 8 shows that the XL-density devices enter System memory boot mode in two cases:
1. If the BOOT pins are configured as follows: BOOT0 = 1 and BOOT1 = 0 2. Or if:
a) the BFB2 bit is reset and
b) boot pins are configured as follows: BOOT0 = 0 and BOOT1 = x
Note: When conditions a, b, and c below are fulfilled, it is equivalent to configuring boot pins for system memory boot (BOOT0 = 1 and BOOT1 = 0). In this case normal bootloader operations are executed.
a) BFB2 bit is reset
b) Both banks don’t contain valid code
c) Boot pins configured as follows: BOOT0 = 0 and BOOT1 = x
When the BFB2 bit is cleared, and Bank 2 and/or Bank 1 contain valid user application code, the Dual Bank Boot is always performed (bootloader always jumps to the user code and never continues normal operations).
Consequently, if you have cleared the BFB2 bit (to boot from Bank 2) then, to be able to execute the bootloader code, you have to either:
- program the content of address 0x0808 0000 (base address of Bank2) and 0x0800 0000 (base address of Bank1) to 0x0, or
- set the BFB2 bit to 1, BOOT0 = 1 and BOOT1 = 0.
Table 8. Boot pin and BFB2 bit configuration
BFB2 bit
Boot mode selection pins
Boot mode Aliasing
BOOT1 BOOT0
1
X 0 User Flash memory User Flash memory is selected as the boot space
0 1 System memory System memory is selected as the boot space 1 1 Embedded SRAM Embedded SRAM is selected as the boot
space
0
X 0 System memory System memory is selected as the boot space then dual bank mechanism is executed 0 1 System memory System memory is selected as the boot space
then dual bank mechanism is executed 1 1 Embedded SRAM Embedded SRAM is selected as the boot
space
6.2 Bootloader configuration
The bootloader embedded in STM32F10xxx XL-density supports two serial interfaces:
USART1 and USART2.
The following table shows the required hardware resources of STM32F10xxx XL-density devices used by the bootloader in System memory boot mode.
The system clock is derived from the embedded internal high-speed RC, no external quartz is required for the bootloader code.
After downloading the application binary, if you choose to execute the Go command, all peripheral registers used by the bootloader (shown in Table 9) are initialized to their default reset values before jumping to the user application.
If the user application uses the IWDG, the IWDG prescaler value has to be adapted to meet the requirements of the application (since the prescaler was set to its maximum value by the bootloader).
Table 9. STM32F10xxx XL-density configuration in System memory boot mode
Bootloader Feature/periphera
l State Comment
Common to all bootloaders
Clock source HSI enabled The system clock is equal to 24 MHz using the PLL.
RAM - 2 Kbytes starting from address 0x2000 0000 are used by the bootloader firmware.
System memory - 6 Kbytes starting from address 0x1FFF E000 contain the bootloader firmware.
IWDG
-The independent watchdog (IWDG) prescaler is configured to its maximum value and is periodically refreshed to prevent watchdog reset (in case the hardware IWDG option was previously enabled by the user).
USART1 bootloader
USART1 Enabled Once initialized, the USART1 configuration is: 8 bits, even parity and 1 Stop bit.
USART1_RX pin Input PA10 pin: USART1 receives.
USART1_TX pin Output
push-pull PA9 pin: USART1 transmits.
USART2_RX (PD6) pin must be kept at a high or low level during the detection phase.
USART2 bootloader
USART2 Enabled Once initialized, the USART2 configuration is: 8 bits, even parity and 1 Stop bit.
USART2_RX pin Input PD6 pin: USART2 receives (remapped pins).
USART2_TX pin Output
push-pull PD5 pin: USART2 transmits (remapped pins).
USART1_RX (PA10) pin must be kept at a high or low level during the detection phase.
USART1 and USART2 bootloaders
SysTick timer Enabled Used to automatically detect the serial baud rate from the host.
STM32F101xx and STM32F103xx XL-density device bootloader AN2606
6.3 Bootloader hardware requirements
The hardware required to put the STM32F10xxx XL-density devices into System memory boot mode consists of any circuitry, switch or jumper, capable of holding the BOOT0 pin high and the BOOT1 pin low during reset.
Note: As explained in Section 6.1: Dual bank boot feature, the System memory boot mode can also be executed by software when the BFB2 bit is reset, both banks start addresses are erased, and boot pins are configured to boot from Flash memory.
To connect to the STM32F10xxx XL-density devices during System memory boot mode, the following conditions have to be verified:
● The RX pin of the peripherals unused in this bootloader have to be kept at a known (low or high) level, and should not be left floating during the detection phase as described below:
– If the USART1 is used to connect to the bootloader: the USART2_RX (PD6) pin has to be kept at a high or low level and must not be left floating during the detection phase.
– If the USART2 is used to connect to the bootloader: the USART1_RX (PA10) pin has to be kept at a high or low level and must not be left floating during the detection phase.
● When the BFB2 bit is cleared, and Bank 2 and/or Bank 1 contain a valid user
application code, the Dual Bank Boot is always performed (bootloader always jumps to the user code and never continues normal operations). Consequently, if you have cleared the BFB2 bit (to boot from Bank 2), then to be able to execute the bootloader code, you have to either:
– program the content of address 0x0808 0000 (base address of Bank2) and 0x0800 0000 (base address of Bank1) to 0x0, or
– set the BFB2 bit to 1, BOOT0 = 1 and BOOT1 = 0.
● Connection to the peripheral to be performed through:
– an RS232 serial interface (example, ST3232 RS232 transceiver) has to be directly connected to the USART1_RX (PA10) and USART1_TX (PA9) pins when
USART1 is used, or to the USART2_RX (PD6) and USART2_TX (PD5) pins when USART2 is used
The USART1_CK, USART1_CTS and USART1_RTS pins are not used, therefore the application can use these pins for other peripherals or GPIOs. This is also applicable for USART2.
6.4 Bootloader selection
The STM32F10xxx XL-density embedded bootloader supports two peripheral interfaces:
USART1 and USART2. Any one of these peripheral interfaces can be used to communicate with the bootloader and download the application code to the internal Flash.
The embedded bootloader firmware is able to auto-detect the peripheral interface to be used. In an infinite loop, it detects any communication on the supported bootloader interfaces.
Note: The RX pins of the peripherals not used in this bootloader must be kept at a known (low or high) level and should not be left floating during the detection phase as described below.
Refer to Section 6.3: Bootloader hardware requirements for more information.
To use the USART bootloader on USART1 or USART2, connect the serial cable to the desired interface. Once the bootloader detects the data byte 0x7F on this interface, the bootloader firmware executes the auto-baudrate sequence and then enters a loop, waiting for any USART bootloader command.
Once one interface is selected for the bootloader, the other interface is disabled.
Figure 3 shows the bootloader detection mechanism. More details are provided in the sections corresponding to each peripheral bootloader.
STM32F101xx and STM32F103xx XL-density device bootloader AN2606
Figure 3. Bootloader selection for STM32F10xxx XL-density devices
MS32104V1
System Reset
0x7F received on USART_1
0x7F received on USART_2
Configure USART2
Execute BL_USART_Loop
for USART2
Configure USART1
Execute BL_USART_Loop
for USART1 No
No
Yes Yes BFB2 bit reset
(BFB2 = 0)
If Value
@0x08080000 is within int. SRAM
address
If Value
@0x08000000 is within int. SRAM
address
System Init (Clock, GPIOs, IWDG, SysTick) Continue Bootloader execution
Yes
No
No
Disable all interrupt sources No
Jump to user code in Bank2
Jump to user code in Bank1 Yes
Yes
6.5 Bootloader version
Table 10 lists the bootloader versions for the STM32F101xx and STM32F103xx XL-density devices.
Table 10. XL-density bootloader versions Bootloader version
number Description
V2.1 Initial bootloader version
STM32L151xx, STM32L152xx and STM32L100xx medium-density ultralow power device
bootload-7 STM32L151xx, STM32L152xx and STM32L100xx medium-density ultralow power device bootloader
Throughout this section, STM32L15xxx medium-density is used to refer to medium-density STM32L151xx and STM32L152xx ultralow power devices.
7.1 Bootloader configuration
The bootloader embedded in STM32L100xx value line and STM32L15xxx medium-density devices supports two serial interfaces: USART1 and USART2 peripherals.
The following table shows the required hardware resources of STM32L100xx value line and STM32L15xxx medium-density devices used by the bootloader in System memory boot mode.
The system clock is derived from the embedded internal high-speed RC, no external quartz is required for the bootloader code.
Table 11. STM32L100xx and STM32L15xxx configuration in System memory boot mode
Bootloader Feature/peripheral State Comment
Common to all bootloaders
Clock source HSI enabled The system clock is equal to 16 MHz.
RAM - 2 Kbytes starting from address 0x20000000 are used by the bootloader firmware.
System memory - 4 Kbytes starting from address 0x1FF00000 contain the bootloader firmware.
IWDG
-The independent watchdog (IWDG) prescaler is configured to its maximum value and is periodically refreshed to prevent watchdog reset (in case the hardware IWDG option was previously enabled by the user).
Power - Voltage range is set to Voltage Range 1.
USART1 bootloader
USART1 Enabled Once initialized, the USART1 configuration is: 8 bits, even parity and 1 Stop bit.
USART1_RX pin Input PA10 pin: USART1 receives.
USART1_TX pin Output PA9 pin: USART1 transmits.
USART2_RX (PD6) pin must be kept at a high or low level during the detection phase.
USART2 bootloader
USART2 Enabled Once initialized, the USART2 configuration is: 8 bits, even parity and 1 Stop bit.
USART2_RX pin Input PD06 pin: USART2 receives.
USART2_TX pin Output PD05 pin: USART2 transmits.
USART1_RX (PA10) pin must be kept at a high or low level during the detection phase.
USART1 and USART2 bootloaders
SysTick timer Enabled Used to automatically detect the serial baud rate from the host.
After downloading the application binary, if you choose to execute the Go command, all peripheral registers used by the bootloader (shown in the above table) are initialized to their default reset values before jumping to the user application. If the user application uses the IWDG, the IWDG prescaler value has to be adapted to meet the requirements of the application (since the prescaler was set to its maximum value by the bootloader).
7.2 Bootloader hardware requirements
The hardware required to put the STM32L15xxx medium-density devices into System memory boot mode consists of any circuitry, switch or jumper, capable of holding the BOOT0 pin high and the BOOT1 pin low during reset.
To connect to the STM32L15xxx medium-density devices during System memory boot mode, the following conditions have to be verified:
● The RX pins of the peripherals unused in this bootloader have to be kept at a known (low or high) level, and should not be left floating during the detection phase as described below:
– If USART1 is used to connect to the bootloader: the USART2_RX (PD6) pin has to be kept at a high or low level and must not be left floating during the detection phase.
– If USART2 is used to connect to the bootloader: the USART1_RX (PA10) pin has to be kept at a high or low level and must not be left floating during the detection phase.
● The peripheral to be used has to be connected through an RS-232 serial interface (example, ST3232 RS-232 transceiver) which must be:
– Directly connected to the USART1_RX (PA10) and USART1_TX (PA9) pins when USART1 is used
– Directly connected to the USART2_RX (PD6) and USART2_TX (PD5) pins when USART2 is used
The USART1_CK, USART1_CTS and USART1_RTS pins are not used, therefore the application can use these pins for other peripherals or GPIOs. The same note is applicable for USART2.
The user can control the BOOT0 and Reset pins from a PC serial applet using the RS-232 serial interface which controls BOOT0 through the CTS line and Reset through the DCD line. The user must use a full null modem cable. The necessary hardware to implement for this control exists in the STM32L152-EVAL board. For more details about this, refer to the
“STM32L152-EVAL board user manual” (UM1018), available from the STMicroelectronics website: http://www.st.com.
7.3 Bootloader selection
The STM32L100xx value line and STM32L15xxx medium-density devices embedded bootloader supports two peripherals interfaces: USART1 and USART2. Any one of these peripheral interfaces can be used to communicate with the bootloader and download the application code to the internal Flash.
The embedded bootloader firmware is able to auto-detect the peripheral interface to be used. In an infinite loop, it detects any communication on the supported bootloader interfaces.
STM32L151xx, STM32L152xx and STM32L100xx medium-density ultralow power device
bootload-Note: The RX pins of the peripherals not used in this bootloader must be kept at a known (low or high) level and should not be left floating during the detection phase as described below.
Refer to Section 7.2: Bootloader hardware requirements for more information.
To use the USART bootloader on USART1 or USART2, connect the serial cable to the desired interface.
Once the bootloader detects the data byte 0x7F on this interface, the bootloader firmware executes the autobaudrate sequence and then enters a loop, waiting for any USART bootloader command.
Once one interface is selected for the bootloader, the other interface is disabled.
The figure below shows the bootloader detection mechanism. More details are provided in the sections corresponding to each peripheral bootloader.
Figure 4. Bootloader selection for STM32L15xxx medium-density devices
System Reset
0x7F received on USART_1
0x7F received on USART_2
Configure USART2
Execute BL_USART_Loop
for USART2
Configure USART1
Execute BL_USART_Loop
for USART1 No
No
Yes
Yes System Init (Clock, GPIOs,
IWDG, SysTick)
Disable all interrupt sources
Disable all interrupt sources
MSv32105V1