5 Circuit Implementation and Experimental Results 40
5.2 Cascode Class E PA with Self-Biased Control Circuit Design
5.2.1 Circuit Design
In order to realize the proposed technique, a cascode Class-E power amplifier shown in Figure 5.1, with a self-biased control circuit for compensating the AM-AM and AM-PM distortion has been implemented in a 0.18 µm CMOS technology process, as shown in Figure 5.9. The self-biased control circuit intends to produce a voltage, the sum of a dc voltage and an analogue voltage. It is implemented by a voltage adder, including an operating amplifier with five resistors. Selecting the ratio of resistors, the expected output voltage is obtained. The operating amplifier has the unit-gain frequency of 100 MHz for achieving a correct output voltage of the self-biased control circuit during supply modulation. The control circuit is just to produce an expected M2 gate voltage VGG= VDD + VTH, so that it only needs to draw few micro-amperes from the 3.3 V supply.
5.2 CASCODE CLASS E PA WITH SELF-BIASED CONTROL CIRCUIT DESIGN
Figure 5.9 Detailed schematic of (a) cascode Class E PA with self-biased control circuit, and (b) self-biased control circuit.
5.2.2 Simulation Results
The result of the PA with self-biased control circuit is reported in Figure 5.10. The relationship of the envelope of the output voltage against the supply voltage is linear and the AM-PM in the supply voltage of 0.5 V to 1.8 V is less than 3°. Therefore, the proposed technique evidently has compensated the AM-AM and AM-PM distortion of the PA during supply modulation. The amplifier has the maximum output power of 16 dBm and drain efficiency of 38%, as shown in Figure 5.11. The drain efficiency is varied from 30% to 38%
as the VDD is swept from 0.5 V to 1.8 V. The figure also shows the amplifier has the maximum PAE of 37% and the PAE is severely degraded with the decreased supply voltage, especially in small supply voltage.
5.2 CASCODE CLASS E PA WITH SELF-BIASED CONTROL CIRCUIT DESIGN
Figure 5.10 Simulation results of the AM-AM and AM-PM distortion.
Figure 5.11 Simulation results of efficiency and output power.
5.2 CASCODE CLASS E PA WITH SELF-BIASED CONTROL CIRCUIT DESIGN
5.2.3 Experimental Results
Fabricated prototypes have been measured by the probe testing. The chip photomicrograph is reported in Figure 5.12. Total die area is 1.6 mm². Figure 5.13 shows the PA measurement setup. The expected gate bias voltage of M2 can be achieved when VDD is swept. Figure 5.14 shows the measured characteristics of the AM-AM and AM-PM of the PA. The phase error is reduced down to 5° as VDD is swept from 0.7 V to 1.8 V. A linear voltage relationship is also obtained and there is a small deviation in low supply voltage, from 0 V to 0.3 V. As expected, the AM-AM and AM-PM distortion of the Class-E PA has been compensated by using proposed design technique. The prototype delivers an output power of 12dBm with an input driving power of 6dBm from a 1.8 V supply voltage and. The output power can be regulated by changing the supply voltage of the amplifier. Figure 5.15 shows the measured output power, drain efficiency and power-added efficiency versus VDD. The output power increases proportionally to VDD², varying from -2 dBm to 12 dBm, as VDD is swept from 0.3 V to 1.8 V.
In small supply voltage, the transistors can not be completely on so that the amplifications of the RF signal are not available. Drain efficiencies are 17.8% in VDD of 0.5 V to 1.8 V. As the supply voltage below 0.6 V, the PAE has seriously reductions, whereas the PAE reduces when the output power becomes comparable to the input power. Due to the targeted output power reduced from 16 dBm to 12 dBm, the maximum PAE is reduced to 16.6%. The output power and power gain versus the input power are also reported in Figure 5.16. The PA has the output power of 12 dBm and power gain of 6 dB with an input driving power of 6dBm. When the input driving power is above 7dBm, the power gain of the PA is degraded to 5dB. The result of the output power versus frequency is shown in Figure 5.17. The output power is above 12 dBm in the 2.3 GHz to 2.8 GHz frequency band, leading the power amplifier to operate in a wide frequency band. The maximum PAE in this wide frequency band is 23.5%.
5.2 CASCODE CLASS E PA WITH SELF-BIASED CONTROL CIRCUIT DESIGN
Figure 5.12 Chip photo of Class E amplifier with self-biased control circuit.
Figure 5.13 PA measurement setup.
5.2 CASCODE CLASS E PA WITH SELF-BIASED CONTROL CIRCUIT DESIGN
Figure 5.14 Measured results of the AM-AM and AM-PM distortion.
Figure 5.15 Measured output power, PAE and drain efficiency versus supply voltage.
5.2 CASCODE CLASS E PA WITH SELF-BIASED CONTROL CIRCUIT DESIGN
Figure 5.16 Measured output power and power gain versus input power.
Figure 5.17 Measured output power and PAE versus frequency.
5.2 CASCODE CLASS E PA WITH SELF-BIASED CONTROL CIRCUIT DESIGN
The design proposed here shows that the AM-AM and AM-PM distortion of the cascode Class-E PA has been compensated by a self-biased control circuit without dissipating more power. However, because of the concern of an allowed current capacity on the top metal layer, the aspect sizes of the transistors for efficiency optimization are difficult to achieve. Therefore, the equivalent series resistances of the transistor are large when the transistor is on, so that the reduction on the drain voltage waveform and the output power. Due to the reduction of the output power, the efficiency of the amplifier is also reduced.
5.2.4 Summary
A cascode Class E amplifier with AM-AM and AM-PM compensation has been implemented in CMOS technology process. The proposed compensation technique is realized by the internal auto-biasing control circuit. The measured results have demonstrated that the proposed compensation technique can effectively improve the AM-AM and AM-PM distortion of the Class E amplifier.
5.3 Summary
Designs of the Class E PA and the Class E PA with self-biased control circuit are implemented in CMOS 0.18 µm technology process. All of measured results show that the AM-AM and AM-PM distortion is improved as the Class E has been compensated by proposed technique. The AM-AM and AM-PM characteristic curves are important that they are a linear and a flat response to change in the supply voltage, respectively, in polar modulation. Furthermore, it is also to minimize the level of predistortion needed in polar modulation. The results are summarized in Table 5.1. The comparison result has also been summarized in Table 5.2.
5.3 SUMMARY
Table 5.1 Performance summary.
Table 5.2 Comparison results.
5.3 SUMMARY
Chapter 6
RF/Baseband System Co-verification
The chapter presents the verification of AM-AM and AM-PM distortion in the system level.
The co-verification platform is addressed in Section 6.1. The comparison results are described in Section 6.2.
6.1 RF/Baseband Co-verification Platform
An EER system co-simulation were performed in ADS-Ptolemy using an IEEE 802.11a OFDM-based waveform (36 Mbits/s, 52 carriers, 16-QAM modulation scheme and modulation bandwidth=20 MHz) up-converted to 2.6 GHz frequency band and the simulation platform of an EER is shown in Figure 6.1. In the platform, all of system blocks are ideal equation-based components, except the Class-E power amplifier. In the transmitter part, the modulation signal is up-converted and then amplified through an EER transmitter. In the receiver part, the received signal is down-converted and demodulated by a signal demodulator.
The EVM and constellation performances can be evaluated by sink components such as Error Vector Magnitude Measurement. Furthermore, the EER transmitter shown in Figure 6.2 consists of a delay cell, an envelope detector, a limiter, an envelope amplifier and the Class E power amplifier. The power amplifier is driven by the voltage of approximately 1.2 V peak-to-peak swing. The compensated delay mismatch between the envelope path and the phase path is estimated by 2.8 ns for 40 dBc IMD (intermodulation distortion) [65]. The histogram of envelope voltage in Figure 6.3 shows that 93% of envelope voltages are in the range from 0.5 V to 1.8 V with a mean voltage of 1 V. It was obtained by adjusting the gain
of the envelope amplifier.
Figure 6.1 The system co-verification platform.
Figure 6.2 EER transmitter.
Figure 6.3 Histogram of the envelope voltage.
6.1 RF/BASEBAND CO-VERIFICATION PLATFORM
6.2 Co-verification Results
Designs of the Class-E with and without compensation have been simulated, respectively, in the EER co-simulation platform. The simulated results of received constellation have been shown in Figure 6.4. For the PA without compensation, the received constellation shown in Figure 6.4(a) reveals that the PA distortion causes the received symbol to move closer to an additional constellation point than the one transmitted and therefore the EVM is -17dB, -19 dB for system specification. For the PA with compensation, the received constellation shown in Figure 6.4(b) is closer to the transmitted constellation point and therefore the EVM is -19.2 dB. Furthermore, for the signal source with 64-QAM modulation scheme, the PA with compensation can also improve the system EVM from -21 dB to -25.1 dB. All of results have been summarized on Table 6.1. It shows that the proposed methodology can effectively compensate the AM-AM and AM-PM distortion of the Class E power amplifiers.
Figure 6.4 received constellations (a) PA without compensation, and (b) PA with compensation.
6.2 CO-VERIFICATION RESULTS
Table 6.1 Performance summary.
6.3 Summary
The influence of the AM-AM and AM-PM characteristic on system performance has been discussed in this chapter. A system platform of EER with OFDM-based signal is constructed to demonstrate the PA distortion effect on EVM performance. When the PA distortion is compensated, the system EVM of an EER with the OFDM-based signal has been improved from -17 dB to -19.2 dB for 16-QAM modulation scheme, from -21 dB to -25.1 dB for 64-QAM modulation scheme.
6.3 SUMMARY
Chapter 7
Efficiency Enhancement with Suspended Inductor
The internal inductors have the advantages of low cost and saving area for manufacturing.
However, the low quality factor of internal inductors results in large resistive losses so that the PA efficiency is degraded. In the chapter, we presented a developed CMOS MEMS process and multi-metal layer suspended inductors to improve the quality factor of inductors for increasing the PA efficiency. In Section 7.1, the efficiency analysis of power amplifiers has been presented, in which the impact of low quality factor of inductors on efficiency is introduced. Section 7.2 describes the flow of CMOS MEMS process and multi-metal layer suspended inductors. The simulation performance of the Class E power amplifier with multi-metal layer suspended inductors has been reported in Section 7.3.
7.1 Efficiency Analysis
According to the well-known Class-E conditions as stated by Sokal [53], inductors used in the amplifiers are assumed ideal to have an infinite quality factor (Q) so that the efficiency of 100% is achieved. However, a large inductance and an inductor with high quality factor are difficult to achieve in silicon substrate. Moreover, due to the low Q-value of internal inductors, the PA has more power dissipations so that has degradations on efficiency.
For considering inductors parasitic losses of the PA shown in Figure 2.3, we will refer to the equivalent PA circuit reported in Figure 7.1, where parasitic elements of inductors are
dissipated through the conductive channel. A simplified expression for the power loss due to
We assume all the inductors having the same Q-value, i.e., the parasitic series resistance is Rx = ωoLx/Q for the two inductors Lck, Lt. Considering resistors Rt-RL realize a voltage divider, the power loss due to Rt normalized to the output power is given by Equation (7.2).
L
Figure 7.1 Schematic of basic Class-E amplifier with equivalent series resistances.
7.1 EFFICIENCY ANALYSIS
Figure 7.2 Drain efficiency versus Q-value of inductors Qck and Qt.
If a dc current is assumed through Lck, the calculation of its power loss contribution is straightforward. The normalized power loss is then given by
L
According to Equations (7.1)-(7.3), the calculated efficiency of power amplifiers can be expressed as η=1/(1+∑i(PLOSS/POUT)|i). To validate the above analysis, the parameter values on Table (2.2) are introduced: Ron= 5 Ω, Lt= 2.6 nH and Lck= 2 nH. The result of calculated efficiency versus the Q-value of Lck and Lt has been reported in Figure 7.2. In Figure 7.2, the curves marked as Qck and Qt denote the variable Q-value of Lck and Lt, respectively, and the
7.2 Suspended Inductor Design
7.2.1 CMOS MEMS Process
The fabrication for the suspended inductor is similar to any IC fabrication process. In this process, etching technology for releasing the oxide and silicon substrate was performed. The process flow has been shown in Figure 7.3. The first step is to deposit the metal layer (Hardmask), which is used to protect the top metal layer of the microstructure during the etching step. The second step is to remove the oxide layer by the anisotropic etching. After removing the oxide layer, silicon substrate is released by an isotropic etching process. The final step is to remove the Hardmask layer after the previous processing steps have been completed. After fabrication, the inductors will be suspended by 40 µm from the top metal layer to silicon substrate.
Figure 7.4 shows the photograph of fabricated suspended inductor. It shows the developed CMOS MEMS is allowed to fabricate CMOS-compatible suspended inductors.
Figure 7.3 CMOS MEMS fabrication process.
7.2 SUSPENDED INDUCTOR DESIGN
Figure 7.4 Fabricated suspended inductor photograph.
7.2.2 HFSS Simulation Model
The micrograph of a single-metal layer suspended inductor and its cross section view have been shown in Figure 7.5. This inductor has 7 turns of spiral coil on air suspension and 2 µm thick of the top metal layer. For perspective of circuit design, an equivalent model of suspended inductor is required. HFSS (high frequency structural simulator) is a commercial finite element method (FEM) solver for electromagnetic structures. The FEM is a numerical technique for finding approximate solutions of partial differential equations (PDE). HFSS uses 3-D FEM and 3-D boundary conditions. The solid models have been obtained from the 2-D layout. The measured and simulated results of this inductor are plotted in Figure 7.6. The comparison result shows that HFSS has good prediction on the characteristics of proposed suspended inductors. Therefore, the equivalent model of suspended inductors can be extracted from HFSS for requirements of circuit design.
7.2 SUSPENDED INDUCTOR DESIGN
Figure 7.5 Micrograph and cross section view of the suspended inductor.
Figure 7.6 Simulated and Measured results of the suspended inductor.
7.2.3 Multi-Metal Layer Suspended Inductor
The suspended inductors can have an improved Q-value due to the reduction of power losses from the silicon substrate. However, it also moves the resonant frequency of Q-value to higher frequency band. In this literature, the stacked-metal layer topology of suspended inductors has been proposed. When stacking two or more meal layers, the thickened metal can
7.2 SUSPENDED INDUCTOR DESIGN
not only reduce the resistive loss but also shift the resonant frequency down to lower frequency band to desired operating frequency. A prototype of suspended inductor having two-metal layer (M5/M6) and the three-metal layer (M4/M5/M6) are performed and the cross-section view is shown in Figure 7.7. The metal layers for signal transmission are stacked to optimize the Q-value and simulated results by HFSS have been plotted in Figure 7.8. The result shows that the Q-value is increased and the frequency of maximum Q-value is also shifted to the higher frequency band by the suspended structure. On the other hand, the frequency of maximum Q-value can be shifted to the lower frequency band by the stacked-metal structure. Therefore, for lower desired operating frequency, the stacked-metal layer suspended inductor effectively enhances the Q-value for efficiency improvement. In Figure 7.8, the slope of curve M654 is nearly the same as the slope of other curves. However, the Q-value of curve M654 at the dc frequency is different from others due to the different shunt capacitance of inductors and the boundary definition of simulator at the dc frequency.
For considering the impact of inductors on efficiency, the inductors having different metal thickness are performed. The simulated Q-value at 2.6 GHz by HFSS is reported in Figure 7.9. The inductor M6(Si) with 20-µm metal width has a typical Q-value of 9.5 in standard CMOS process. For single-metal layer suspended inductor M6, the Q-value is 9.7.
When the suspended inductor stacked the three top-metal layers, the Q-value of 12 is achieved.
The inductors Lck with more stacked-metal layer have a degraded Q-value due to the skin effect from the exceeding metal thickness.
Figure 7.7 Cross-section view of suspended inductor (a) two-metal layer, (b) three-metal layer.
7.2 SUSPENDED INDUCTOR DESIGN
Figure 7.8 Q-value of CMOS inductor and suspended inductor.
Figure 7.9 The Q-value of inductors with different metal thickness.
7.2 SUSPENDED INDUCTOR DESIGN
7.3 Simulation Results
The dc-feed inductor and the inductor of output matching network in Class E power amplifier proposed in Chapter 3 is implemented with multi-metal layer suspended inductors as shown in Figure 7.10. The simulation model of suspended inductors has been created by HFSS. The amplifier intends to demonstrate that the PA efficiency could effectively be enhanced with auto-biasing technique and suspended inductors. The comparison of simulation results will be reported as followings.
The dc current and output power of amplifiers are plotted in Figure 7.11. The output power has no change when proposed compensation technique and suspended inductors have been performed. The dc current still has no change if only suspended inductors are performed.
Drain efficiency of the amplifiers versus the supply voltage has been plotted in Figure 7.12. It is apparently that the PA with the three-metal (M654) layer suspended inductors has the maximum efficiency performance. When the auto-biasing cascode Class-E amplifier with the three-metal layer (M654) suspended inductors, the efficiency can have the maximum improvement of the efficiency of 17% at the supply of 0.65 V. The result has demonstrated that the Class-E power amplifier with proposed compensation technique and suspended inductors effectively improves the power efficiency.
Figure 7.10 Cascode Class-E PA with suspended inductors.
7.3 SIMULATION RESULTS
Figure 7.11 Comparison results of dc current and output power versus supply voltage.
Figure 7.12 Comparison results of drain efficiency versus supply voltage.
7.3 SIMULATION RESULTS
7.4 Summary
The analysis for efficiency improvement of the CMOS Class-E PA with suspended inductors has been presented. A process which can fabricate the suspended inductors is also introduced in this work. Furthermore, for increasing Q-value, the stacked-metal layer suspended inductors have been presented. Prototypes of inductors have been designed to demonstrate that the stacked-metal layer inductors in CMOS MEMS process can reduce the substrate loss and resistive loss for improving the Q-value of inductors. It has shown that the PA efficiency can be improved by the stacked-metal layer MEMS inductors and also provides a design methodology for improving the PA efficiency by optimizing the Q-value of fully integrated inductors. Finally, with proposed compensation technique and suspended inductors, the Class E power amplifier can have the maximum efficiency enhancement.
7.4 SUMMARY
Chapter 8 Conclusions
The dissertation has presented the design of CMOS cascode Class E power amplifier with AM-AM and AM-PM compensation. The techniques presented in earlier chapters have enabled the implementation of a CMOS cascode Class E power amplifier in a 0.18 µm technology. To conclude, we briefly summarize the key contributions presented in precious chapters.
8.1 Summary
The design methodology of conventional common source Class E power amplifiers has been described in Chapter 2. For practical considerations of integration and reliability, the design requirements of cascode Class E power amplifier with small dc-feed inductance have been analyzed.
Chapter 3 has presented a conventional cascode Class E power amplifier in CMOS 0.18 µm technology. As cascode Class E power amplifiers in supply modulation, the reason for producing the envelope deviation and the phase error at the RF output signal is described.
Chapter 3 has presented a conventional cascode Class E power amplifier in CMOS 0.18 µm technology. As cascode Class E power amplifiers in supply modulation, the reason for producing the envelope deviation and the phase error at the RF output signal is described.