6 RF/Baseband System Co-verification 5
6.2 Co-verification Results
Designs of the Class-E with and without compensation have been simulated, respectively, in the EER co-simulation platform. The simulated results of received constellation have been shown in Figure 6.4. For the PA without compensation, the received constellation shown in Figure 6.4(a) reveals that the PA distortion causes the received symbol to move closer to an additional constellation point than the one transmitted and therefore the EVM is -17dB, -19 dB for system specification. For the PA with compensation, the received constellation shown in Figure 6.4(b) is closer to the transmitted constellation point and therefore the EVM is -19.2 dB. Furthermore, for the signal source with 64-QAM modulation scheme, the PA with compensation can also improve the system EVM from -21 dB to -25.1 dB. All of results have been summarized on Table 6.1. It shows that the proposed methodology can effectively compensate the AM-AM and AM-PM distortion of the Class E power amplifiers.
Figure 6.4 received constellations (a) PA without compensation, and (b) PA with compensation.
6.2 CO-VERIFICATION RESULTS
Table 6.1 Performance summary.
6.3 Summary
The influence of the AM-AM and AM-PM characteristic on system performance has been discussed in this chapter. A system platform of EER with OFDM-based signal is constructed to demonstrate the PA distortion effect on EVM performance. When the PA distortion is compensated, the system EVM of an EER with the OFDM-based signal has been improved from -17 dB to -19.2 dB for 16-QAM modulation scheme, from -21 dB to -25.1 dB for 64-QAM modulation scheme.
6.3 SUMMARY
Chapter 7
Efficiency Enhancement with Suspended Inductor
The internal inductors have the advantages of low cost and saving area for manufacturing.
However, the low quality factor of internal inductors results in large resistive losses so that the PA efficiency is degraded. In the chapter, we presented a developed CMOS MEMS process and multi-metal layer suspended inductors to improve the quality factor of inductors for increasing the PA efficiency. In Section 7.1, the efficiency analysis of power amplifiers has been presented, in which the impact of low quality factor of inductors on efficiency is introduced. Section 7.2 describes the flow of CMOS MEMS process and multi-metal layer suspended inductors. The simulation performance of the Class E power amplifier with multi-metal layer suspended inductors has been reported in Section 7.3.
7.1 Efficiency Analysis
According to the well-known Class-E conditions as stated by Sokal [53], inductors used in the amplifiers are assumed ideal to have an infinite quality factor (Q) so that the efficiency of 100% is achieved. However, a large inductance and an inductor with high quality factor are difficult to achieve in silicon substrate. Moreover, due to the low Q-value of internal inductors, the PA has more power dissipations so that has degradations on efficiency.
For considering inductors parasitic losses of the PA shown in Figure 2.3, we will refer to the equivalent PA circuit reported in Figure 7.1, where parasitic elements of inductors are
dissipated through the conductive channel. A simplified expression for the power loss due to
We assume all the inductors having the same Q-value, i.e., the parasitic series resistance is Rx = ωoLx/Q for the two inductors Lck, Lt. Considering resistors Rt-RL realize a voltage divider, the power loss due to Rt normalized to the output power is given by Equation (7.2).
L
Figure 7.1 Schematic of basic Class-E amplifier with equivalent series resistances.
7.1 EFFICIENCY ANALYSIS
Figure 7.2 Drain efficiency versus Q-value of inductors Qck and Qt.
If a dc current is assumed through Lck, the calculation of its power loss contribution is straightforward. The normalized power loss is then given by
L
According to Equations (7.1)-(7.3), the calculated efficiency of power amplifiers can be expressed as η=1/(1+∑i(PLOSS/POUT)|i). To validate the above analysis, the parameter values on Table (2.2) are introduced: Ron= 5 Ω, Lt= 2.6 nH and Lck= 2 nH. The result of calculated efficiency versus the Q-value of Lck and Lt has been reported in Figure 7.2. In Figure 7.2, the curves marked as Qck and Qt denote the variable Q-value of Lck and Lt, respectively, and the
7.2 Suspended Inductor Design
7.2.1 CMOS MEMS Process
The fabrication for the suspended inductor is similar to any IC fabrication process. In this process, etching technology for releasing the oxide and silicon substrate was performed. The process flow has been shown in Figure 7.3. The first step is to deposit the metal layer (Hardmask), which is used to protect the top metal layer of the microstructure during the etching step. The second step is to remove the oxide layer by the anisotropic etching. After removing the oxide layer, silicon substrate is released by an isotropic etching process. The final step is to remove the Hardmask layer after the previous processing steps have been completed. After fabrication, the inductors will be suspended by 40 µm from the top metal layer to silicon substrate.
Figure 7.4 shows the photograph of fabricated suspended inductor. It shows the developed CMOS MEMS is allowed to fabricate CMOS-compatible suspended inductors.
Figure 7.3 CMOS MEMS fabrication process.
7.2 SUSPENDED INDUCTOR DESIGN
Figure 7.4 Fabricated suspended inductor photograph.
7.2.2 HFSS Simulation Model
The micrograph of a single-metal layer suspended inductor and its cross section view have been shown in Figure 7.5. This inductor has 7 turns of spiral coil on air suspension and 2 µm thick of the top metal layer. For perspective of circuit design, an equivalent model of suspended inductor is required. HFSS (high frequency structural simulator) is a commercial finite element method (FEM) solver for electromagnetic structures. The FEM is a numerical technique for finding approximate solutions of partial differential equations (PDE). HFSS uses 3-D FEM and 3-D boundary conditions. The solid models have been obtained from the 2-D layout. The measured and simulated results of this inductor are plotted in Figure 7.6. The comparison result shows that HFSS has good prediction on the characteristics of proposed suspended inductors. Therefore, the equivalent model of suspended inductors can be extracted from HFSS for requirements of circuit design.
7.2 SUSPENDED INDUCTOR DESIGN
Figure 7.5 Micrograph and cross section view of the suspended inductor.
Figure 7.6 Simulated and Measured results of the suspended inductor.
7.2.3 Multi-Metal Layer Suspended Inductor
The suspended inductors can have an improved Q-value due to the reduction of power losses from the silicon substrate. However, it also moves the resonant frequency of Q-value to higher frequency band. In this literature, the stacked-metal layer topology of suspended inductors has been proposed. When stacking two or more meal layers, the thickened metal can
7.2 SUSPENDED INDUCTOR DESIGN
not only reduce the resistive loss but also shift the resonant frequency down to lower frequency band to desired operating frequency. A prototype of suspended inductor having two-metal layer (M5/M6) and the three-metal layer (M4/M5/M6) are performed and the cross-section view is shown in Figure 7.7. The metal layers for signal transmission are stacked to optimize the Q-value and simulated results by HFSS have been plotted in Figure 7.8. The result shows that the Q-value is increased and the frequency of maximum Q-value is also shifted to the higher frequency band by the suspended structure. On the other hand, the frequency of maximum Q-value can be shifted to the lower frequency band by the stacked-metal structure. Therefore, for lower desired operating frequency, the stacked-metal layer suspended inductor effectively enhances the Q-value for efficiency improvement. In Figure 7.8, the slope of curve M654 is nearly the same as the slope of other curves. However, the Q-value of curve M654 at the dc frequency is different from others due to the different shunt capacitance of inductors and the boundary definition of simulator at the dc frequency.
For considering the impact of inductors on efficiency, the inductors having different metal thickness are performed. The simulated Q-value at 2.6 GHz by HFSS is reported in Figure 7.9. The inductor M6(Si) with 20-µm metal width has a typical Q-value of 9.5 in standard CMOS process. For single-metal layer suspended inductor M6, the Q-value is 9.7.
When the suspended inductor stacked the three top-metal layers, the Q-value of 12 is achieved.
The inductors Lck with more stacked-metal layer have a degraded Q-value due to the skin effect from the exceeding metal thickness.
Figure 7.7 Cross-section view of suspended inductor (a) two-metal layer, (b) three-metal layer.
7.2 SUSPENDED INDUCTOR DESIGN
Figure 7.8 Q-value of CMOS inductor and suspended inductor.
Figure 7.9 The Q-value of inductors with different metal thickness.
7.2 SUSPENDED INDUCTOR DESIGN
7.3 Simulation Results
The dc-feed inductor and the inductor of output matching network in Class E power amplifier proposed in Chapter 3 is implemented with multi-metal layer suspended inductors as shown in Figure 7.10. The simulation model of suspended inductors has been created by HFSS. The amplifier intends to demonstrate that the PA efficiency could effectively be enhanced with auto-biasing technique and suspended inductors. The comparison of simulation results will be reported as followings.
The dc current and output power of amplifiers are plotted in Figure 7.11. The output power has no change when proposed compensation technique and suspended inductors have been performed. The dc current still has no change if only suspended inductors are performed.
Drain efficiency of the amplifiers versus the supply voltage has been plotted in Figure 7.12. It is apparently that the PA with the three-metal (M654) layer suspended inductors has the maximum efficiency performance. When the auto-biasing cascode Class-E amplifier with the three-metal layer (M654) suspended inductors, the efficiency can have the maximum improvement of the efficiency of 17% at the supply of 0.65 V. The result has demonstrated that the Class-E power amplifier with proposed compensation technique and suspended inductors effectively improves the power efficiency.
Figure 7.10 Cascode Class-E PA with suspended inductors.
7.3 SIMULATION RESULTS
Figure 7.11 Comparison results of dc current and output power versus supply voltage.
Figure 7.12 Comparison results of drain efficiency versus supply voltage.
7.3 SIMULATION RESULTS
7.4 Summary
The analysis for efficiency improvement of the CMOS Class-E PA with suspended inductors has been presented. A process which can fabricate the suspended inductors is also introduced in this work. Furthermore, for increasing Q-value, the stacked-metal layer suspended inductors have been presented. Prototypes of inductors have been designed to demonstrate that the stacked-metal layer inductors in CMOS MEMS process can reduce the substrate loss and resistive loss for improving the Q-value of inductors. It has shown that the PA efficiency can be improved by the stacked-metal layer MEMS inductors and also provides a design methodology for improving the PA efficiency by optimizing the Q-value of fully integrated inductors. Finally, with proposed compensation technique and suspended inductors, the Class E power amplifier can have the maximum efficiency enhancement.
7.4 SUMMARY
Chapter 8 Conclusions
The dissertation has presented the design of CMOS cascode Class E power amplifier with AM-AM and AM-PM compensation. The techniques presented in earlier chapters have enabled the implementation of a CMOS cascode Class E power amplifier in a 0.18 µm technology. To conclude, we briefly summarize the key contributions presented in precious chapters.
8.1 Summary
The design methodology of conventional common source Class E power amplifiers has been described in Chapter 2. For practical considerations of integration and reliability, the design requirements of cascode Class E power amplifier with small dc-feed inductance have been analyzed.
Chapter 3 has presented a conventional cascode Class E power amplifier in CMOS 0.18 µm technology. As cascode Class E power amplifiers in supply modulation, the reason for producing the envelope deviation and the phase error at the RF output signal is described.
More detailed analyses including the current/voltage curves and impedance variations of transistors are also introduced in this chapter.
A design technique, which modulates the gate bias voltage of the cascode transistor to operate the transistor as a resistance, to compensate the AM-AM and AM-PM distortion of the cascode Class E amplifier has been presented in Chapter 4. The efficiency performance of the amplifier is also improved as the distortion has been compensated.
The design of cascode Class E power amplifier implemented in CMOS 0.18 µm technology has been presented in Chapter 5. The experimental results demonstrate the phase shift of the output signal from 30˚ to 6˚ when VDD is 0.4 V to 1.8 V. The design of cascode Class E power amplifier with self-biased control circuit implemented in CMOS 0.18 µm technology demonstrates the Class E power amplifier with compensated AM-AM and AM-PM distortion. The experimental result shows the phase error reduced down to 5° as VDD is swept from 0.7 V to 1.8 V. The output power is 12 dBm from a 1.8 V supply. Drain efficiency and PAE is18.7% and 16.6%, respectively.
For the RF/baseband co-verification, Chapter 6 presents the co-verification platform. The case study of a 2.6 GHz EER transmitter with OFDM-based signal source has been presented to demonstrate the feasibility of the AM-AM and AM-PM compensation.
A developed CMOS MEMS process and stacked metal layer suspended inductors have been presented in Chapter 7 to demonstrate the improved PA efficiency due to the increased quality factor of internal inductors. The amplifier has the maximum efficiency improvement of 17%.
8.2 Recommendations for Future Work
The determination of transistor size is constrained by the current density of internal inductors.
The optimization of MOS size and inductor Q-value could help to enhance the circuit performance such as output power and efficiency. In addition, it should be feasible to improve the efficiency at high power level as the amplifier was compensated. Moreover, the characteristic of AM-AM and AM-PM curves could be optimized with the elimination of process variations.
8 CONCLUSIONS
Appendix A
Analysis of Ideal Class E PA with Finite DC-Feed Inductor
One of the first attempts was made to study finite dc-feed inductor in [60]. Some other related studies are included in [68]-[69]. All these researches have recommended that procedure of obtaining final circuit component values is either long, complex and iterative, and is difficult to provide a direct insight into the circuit design, or is too simplistic and not exactly.
Practically, the design of the Class E PA with finite dc-feed inductor is a transcendent problem from the mathematical point of view. Therefore, the designer needs to iteratively figure out the systm of equations for a certain set of input parameters to gain the final circuit component values. If any of the input parameters is changed, the calculation must be repeated from the beginning. Thus, it is a tedious and extremely impractical procedure. In [70] an approach has been proposed to alleviate the problem. The system of transcendent equations is numerically solved for a certain number of discrete points of an input parameter, and the obtained results are interpolated by the Lagrange polynomial. The polynomial interpolation provides adequate accuracy and can be used for any value of the input parameter on that segment, if it performs with enough density of points on the segment of interest. In other words, it obtains clear and directly usable design equations for the Class E power amplifier.
The well-known design equations have been many times derived in the literature, and they are given by
out
where VDD and Pout are the supply voltage and the desired output power, respectively, and the load resistance R, the shunt susceptance B and the excessive reactance X. The equations are based on the Lck is an RF choke with large inductance. But in case of the Class E amplifier with finite dc-feed inductor, the equations don’t hold anymore. At the beginning of the design procedure, the designer could choose a value of inductance for the finite dc-feed inductor.
Therefore, the reactance of the inductor is known and can be given by
ck
dc
L
X = ω
(A.4)On the other hand, an ideal Class E amplifier provides a 100% dc-to-RF efficiency.
Therefore, the dc resistance that the circuit presents to the supply source is also known from the PA specifications, and is simply given as
out DD
dc
P
R V
=
2 (A.5)Depending on the value of Xdc/Rdc, the circuit parameters R, B and X will change their value from the given equations for the RF choke based Class E power amplifier. The three parameters have calculated by numerically solving the transcendent circuit equations for a number of different values of Xdc/Rdc. The results of these calculations are plotted in Figure A.1. In Figure A.1, the variations of the elements R, B and X is plotted as a function of Xdc/Rdc. However, the plots are not continuous functions and they are discrete character.
In order to obtain explicit design equations for the Class E PA component values, the Lagrange polynomial interpolation of the numerically obtained results is used. Finally, the
new equations for Class E power amplifier with finite dc-feed inductor are presented in the
Figure A.1 Effect of the finite dc-feed inductance on the Class E circuit elements.
Design equations (A.6)-(A.11) are explicit, relatively simple and can be used for any value of z=Xdc/Rdc within the corresponding segment. But outside these segments, they are not valid.
The utilization of a finite dc-feed inductor has several major benefits. First, it results in a higher load resistance in comparison to the case of RF choke. This effect makes the design of low-loss matching networks easier, since the designer typically needs to transform a standard 50 Ohm termination to the load resistance of several Ohms. Furthermore, the excessive inductance X is also lower, and the shunt susceptance B is increased. This increase of the shunt susceptance is particularly useful, as it extends the maximum frequency limitation of the device imposed by its output capacitance.
Appendix B
Common Source Class E PA with Stacked Resistance
In this work, we present that when the cascode transistor is operated as a resistance alike, the AM-AM and AM-PM distortion is improved. Therefore, of the Class E amplifier the cascode transistor replaced with a resistance has been shown in Figure B.1. With the same operating conditions the simulation results of the common source Class E with stacked resistance are obtained. The simulated result compared with that of the cascode Class E with compensation is shown in Figure B.2. It demonstrates that both of two amplifiers have good agreement on the AM-AM and AM-PM characteristic. However, the resistance captures more voltage headrooms so that the output power of the amplifier is degraded as shown in Figure B.3.
There has a 3-dB reduction to the output power and the power gain of the amplifier. Even having smaller current consumptions as shown in Figure B.4, the efficiency is less than that of the cascode Class E owing to the severely degraded output power.
Figure B.1 Common source Class E with stacked resistance.
Figure B.2 Comparison of AM-AM and AM-PM distortion.
Figure B.3 Comparison of power gain and output power.
Figure B.4 Comparison of drain efficiency and dc current.
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