國 立 交 通 大 學
電子工程學系電子研究所
博 士 論 文
具線性度補償之
互補金氧半層疊E類功率放大器設計
CMOS Cascode Class E Power Amplifier Design with
Linearity Compensation
研 究 生 ： 鄒 文 安
指導教授 ： 溫 瓌 岸
具線性度補償之
互補金氧半層疊 E 類功率放大器設計
CMOS Cascode Class E Power Amplifier Design with
Linearity Compensation
研 究 生：鄒文安
Student：Wen-An Tsou
指導教授：溫瓌岸 博士
Advisor：Dr. Kuei-Ann Wen
國 立 交 通 大 學
電子工程學系 電子研究所
博 士 論 文
A Dissertation
Submitted to Department of Electronics Engineering and Institute of Electronics
College of Electrical and Computer Science National Chiao Tung University in partial Fulfillment of the Requirements
for the Degree of Doctor of Philosophy
in
Electronics Engineering
May 2010
Hsinchu, Taiwan, Republic of China
具線性度補償之互補金氧半層疊 E 類功率放大器設計
學生：鄒文安 指導教授：溫瓌岸 博士
國立交通大學電子工程學系 電子研究所
摘
要
本論文針對可應用於極座標調變傳送機之互補式金氧半層疊 E 類功率放大器提出 AM-AM 和 AM-PM 失真補償之設計。本文探討之 E 類功率放大器為使用小電感值 dc-feed 之層疊式架構，主要考量為互補式金氧半製程中，大電感值電感不易取得以及主動元件 的低崩潰電壓特性。而當層疊 E 類功率放大器應用於極座標調變（亦即調變放大器之供 給電壓）時，在放大器的輸出訊號上會產生 AM-AM 和 AM-PM 失真特性。 本文除探討 AM-AM 和 AM-PM 失真產生之原因，並且提出一失真補償技術 ─ 藉由改 變層疊電晶體之閘極偏壓，使電晶體操作如一電阻性元件，進而改進放大器之非線性效 應。由設計的 2.6 GHz 層疊 E 類功率放大器實驗結果顯示，經由外部改變偏壓的方式， 在供給電壓大於 0.6 伏特時，補償後之輸出訊號相位偏移可從 30 度降低到 6 度，輸出 訊號振幅相對供給電壓可成線性變化。而另一 2.6 GHz 層疊 E 類功率放大器整合自我偏 壓控制電路設計之實驗結果顯示，輸出訊號振幅與供給電壓成 1V/V 之線性關係外，並 有 5 度輸出訊號相位的偏移；在 1.8 伏特供給電壓和輸入功率為 6 dBm 下，輸出功率為 12 dBm，汲極效率為 17.8％，PAE 為 16.6％。實驗結果顯示，所提出的補償技術可有效 的改進功率放大器之 AM-AM 和 AM-PM 失真。 並且利用射頻/基頻共同驗證方法，輸入為一 OFDM 訊號時，放大器經過補償後，模 擬結果顯示，在 16QAM 的調變下，EVM 可從-17dB 到-19.2dB；在 64QAM 的調變下，EVM 可從-21dB 到-25.1dB。最後針對矽基底電感的低品質因素造成放大器效率的降低，因此 整合多層金屬層之懸空式電感於放大器匹配電路中，模擬結果顯示可使放大器有最大 17%的效率提昇。
CMOS Cascode Class E Power Amplifier Design with
Linearity Compensation
Student：Wen-An Tsou
Advisors：Dr. Kuei-Ann Wen
Department of Electronics Engineering and
Institute of Elecronics
National Chiao-Tung University
ABSTRACT
The dissertation presents the design of the cascode Class E power amplifier with AM-AM and AM-PM compensation for polar applications. For integration and reliability analysis in CMOS process, the Class E designed with small dc-feed and using cascode topology has been presented. When the Class E is in supply modulation, the AM-AM and AM-PM distortion is introduced at the RF output signal.
This work not only analyzes the cause of the distortion but also presents a compensation technique. When modulating the gate bias voltage of the cascode transistor, the transistor operates as a resistance alike to improve the distortion of the amplifier. The experimental result of proposed 2.6 GHz cascode Class E power amplifier shows that when the PA is compensated the AM-PM is reduced from 30° to 6° and the output envelope voltage is linearly to supply voltage in VDD > 0.6 V. The experimental result of the 2.6 GHz cascode
Class E power amplifier with self-biased control circuit shows that the voltage slope of AM-AM is 1 V/V and the phase error of AM-PM is 5°. The PA has a output power of 12 dBm, drain efficiency of 17.8% and PAE of 16.6% from a 1.8 V supply and an input driving of 6 dBm. Therefore, the experimental results demonstrate the proposed compensation technique can effectively improve the AM-AM and AM-PM distortion of the cascode Class E amplifiers.
In addition, the simulation results of the RF/baseband co-verification platform with OFDM-based signal source show that the EVM is improved from -17 dB to -19.2 dB at 16QAM modulation and from -21 dB to -25.1 dB at 64QAM modulation. Finally, due to the low quality factor of silicon-based inductor causing the degradation on PA efficiency, the PA with multi-metal layer suspended inductors has been presented. The simulation result shows that the PA can have a maximum efficiency improvement of 17%.
誌 謝
這篇論文的完成需要感謝許多的同學、同事與朋友，由於他們時時刻刻的支持與鼓 勵，才讓我得以完成博士論文。 首先要感謝的是指導教授溫瓌岸老師。在這幾年的研究生涯中，因為老師的指導與 教誨，使我在學術研究與待人處事上，可以不斷的成長；也由於老師提供自由的研究空 間，並賦予了豐富的資源和環境，使我能夠隨心所欲的進行研究，激發研究的樂趣。其 次要特別感謝學位考試委員們在百忙之中抽空前來給予論文指導；承蒙口試委員們的指 導與建議，才能讓本論文的內容得以更加完備。 很榮幸能成為無線通訊技術實驗室的一員，參與 RF 電路的研究工作。感謝溫文燊 學長在論文研究所給予的批評與討論，以及實驗室的團隊─周美芬學姊、彭嘉笙學長、 陳哲生學長、莊源欣學長等在研究上的協助與陪伴。感謝實驗室眾多的學弟們，直接或 間接所給予的協助。 感謝實驗室的助理─卉蓁、苑佳、淑怡、宛君、智伶，在研究過程上的協助，並不 時給予我鼓勵；特別是苑佳，總是在我遇到挫折時，給予我信心與勉勵。也感謝女友亭 菱的支持與鼓勵，並時常給予關懷，讓我得以持續努力、堅持下去。 最後感謝我的每一個親人，感謝父母親在整個求學生涯的幫助，總是大力的支持我 所做的決定，感謝姊姊在我遇到挫折時，總能給我鼓勵，讓我能夠繼續前進與追求未來 目標；在研究過程中難免遇到挫折，因為家人的鼓勵，讓我重拾信心全力以赴，完成學 業。謹將本論文獻給我最親愛的家人。 鄒文安 99 年 5 月Contents
摘要 摘要 摘要 摘要 i Abstract ii 誌謝 誌謝 誌謝 誌謝 iv Contents v List of Figures vii List of Tables x 1 Introduction 1 1.1 Motivation --- 21.2 Organization --- 4
2 Design Considerations of Class E Power Amplifiers 6 2.1 Common-Source Class E Power Amplifier --- 6
2.1.1 Design Principles --- 7
2.1.2 Design Equations --- 9
2.1.3 Power Control --- 13
2.1.4 Practical Considerations --- 14
2.1.5 Finite DC-Feed Inductor --- 15
2.2 Cascode-Based Topology --- 17
2.3 Summary --- 19
3 Design Considerations of Cascode Class E Power Amplifiers 20 3.1 Operation Waveform Analysis --- 20
3.2 Physical Analysis of AM-AM and AM-PM Distortion--- 22
3.2.1 Device Operation --- 23
3.2.2 I/V Curve--- 25
3.2.3 Impedance Variation--- 27
3.3 Summary --- 31
4 Innovative Linearity Compensation Technique 32 4.1 Improved AM-AM and AM-PM--- 32
4.2 Efficiency Improvement --- 36
4.3 Summary --- 39
5 Circuit Implementation and Experimental Results 40 5.1 CMOS Cascode Class E PA Design --- 40
5.1.1 Circuit Design --- 40
5.1.2 Simulation Results--- 42
5.1.3 Experimental Results--- 44
5.1.4 Summary --- 47
5.2 Cascode Class E PA with Self-Biased Control Circuit Design --- 47
5.2.1 Circuit Design --- 47
5.2.2 Simulation Results--- 48
5.2.3 Experimental Results--- 50
5.2.4 Summary --- 54
5.3 Summary --- 54
6 RF/Baseband System Co-verification 56 6.1 RF/Baseband Co-verification Platform --- 56
6.2 Co-verification Results--- 58
6.3 Summary --- 59
7 Efficiency Enhancement with Suspended Inductor 60 7.1 Efficiency Analysis --- 60
7.2 Suspended Inductor Design --- 63
7.2.1 CMOS MEMS Process--- 63
7.2.2 HFSS Simulation Model --- 64
7.2.3 Multi-Metal Layer Suspended Inductor --- 65
7.3 Simulation Results --- 68
7.4 Summary --- 70
8 Conclusions 71 8.1 Summary --- 71
8.2 Recommendations for Future Work --- 72
Appendix A Analysis of Ideal Class E PA with Finite DC-Feed Inductor 73
Appendix B Common Source Class E PA with Stacked Resistance 77
Bibliography 80
List of Figures
Figure 1.1 Cutting edge architecture of transmitters 2 Figure 1.2 Envelope elimination and restoration (EER) 3 Figure 1.3 Polar transmitters 3 Figure 1.4 Envelope tracking transmitters 3 Figure 1.5 Technologies for linearity improvement 4 Figure 2.1 Conceptual “target” waveforms in high efficiency power amplifiers 8 Figure 2.2 Schematic of common-source Class E power amplifier 8 Figure 2.3 The Class E configuration 10 Figure 2.4 Switching voltage and switching current waveforms 11 Figure 2.5 Current waveform of Id and Ic 12
Figure 2.6 Output voltage and output current waveform 12 Figure 2.7 Constant efficiency over variable supply voltage 14 Figure 2.8 Switching voltage and switching current waveforms 16 Figure 2.9 Output voltage and output current waveforms 16 Figure 2.10 (a) Common-source switch 18 Figure 2.10 (b) Common-gate switch 18 Figure 2.10 (c) Common-gate switch combined with common-source stage 18 Figure 2.10 (d) Maximum voltage stress for each case 18 Figure 3.1 CMOS cascode Class E power amplifier 21 Figure 3.2 Simulated waveforms of the cascode Class E power amplifier 21 Figure 3.3 Theoretical and simulation results of VDS2 against supply voltage 24
Figure 3.4 Drain voltage of M1 and M2 as the variations of VDD 25
Figure 3.5 Drain-source voltage and drain current of M2 26
Figure 3.6 Equivalent model of the transistor M2 28
Figure 3.7 Theoretical results of Cdb2, Cgd2 and gm2 against supply voltage 28
Figure 3.8 Theoretical and simulated result of |Zds2| against supply voltage 30
Figure 3.9 AM-AM and AM-PM distortion 30 Figure 4.1 Equivalent schematic of the PA with AM-AM and AM-PM
compensation 33
Figure 4.2 Simulated results of |Zds2| and VDS2 against supply voltage 34
Figure 4.3 Simulated results of M1 and M2 drain voltages against supply voltage 34
against supply voltage. 35 Figure 4.5 Compared AM-AM and AM-PM distortion 35 Figure 4.6 Compared dc current 37 Figure 4.7 Compared drain efficiency 38 Figure 4.8 Gain and output power against supply voltage 38 Figure 5.1 Cascode Class E power amplifier 41 Figure 5.2 Simulation results of the AM-AM and AM-PM distortion 43 Figure 5.3 Simulation results of drain efficiency and dc current 43 Figure 5.4 Simulation results of power gain and output power 44 Figure 5.5 Chip photo of cascode Class E power amplifier 45 Figure 5.6 PA measurement setup 45 Figure 5.7 Measured results of AM-AM and AM-PM distortion 46 Figure 5.8 Measured results of output power and drain efficiency 46 Figure 5.9 (a) cascode Class E PA with self-biased control circuit 48 Figure 5.9 (b) self-biased control circuit 48 Figure 5.10 Simulation results of the AM-AM and AM-PM distortion 49 Figure 5.11 Simulation results of efficiency and output power 49 Figure 5.12 Chip photo of Class E amplifier with self-biased control circuit 51 Figure 5.13 PA measurement setup 51 Figure 5.14 Measured results of the AM-AM and AM-PM distortion 52 Figure 5.15 Measured output power, PAE and drain efficiency versus supply voltage 52 Figure 5.16 Measured output power and power gain versus input power 53 Figure 5.17 Measured output power and PAE versus frequency 53 Figure 6.1 The system co-verification platform 57 Figure 6.2 EER transmitter 57 Figure 6.3 Histogram of the envelope voltage 57 Figure 6.4 received constellations (a) PA without compensation, and
(b) PA with compensation. 58 Figure 7.1 Schematic of basic Class-E amplifier with equivalent series resistances 61 Figure 7.2 Drain efficiency versus Q-value of inductors Qck and Qt 61
Figure 7.3 CMOS MEMS fabrication process 63 Figure 7.4 Fabricated suspended inductor photograph 64 Figure 7.5 Micrograph and cross section view of the suspended inductor 65 Figure 7.6 Simulated and Measured results of the suspended inductor 65
Figure 7.7 Cross-section view of suspended inductor 66 Figure 7.8 Q-value of CMOS inductor and suspended inductor 67 Figure 7.9 The Q-value of inductors with different metal thickness 67 Figure 7.10 Cascode Class-E PA with suspended inductors 68 Figure 7.11 Comparison results of dc current and output power versus supply voltage 69 Figure 7.12 Comparison results of drain efficiency versus supply voltage 69 Figure A.1 Effect of the finite dc-feed inductance on the Class E circuit elements 75 Figure B.1 Common source Class E with stacked resistance 77 Figure B.2 Comparison of AM-AM and AM-PM distortion 78 Figure B.3 Comparison of power gain and output power 78 Figure B.4 Comparison of drain efficiency and dc current 79
List of Tables
Table 2.1 Class E design equations [52] 10 Table 2.2 Design parameters of the Class E amplifier 15 Table 3.1 Design parameters of cascode Class E amplifier 21 Table 5.1 Performance summary 55 Table 5.2 Comparison results 55 Table 6.1 Performance summary 59
Chapter 1
Introduction
To increase the capacity of wireless data transmission, recent wireless system, wireless LAN (WLAN), allows amplitude or envelope variations of the phase modulated RF carriers. In order to efficiently use the limited available frequency spectrum, these systems employ spectrally efficient spectrum, such as orthogonal frequency division multiplexing (OFDM). IEEE 802.11a/g systems, for example, are capable of transmitting data at the rate of 54 Mb/s while occupying a channel bandwidth of only 20 MHz. This bandwidth efficiency in the frequency domain comes at the expense of the increased peak-to-average-power ratio (PAPR) in the time domain. For example, 802.11a OFDM signals theoretically have a PAPR of 17 dB. In contrast to constant envelope systems like GSM and Bluetooth, the signal with envelope variations requires a linear power amplifier (PA) in transmissions. A linear power amplifier, such as a Class A or AB amplifier, has the drawbacks of lower efficiency and hence reduced battery lifetime. Since the efficiency of PAs is and has always been a major topic in transmitter systems, decreasing the dissipated power and increasing battery lifetime are the driving forces in the development of efficient systems.
Therefore, the efficient transmitters of envelope elimination and restoration (EER), polar and envelope-tracking (ET) are more attractive in wireless communication systems in the latest years [1]-[37], as shown in Figure 1.1. The EER transmitter is first proposed as it can utilize efficient switching power amplifiers, while also providing high linearity [38]. Recently, the EER system and its modern derivative polar and ET systems have been extensively discussed in wireless communication applications [39]-[44].
Figure 1.1 Cutting edge architecture of transmitters.
1.1 Motivation
For the efficient transmitters as shown in Figures 1.2, Figures 1.3 and Figures 1.4, to recombine the envelope and phase signal is to use a switching mode Class E power amplifier, which is a potential candidate for power amplification in wireless transceivers. The linearity requirements in Class E PAs have been concerned [45]-[50]. As shown in Figures 1.5, several techniques such as digitally modulated technique [10]-[14], using thick-oxide transistors [16]-[17], feedback topology [15] [29] and predistortion technique [28], have been proposed to solve the PA linearity problems in efficient transmitter applications. Moreover, the cascode-based topology of Class E PAs is considered for reliability analysis.
The research goal of this work is to explore the techniques for implementing a cascode Class E power amplifier for polar systems in low-cost complimentary metal-oxide semiconductor (CMOS) technology while provide sufficient performance. For reliability issues in a CMOS technology process, the cascode topology is a viable way to relax the device stress in Class E power amplifiers [42], [50]-[51]. Since the AM-AM and AM-PM
distortion is the important specification for PAs in polar transmitter applications, the design issues of compensating the distortion is one of the interests of the work. Moreover, CMOS multi-metal layer suspended inductors are presented to improve the efficiency of the PA.
Figure 1.2 Envelope elimination and restoration (EER).
Figure 1.3 Polar transmitters.
Figure 1.4 Envelope-tracking transmitters.
Figure 1.5 Technologies for linearity improvement.
1.2 Organization
The organization of the dissertation is overviewed as follows:
Chapter 2 begins with a review of conventional common source Class E power amplifiers. The characteristic of power control and practical considerations are included. The small dc-feed inductor for integration as well as the cascode topology of the Class E for reliability analysis is also discussed in the chapter.
Based on the design methodology of the Class E in Chapter 2, a conventional cascode Class E power amplifier using a CMOS 0.18 µm technology has been presented in Chapter 3. Moreover, the characteristics for supply modulation applications have been discussed. The detailed analysis for the AM-AM and AM-PM distortion is described in the chapter.
The AM-AM and AM-PM distortion of the cascode Class E amplifiers mainly comes from the nonlinear operation of the cascode transistor against the changed supply voltage.
Chapter 4 presents the technique to compensate the distortion. When modulating the gate bias voltage of the cascode transistor, the transistor is operated as a resistance alike and the distortion is improved. Moreover, the efficiency performance of the amplifier is discussed in the chapter.
One design of cascode Class E power amplifier implemented in a CMOS 0.18 µm technology process has been presented in Chapter 5. With controlling the external biasing voltage, the experimental results demonstrate the ability of proposed technique on compensating the AM-AM and AM-PM distortion. Furthermore, the design of cascode Class E power amplifier with auto-biasing control circuit has also been implemented in a CMOS 0.18 µm technology process. Its experimental results show the cascode Class E amplifier with compensated AM-AM and AM-PM characteristics.
Chapter 6 presents the RF/baseband co-verification platform with OFDM-based signal source for EER system. The co-simulation results demonstrate the improved system EVM due to the PA using proposed compensation technique.
The PA efficiency is severely degraded due to the internal inductors with low quality factor. To alleviate the problem, a developed CMOS MEMS process and stacked metal layer suspended inductors have been presented in Chapter 7. The simulation results shows that the efficiency of the PA with proposed technique and suspended inductors can effectively increased. For the completeness of the dissertation, the cascode transistor replaced by a resistance in the cascode Class E has been presented and its results compared with that of the compensated cascode Class E are included in Appendix B.
Chapter 8 concludes the summary of contributions and some suggestions for future work.
Chapter 2
Design Considerations of Class E Power
Amplifiers
Progress in the last years has shown that CMOS, traditionally confined to the digital and baseband part of radio transceivers, is also a competitive technology for radio frequency (RF) front-end. The demand for compact, low-cost and low-power portable wireless devices has prompted the quest for single-chip radio transceivers realized in a standard CMOS technology. One of the most difficult remaining challenges is the integration of the power amplifier that meets the required output power with high efficiency. Recently, there have been considerable interest and research effort in the design, analysis and implementation of CMOS Class E tuned PAs [52]. This is due to its high efficiency, simplicity and high tolerance to circuit variations, comparing to other types of PA. As a result, the Class E is the most attractive power amplifier for power efficient transmitter designs. Therefore, understanding the operation of the Class E power amplifier is necessary. The circuit principle of the Class E is introduced in Section 2.1. After that, the cascode topology of Class E is also discussed in Section 2.2, where this topology is commonly used to reduce the high drain voltage swing on each transistor.
2.1 Common-Source Class E Power Amplifier
It is desirable to obtain high RF power amplifier efficiency in many practical applications. At least one, if not all, of the following requirements is important: low power consumption, low
power amplifiers can achieve very high efficiency by minimizing the dissipated power in the transistor.
2.1.1 Design Principles
The key idea behind any high efficiency power amplifier is to reduce the overlap of current conducting through the transistor and voltage across the transistor. This will result in less dissipation in the transistor and hence increases the efficiency of the amplifier. A second idea is to use the transistor not as a current source, but as a switch. A further efficiency enhancement is obtained by minimizing the voltage across the switch when it is closed, the so-called zero-voltage switching criteria (ZVS). Thus the product of the transistor voltage and current will be low at all time during the period. Figure 2.1 shows the ideal waveforms of the transistor voltage and current that meet the high-efficiency requirements [53]. The low voltage-current product can be made because:
1. “ON” state: The voltage is zero when the current is drawing. 2. “OFF” state: The current is zero when the voltage level is high.
3. The rise of transistor voltage is delayed until after the current has reduced down to zero.
4. The transistor voltage returns to zero before the current begins to rise. 5. The slope of the transistor voltage waveform is zero at turn-on time. 6. The transistor voltage at turn-on time is zero.
The basic topology of the Class E amplifier is shown in Figure 2.2 [54] [55]. The circuit includes a transistor M1, operated as a switch, a shunt capacitor Cshunt, an RF choke Lck, a
series-tuned output circuit Ls-Cs, a reactance jX and the load resistance RL. Cshunt is the
parasitic capacitance in parallel at the switch (including intrinsic transistor output capacitance and circuit stray capacitance).
The simple equivalent circuit is based on the following assumptions [50], [53].
The RF choke Lck is ideal: zero series dc resistance and infinite reactance at the
operating frequency. The RF choke therefore allows only a constant (dc) input current.
The series resonant circuit Ls-Cs is tuned to the operating frequency. 2.1 COMMON-SOURCE CLASS E POWER AMPLIFIER
At the operating frequency a series reactance jX produces the difference in the reactance of the inductor and capacitor of the series-tuned circuit.
The active device acts as an ideal switch: zero saturated voltage, zero turn-on resistance, and infinite OFF resistance; the switching action is instantaneous and lossless.
The total capacitance, Cshunt plus the intrinsic transistor output capacitance, is
independent of the drain voltage.
All components are ideal.
Figure 2.1 Ideal waveforms in high efficiency power amplifiers.
Figure 2.2 Schematic of common-source Class E power amplifier.
Therefore, the voltage-current separation and ZVS are obtained by the series-tuned LC network. The switch is closed at the instant where both the switch voltage and its first derivative are zero. The ZVS condition prevents dissipation of the energy stored by the shunt capacitor at turn-on time. The requirement of a zero first derivative makes the amplifier less sensitive to component, frequency and switching instants variations. This leads to the well-known Class E conditions as stated by Sokal [53]:
0
)
(
t
1=
swing
V
(2.1)0
1=
=
∂
∂
t
t
t
V
swing (2.2) where t1 represents the instant at which the switch, and Vswing(t1) represents the switchingvoltage. A Class E amplifier then can generate waveforms that approximate the conceptual waveforms. The derived component values and the operation waveforms of the Class E amplifier will be discussed in the next section.
2.1.2 Design Equations
Based on the assumptions above, the equivalent circuit of the Class E amplifier can be obtained in Figure 2.3. A Class E amplifier consists of a switch S, an inductor Lck connecting
the switch to the supply voltage VDD, a capacitor Cd in parallel with the switch, a tuned circuit
Cs-Ls in series with a reactive component Lx and a load RL.
The value of RL is chosen to deliver a desired amount of power with a specific supply
voltage VDD. This network acting as a filter also rejects the harmonics of the Class E
waveform at the drain of the switch. In the original Class-E design of Sokal, the RF choke (Lck) is made very large so it acts as a current source. Cs and Ls form a series resonator tuned
at the desired frequency. Since the Class-E working conditions are given by two equations, two components of the circuit can be chosen in such a way that the amplifier fulfills the Class-E working conditions (Equations (2.1) and (2.2)). For the circuit of Figure 2.3, these two components are the capacitor Cd and the inductor Lx. In this way, all components are
determined. The values of elements for Class E operation are given on Table 2.1, where Qout
is the quality factor of the output network. The design parameter Qout involves a tradeoff
between operation bandwidth and the harmonic content of the output signal. For design specifications of a Class E, VDD=1.8 V, ω=2π·2 Grad/sec, Pout=100 mW, Qout=10000, its
voltage and current waveforms are simulated by an ADS simulator. The switch with an on-resistance of 0.00001 Ω and an off-resistance of 1 MΩ are also assumed.
Figure 2.3 The Class E configuration. Table 2.1 Class E design equations [52].
Figure 2.4 Switching voltage and switching current waveforms.
Figure 2.4 shows the switching voltage and the switching current waveforms of the Class E. The switching voltage and the switching current are not overlap, causing no power dissipation in the amplifier. When the switch is OFF, the voltage has a maximum value of 6.4 V, which is 3.56 times the supply value. When the switch is ON, the switch draws a large current Id, as shown in Figure 2.5. When the switch is OFF, the switch draws a zero current,
and then the capacitance Cd begins to charge with a current Ic. This means that the amplifier
switches correctly, changing alternately between ON and OFF. The output voltage and current with a sine wave, shown in Figure 2.6, are achieved when the switching voltage and current are through the series-tuned network. The harmonic content of the output signal are filtered out by this tuned network resonating at the carrier frequency. Finally, the efficiency (Pout/VDD·IDC) of 99.78% is obtained, where the Class E has a theoretical efficiency of 100%.
These results indicate that the analytic solution has an appropriate prediction on the operation of the Class E amplifier.
Figure 2.5 Current waveform of Id and Ic.
Figure 2.6 Output voltage and output current waveform.
2.1.3 Power Control
Since the input signal only provides timing information in a Class E power amplifier, the output power can not be controlled through the input signal like what is normally done in a linear or weakly nonlinear amplifier. Instead, the control of output power can be effectively realized through a variable supply voltage, for example, by a dc-dc converter. Since VDD is
the only voltage reference in the switching circuit, the voltage at each node is proportional VDD, and the power term of output power is proportional to VDD2. This means that the output
power can be controlled through the supply voltage, which leads to the potential of maintaining a constant efficiency over a wide range of output power. This is illustrated in Figure 2.7, in which we assume, without loss of generality, that the loss is only from the finite on-resistance of the switch. Since both the loss and the output power scale with VDD2, their
ratio, and the overall efficiency, are virtually unaffected as the output power is adjusted through the supply voltage.
.
,
2const
P
P
P
Efficiency
V
P
P
loss out out DD loss out∝
⇒
=
+
=
(2.3)This characteristic is in sharp contrast to conventional power amplifiers with constant supply voltage in which the efficiency is typical optimized only at the maximum output power. Because the PA may spend most of its time operating at medium or low power levels in practical applications [56], a constant efficiency can potentially result in substantial power saving.
Figure 2.7 Constant efficiency over variable supply voltage.
2.1.4 Practical Considerations
The analysis presented in previous sections is based on several simple assumptions. In practice, however, some conditions are not acceptable in the implementation of chip design [57].
Non-ideal passive components: The loss of passive components in CMOS technology can not be neglected because with low quality factor.
A large RF choke is hard to implement in an on-chip design.
Nonzero transition time: there exists inevitable transition time between ON and OFF. During the transition, the overlap of the switch voltage and the switch current causes the potential power dissipation in the typical switching amplifier.
A square waveform as an input driving is not easy to implement.
A nonzero on-resistance and a nonzero saturation voltage of the transistor [58].
Finite Q of the load network: The output signal with a pure sine waveform can not be achieved, because the finite Q of the series-tuned output network.
2.1.5 Finite DC-Feed Inductor
The Class E required an RF choke between the dc supply voltage and the active device has been described in the previous section. However, the RF choke itself is large in size, and hence presents problems in terms of both large resistance loss and hard to implement in a single chip. Therefore, a small inductance is necessary for designing a fully-integrated Class E power amplifier.
While we have analytic solutions to the element values of a Class E amplifier with an RF choke, the element values for finite dc-feed inductance should be obtained by solving a set of differential equations with iterative numerical methods [53], [59]. Based on Equations (A.6)-(A.11) (see Appendix A), the component values of the Class E amplifier can be obtained. For example, the specifications of Class E are assumed as follows: VDD=1.8 V,
carrier frequency=2 GHz, Pout=24 dBm (~250 mW), and the dc-feed inductance of 2 nH. The
calculated component values are summarized on Table 2.2. The simulated switching voltage and current waveforms are also reported in Figure 2.8. For given parameters, the Class E switches normally and its output signal waveform approximates a sine wave, as shown in Figure 2.9. Therefore, design parameters for the Class E amplifier with a dc-feed inductor are available.
Table 2.2 Design parameters of the Class E amplifier. Parameter Value Units
VDD 1.80 V Pout 250 mW f 2 GHz Lck 2 nH RL 13.3 Ω Cd 2.53 pF Lx 0.591 nH Ls 2.53 nH Cs 2.50 pF 2.1 COMMON-SOURCE CLASS E POWER AMPLIFIER
Figure 2.8 Switching voltage and switching current waveforms.
Figure 2.9 Output voltage and output current waveforms.
According to design equations mentioned previously, the required RL of Class E with a
finite dc-feed inductance is 13.3 Ω and with an RF choke is 7.48 Ω on the same design
specifications. It was shown that the Class E configuration with finite dc-feed inductance increases the load resistance RL for a given output power and supply voltage by exploiting the
property that the load resistance RL is a complex function of the dc-feed inductance.
In a Class E ensuring functionally switching, the inductor Lck can be either an RF choke
or a finite inductor. One benefit of a finite inductance Lck instead of an RF chock is to provide
the relief on the supply voltage and the load resistance [60]. If the dc-feed inductance is finite, we have one more degree of freedom, the value of dc-feed inductance, in choosing the element values for a given design requirement than with an RF choke.
2.2 Cascode-Based Topology
The feasibility of realizing efficient power amplifiers in regular CMOS technology is to receive increased attention because of considerable economic and fully-integration benefits. It was also shown that the Class E configuration with finite dc-feed inductance increases the load resistance RL for a given output power and supply voltage by exploiting the property that
the load resistance RL is a complex function of the dc-feed inductance. For further increase of
the load resistance RL, it is desirable to find the way to allow high supply voltage for a given
technology without stressing the transistors because the load resistance RL is basically
proportional to the square of the supply voltage [53]. However, as the technology scale down the safe operating voltage will decrease.
Usually, the transistor is switched from the gate as shown in Figure 2.10 (a), but the maximum voltage across on the transistor is Vdrain,max can be as large as 3.56 times the dc
supply voltage for an ideal Class E power amplifier. At this regard, gate-oxide breakdown, occurring when high voltages drop across the gate oxide, deserves particular care in a conventional common-source Class E power amplifier [58]. On the contrary, if the transistor is switched from source instead of the gate as shown in Figure 2.10(b), the maximum voltage stress is reduced to Vdrain,max-VGG because the source of the transistor swings up with the input
voltage [61]. Therefore, the maximum allowable supply voltage is Vdrain,max/(Vdrain,max-VGG)
times larger for common gate switch than that for a common-source switch. The common-gate switch presents the input driving stage with a low impedance node, differing from the common-source switch with a high impedance node.
Figure 2.10 (a) Common-source switch, (b) Common-gate switch, (c) Common-gate switch combined with common-source stage, (d) Maximum voltage stress for each case
assuming the voltage Vin swings from 0 to VGG.
In order to avoid the damage to the transistor due to the low breakdown voltage in CMOS process and the low impedance driving node, the cascode topology is a viable way in designing Class E power amplifiers [42] [62]. In Figure 2.10 (c), a common-source stage is combined with the common-gate switch into the cascode topology. In this way, the maximum drain voltage is divided between the two devices, and also the maximum oxide voltage drop reduces since a constant voltage VGG is applied on the gate of common-gate transistor. During
the OFF state, the drain voltage of the common-source switch transistor rises to VGG-VT. The
maximum drain-source voltage drop, therefore, reduces from Vdrain,max to Vdrain,max-VGG+VT.
The additional benefit of the cascode Class E is the reduced output-input coupling [63].
The important feature of the Class E for communication system applications is the mechanism of modulating the supply voltage. Although cascode implementations of Class E
power amplifiers are present in the literatures, the source of AM-AM and AM-PM distortion as supply modulation has never been discussed nor identified.
2.3 Summary
This chapter gives an overview of Class E power amplifiers. The overview of the switching power amplifier designs, including common-source topology and cascode-based topology, are given. The design methodology of common-source Class E amplifiers with RF choke has been revisited, and for the fully-integration purpose the amplifiers with finite dc-feed inductor has also been described. The cascode topology, for reliability analysis in CMOS process technology, of Class E power amplifiers is required and its characteristics are also studied.
Chapter 3
Design Considerations of Cascode Class E
Power Amplifiers
For reliability analysis and fully integration, the cascode Class E power amplifier with a small dc-feed inductance is a good candidate for communication system applications. For high efficiency transmitter applications, the characteristics of the cascode Class E power amplifier should be identified, especially in AM-AM and AM-PM distortion. In this chapter, Section
3.1 describes a design of CMOS cascode Class E power amplifier. Section 3.2 introduces the cause of AM-AM and AM-PM distortion. The physically based analysis compare with the simulation analysis give more details and understandings on the cause of the distortion.
3.1 Operation Waveform Analysis
The cascode Class-E power amplifier, shown in Figure 3.1, consists of two nMOS transistors, a dc-feed inductor, and output network comprised of a shunt capacitor, a series LC circuit and an impedance matching network. The series LC circuit appears inductive at the carrier frequency and the impedance matching network made of Lm-Cm transforms 50 Ω,
representative of the antenna resistance, into RL. The inductor Ls, Lx and Lm can be realized
by the inductor Lout. The shunt capacitor Cp is implemented entirely by a parasitic capacitor of
the transistor M2 drain to ground. The transistor M1 is biased at threshold voltage for a 50%
duty cycle while the transistor M2 is applied by a dc voltage VGG. The input signal is used to
Figure 3.1 CMOS cascode Class E power amplifier. Table 3.1 Design parameters of cascode Class E amplifier.
Device Value Units Lck 2 nH
Cp 1.1 pF
Cs 5 pF
Lout 2.5 nH
Cm 0.9 pF
Figure 3.2 Simulated waveforms of the cascode Class E power amplifier.
For design specifications of f = 2.6 GHz and Pout = 125 mW (~21 dBm), all design
parameters of the cascode Class E amplifier with a dc-feed inductor can be obtained, referring to the analytic solution in Appendix A. All component values of a CMOS 0.18 µm Class E amplifier are summarized on Table 3.1. The additional degree of freedom provided by finite dc-feed inductance Lck=2 nH is set, whereas Lck is small enough to be implemented in CMOS
process. The shunt capacitance is entirely absorbed by the output capacitances of cascode transistor. For an ideal Class E power amplifier with an RF choke, the peak voltage stress on the switch is no longer 3.56VDD. For practical Class E power amplifiers, the peak voltage can
be as low as 2.4VDD, as illustrated in the simulated waveforms in Figure 3.2, which is
obtained from ADS simulation of the circuit in Figure 3.1 with VGG = 1.8 V and VDD = 1.8 V.
In order to switch the common-source transistor correctly, the input power of 6 dBm is required. Due to the voltage at the source of cascode transistor is nearly VGG-VTH, the
maximum voltage stress of Vdrain,max is reduced to Vdrain,max-VGG+VTH, where the threshold
voltage VTH is ~ 0.45 V.
The correct component values of output network allows the drain voltage and current of the transistor M2 operating separately without the overlap of waveforms and tunes out the
desired frequency at the output load. However, in practice, the transistor M1 has a finite
on-resistance and transition time from the OFF-state to the ON-state. Therefore, the peak voltage is reduced to 2.4VDD due to the nonzero on-resistance. These factors cause a certain
amount of power dissipation on the switch, resulting in a reduction in power efficiency [60]. The simulated drain efficiency of the amplifier is degraded to 60%, and the output power is 18.5 dBm.
3.2 Physical Analysis of AM-AM and AM-PM
Distortion
In EER or polar transmitters, the Class-E PA is driven by two input signals, one is the constant-envelope RF signal and the other is the modulating signal delivering to the PA supply voltage. The RF output signal, therefore, can be recombined by the Class E power amplifier. However, when the PA is in supply modulation, the modulated transistors cause the
AM-AM and AM-PM distortion on the RF output signal. The AM-AM distortion is the difference between the supply voltage and the envelope of the RF output voltage. Such a difference is caused by a nonlinear relationship between the supply voltage and the envelope of the RF output signal. The AM-AM distortion in the RF PA itself can be kept low if it is always operated as a switching amplifier. In other words, the supply voltage of the PA driver stage will be kept high to ensure the switching nature of the amplifier. Besides the AM-AM, the AM-PM distortion will also be presented in the circuit. This distortion is an unwanted phase modulation of the RF output carrier due to the modulation of the supply voltage. The distortion will severely degrade the system emission performances. It is necessary to identify the cause of this distortion in order to recover the transmitted RF signal.
3.2.1 Device Operation
As drain amplitude modulation of PAs, the transistor M1 still acts as a switch, however, the
transistor M2 operating in different mechanisms dependents on the variations of supply
voltage. When the transistor M1 is turn-on, the voltage across these two transistors is very low
because the transistor M1 acts as a switch and the transistor M2 only provides a path for
current-flowing. When the transistor M1 is cut-off, no current flows from the transistor M2
drain to ground and the transistor M2 drain voltage is still allowed to surpass the supply
voltage.
In small supply voltage range, the transistor M2 operates in the deep-triode region and
therefore its drain-source voltage, VDS2, is very low, occupying extremely small voltage
headroom. VDS2 means the dc component of the M2 drain-source voltage, Vds2. When the
supply voltage is large enough to completely turn the transistor M1 on, the transistor M2 has
the ability of current driving and occupies the significant drain-source voltage. According to the statement above, the voltage VDS2 can be expressed as
0 2 = DS V , for VDD < Vc (3.1) c DD DD c c DD DD DD DS V V V V V V V V V − × − − × = max , max , 2 1 max , max , 2 1 2 , for VDD ≥ Vc (3.2)
where VDD,max=1.8 V, Vc=(VGG-VTH)/λ and λ is the ratio of the M2 maximum drain voltage to
VDD,max. When λ is 2.4, Vc is ~ 0.6 V. In Equations (3.1) and (3.2), the effect of the maximum
drain voltage of the Class-E amplifier has been included. Equations (3.1) and (3.2) illustrate that the drain-source voltage of the transistor M2 is changed not only by the supply VDD but
also by the gate-biased voltage of the transistor M2. In other words, the voltage VDS2 is
simultaneously modulated by the supply voltage and the voltage VGG.
The theoretical result of Equations (3.1) and (3.2), and simulated VDS2 are plotted in
Figure 3.3. The supply VDD is swept from 0 to 1.8 V by 0.2 V per step. It shows that the
theoretical result has a good agreement with the simulated result. It indicates that the operating mechanisms of transistors are varied with the modulated supply voltage. On this operating condition, the relationship of the voltage VDS2 and the supply voltage is nonlinear.
Furthermore, this variant condition of the transistor M2 leads to a nonlinear drain-source
voltage, which will also introduce a non-constant capacitance and a non-constant transconductance.
Figure 3.3 Theoretical and simulation results of VDS2 against supply voltage. 3.2 PHYSICAL ANALYSIS OF AM-AM AND AM-PM DISTORTION
3.2.2 I/V Curve
As the variations of VDD, the transistor M1 and M2 operate in different operating mechanisms,
which can be illustrated by drain voltage waveform of the transistor M1 and M2, respectively.
The simulated drain voltage waveforms of the transistor M1 and M2 are reported in Figure 3.4.
The supply voltage is swept from 0 V to 1.8 V by 0.2 V per step. As VDD ≤ 0.6 V, the
transistor M1 acts as a switch and the transistor M2 just performs a transmission path for the
current drawn from the power supply to M1. The drain voltage waveforms of the transistor M1
and M2 are almost the same because the required drain-source voltage of the transistor M2 is
very small. When the supply approximates 0.6 V, the transistor M1 is close to completely
switching and the transistor M2 begins to have the capability of amplifying the desired signal.
Figure 3.4 Drain voltage of M1 and M2 as the variations of VDD. 3.2 PHYSICAL ANALYSIS OF AM-AM AND AM-PM DISTORTION
Figure 3.5 Drain-source voltage and drain current of M2.
When VDD > 0.6 V, the drain voltage of transistor M1 only has the slightly increase, but, the
drain voltage of transistor M2 begins to increase proportionally to VDD. In this operating
condition, the transistor M1 acts as a switch and the transistor M2 gradually amplifies the
signal with the increased supply voltage. Furthermore, in order to understand the operating mechanisms of transistors, the drain-source voltage and drain waveforms of the transistor M2
as shown in Figure 3.5 can have an illustration on that.
Figure 3.5 shows the drain current increases proportionally to the supply voltage. This indicates that the amplifier can regularly operate in the varied supply voltage. However, the drain-source voltage only amplifies proportionally to the supply voltage, as the supply voltage is swept from 0.6 to 1.8 V. It is owing to the transistor M2 operating in different regions.
Unfortunately, due to this nonlinear relationship of the voltage and current, the amplifier will have an amplitude error and a phase error on the RF output signal.
3.2.3 Impedance Variation
When modulating the PA supply voltage, the transistor M2 operating in different regions has
nonlinear drain voltage and current output waveforms, which are caused by a nonlinear capacitance and a transconductance. Moreover, the PA output signal would accompany the nonlinear characteristics of the transistor M2. In this work, we propose that the drain-source
impedance variation of the transistor M2 is the cause of the AM-AM and AM-PM distortion.
This can be understood by the physical model depicted in Figure 3.6.
This simplified equivalent model consists of the gate-source capacitor (Cgs2), the
gate-drain capacitor (Cgd2), the drain-bulk capacitor (Cdb2) and the current-source (gm2·Vgs2).
Given an insight into impedance analysis, the capacitance Cdb2 and transconductance gm2 can
be given by Equations (3.3) and (3.4).
bi DB j db
V
V
C
C
2 0 21
+
=
(3.3))
(
)
(
2 2 n OX M2 GS TH mV
V
L
W
C
g
=
µ
−
(3.4)where Vbi is the built-in potential of the body diode, Cj0 is the output capacitance as the
drain-bulk voltage VDB2=0 and VGS2 is the dc component of the M2 gate-source voltage, Vgs2.
Equations (3.1) and (3.2) show that the variations of the supply voltage caused a nonlinear voltage VDS2. In Equation (3.4), the voltage VGS2 can also be expressed as VGG-(VDD-VDS2).
Substituting Equations (3.1)-(3.2) into Equations (3.3) and (3.4), the relationship of Cdb2 and
gm2 against VDD are plotted in Figure 3.7. Cgd2 is difficult to be expressed by the close form of
voltages. However, the values of Cgd2 are obtained by the interpolation method and also have
been included in Figure 3.7. The result indicates that, as VDD is swept from 0 to 1.8 V, the
nonconstant capacitances and the nonconstant tranconductance are introduced.
Figure 3.6 Equivalent model of the transistor M2.
Figure 3.7 Theoretical results of Cdb2, Cgd2 and gm2 against supply voltage.
Since the component values are non-constant, the equivalent drain-source impedance, Zds2, at the carrier frequency should be non-constant. The impedance Zds2 is derived according
to the equivalent model and has been given by Equation (3.5).
DD gd o ds db o gs m ds ds ds ds V C j V C j V g V I V Z λ ω ω 2 2 2 2 2 2 2 2 2 = = + + ) ( )) ( ( 2 2 2 2 2 2 DD gd ds db o ds DD GG m ds V C V C j V V V g V λ ω λ − + + − = (3.5)
where Ids2 and ωo denote the M2 drain-source current at the carrier frequency and angular
frequency, respectively. Equation (3.5) shows how the impedance Zds2 is a function of the
transconductance, capacitances and voltages. Furthermore, the transconductance, capacitances and voltages in Equations (3.3)-(3.5) can be expressed as a function of VDD, respectively. In
order to simplify the analysis, the magnitude of Zds2, |Zds2|, has been plotted against VDD as
shown in Figure 3.8, where |Zds2| has been given by Equation (3.6).
DD gd o ds db o gs m ds ds ds ds V C j V C j V g V I V Z λ ω ω 2 2 2 2 2 2 2 2 2 = = + + ) ( )) ( ( 2 2 2 2 2 2 DD gd ds db o ds DD GG m ds V C V C j V V V g V λ ω λ − + + − = 2 2 2 2 2 2 2 2 2 )) ( ( )) ( ( m GG DD ds o db ds gd DD DS V C V C V V V g V λ ω λ + + + − = (3.6)
The comparison in Figure 3.8 shows that the theoretical result is in good agreement with the simulated result and also proves that the variant capacitances and the transconductance of M2 really bring a nonconstant |Zds2|. This non-constant impedance will be converted to an
imperfect voltage waveform, equally the magnitude and phase errors, at the M2 drain node.
The difference between the theoretical result and the simulated result is due to the saturation voltage of transistors and the voltage drops on Lck are neglected. Furthermore, the PA output
signal accompanies with the magnitude and phase errors from the M2 drain node, so-called the
AM-AM and AM-PM distortion. The simulated AM-AM and AM-PM distortion has been shown in Figure 3.9.
The result reveals that the relationship of the envelope of the RF output voltage against the supply voltage is nonlinear and the voltage deviation at VDD=0 V causes an additional
distortion at low envelope levels. When the supply voltage deviates from its optimum value of 1.8 V down to 0.5 V the maximum AM-PM changes by 21 degrees/V and 21° of the phase error. In the supply voltage of 0 V to 0.5 V, the AM-PM is highly nonlinear and the phase error is as large as 78°. These characteristics indicate that low envelope levels are harder to reconstruct than high envelope levels.
Figure 3.8 Theoretical and simulated result of |Zds2| against supply voltage.
Figure 3.9 AM-AM and AM-PM distortion.
3.3 Summary
A prototype of cascode Class E power amplifier using CMOS technology has been presented. The characteristics of the cascode Class E amplifier in supply modulation have also been discussed. The theoretical analysis and simulation results illustrate that the cascode transistor operating in different regions cause the non-constant equivalent impedance at the drain node as the supply voltage is modulated. The impedance results in the magnitude and phase errors at the drain voltage as well as the AM-AM and AM-PM distortion on the output signal.
Chapter 4
Innovative Linearity Compensation
Technique
Since the cause of the AM-AM and AM-PM distortion has been discussed, a technique for compensating this distortion is presented in this chapter. By controlling the gate voltage of the cascode transistor, the nonlinear effects at its drain node are minimized and the AM-AM and AM-PM distortion at the output node are improved. Furthermore, the efficiency performance of the amplifier is also discussed. In this chapter, Section 4.1 describes the compensation technique for AM-AM and AM-PM distortion. The comparison results of the amplifier with and without compensation are reported. The efficiency performance, as the amplifier has been linearized, is discussed in Section 4.2.
4.1 Improved AM-AM and AM-PM
Since the non-constant impedance causes the nonlinear effect at the cascode transistor drain node as well as the AM-AM and AM-PM distortion at the output load, having a constant |Zds2|
should be allowed to minimize the distortion. In supply modulation, the cascode transistor is driven by two input signals, one is from the drain node and the other is from the source node. The drawing current therefore is simultaneously reacted by the gate-source voltage VGS2 and
the drain-source voltages VDS2. Moreover, the voltage VGS2 and VDS2 are the function of the
VDD and can be expressed as Equations (4.1) and (4.2), respectively, where VDS1(VDD) means
the non-constant component values are introduced. ) ( 1 2 GG DS DD GS V V V V = − (4.1) ) ( 1 2 DD DS DD DS V V V V = − (4.2)
In order to obtain a constant |Zds2|, it is feasible to get VGS2 and VDS2 linearly against VDD,
and the components value is linearly against VDD. According to the Equation (3.4) the voltage
of VGS2 –VTH should be linearly against VDD. And substituting the Equations (4.1) and (4.2),
the impedance |Zds2| can be expressed by the parameters of VGG and VDD. Therefore, the M2
gate voltage is changed to VDD + VTH, which forces the transistor M2 to act a resistance alike.
When the cascode transistor has been operated as a resistance as shown in Figure 4.1, it is expected that the impedance |Zds2| is constant.
In Figure 4.1, the adder produces a voltage, which equals the threshold voltage VTH plus
the supply VDD, on the M2 gate node and therefore the transistor M2 will be operated as a
resistance. During drain amplitude modulation, the adder output voltage varied with the supply VDD always forces the transistor M2 to operate as a resistance while the transistor M1
acts as a switch. Therefore, a constant |Zds2| is obtained and its simulated result has been
shown in Figure 4.2. It shows that the voltage VDS2 is linearly against the supply voltage and
hence the constant |Zds2| is obtained.
Figure 4.1 Equivalent schematic of the PA with AM-AM and AM-PM compensation.
Figure 4.2 Simulated results of |Zds2| and VDS2 against supply voltage.
Figure 4.3 Simulated results of M1 and M2 drain voltages against supply voltage. 4.1 IMPROVED AM-AM AND AM-PM
Figure 4.4 Simulated results of M2 drain-source voltage and drain-source current against
supply voltage.
Figure 4.5 Compared AM-AM and AM-PM distortion.
Figure 4.3 shows the simulation results of M1 drain voltage and M2 drain voltage. The
supply voltage is swept from 0 V to 1.8 V by 0.2 V per step. As expected, both the maximum drain voltages are proportionally increased with the supply voltage. It has much improvement comparing with the result in Figure 3.4. The results of M2 drain-source voltage and drain
current are shown in Figure 4.4. The drain-source voltage is also proportionally varied with the increase of the supply voltage. Therefore, when the cascode transistor M2 is degenerated
into a resistance, the linear voltage VDS2 and the constant impedance |Zds2| are achieved.
The results of the PA with and without the AM-AM and AM-PM compensation are compared in Figure 4.5. When the PA has the compensation, the relationship of the magnitude of the output voltage against the supply voltage is linear and the AM-PM in the supply voltage of 0.5 V to 1.8 V is improved from 21° to 2.2°. The proposed methodology evidently has compensated the AM-AM and AM-PM distortion of the PA during supply modulation.
4.2 Efficiency Improvement
One more advantage of the transistor M2 operating as a resistance is to improve the drain
efficiency in low supply voltage and extend the operating supply range. The dc current IDC in
[64] can be rewritten by Equation (4.3), where Vdmin means the finite drain-source voltage
during the transistor conducting and Rs is the source terminal resistance. The relationship
between the PA efficiency and the dc current IDC is given in Equation (4.4). When the PA
with or without the proposed compensation methodology, operating on the identical conditions of Pout and VDD, drain efficiency is inversely proportion to IDC.
) C (C R 2 1 ) V )(V C (C I gd2 db2 s dmin DD gd2 db2 DC + + − + = ω πω
π
(4.3) DC DC DD out DC out I 1 I V P % 100 P P Efficiency= × ∝ ∝ (4.4) Figure 4.6 shows the results of IDC against the supply voltage. In small supply voltage,the I value of the PA with compensation is less than the PA without compensation and
therefore drain efficiency of the PA is increased as shown in Figure 4.7. The maximum improvement of 20% is achieved at VDD=0.55V. This improvement benefits the operation of
the PA in low supply voltage. When modulating the supply voltage of the Class E PA, the consistent efficiency in entire operating supply range is demanded. In other words, the proposed methodology extends the operating supply range during supply modulation since the PA has the slightly degradation on drain efficiency in high supply voltage. The degradation in high supply voltage is due to the equivalent resistance has more dc power consumptions (see Appendix B). The results of power gain and output power against the supply voltage are also reported in Figure 4.8, where the input driving power is 6dBm. When the amplifier is compensated, the power gain and output power of the PA are not degraded. The result indicates that the proposed methodology can compensate the AM-AM and AM-PM distortion of the Class-E power amplifier without degrading the PA performance.
Figure 4.6 Compared dc current.
Figure 4.7 Compared drain efficiency.
Figure 4.8 Gain and output power against supply voltage.
4.3 Summary
The design methodology for compensating the AM-AM and AM-PM distortion has been proposed in this chapter. By changing the gate bias voltage of the cascode transistor, the distortion is compensated and its comparison results of the PA with and without compensation have also been reported. In the operating supply range, the AM-PM phase error has been reduced from 21° to 2.2°. Furthermore, the efficiency performance has the maximum improvement of 20% when the PA has been compensated.
Chapter 5
Circuit Implementation and Experimental
Results
In order to demonstrate the proposed compensation technique, designs of cascode Class E power amplifier and cascode Class E with auto-biasing control circuit have been implemented in CMOS technology process. In the design of Class E, the gate bias voltage of cascode transistor applied by the external supply intends to give a comparison of the AM-AM and AM-PM characteristic between the PA with and without compensation. Furthermore, the cascode Class E with auto-biasing control circuit is an example to show the PA with improved AM-AM and AM-PM characteristic. All of simulation and measurement results demonstrate that the compensation technique is allowed for improving the AM-AM and AM-PM distortion. In this chapter, the design of cascode Class E power amplifier and its measured results are described in Section 5.1. Section 5.2 presents the design of cascode Class E with self-biased control circuit and its measured results. The performances are summarized in Section 5.3.
5.1 CMOS Cascode Class E PA Design
5.1.1 Circuit Design
CMOS technology, as shown in Figure 5.1. The cascode topology of Class E amplifiers is used due to the concern of low breakdown voltage in CMOS process. For highly integration, all of passive devices are implemented by the internal components. The amplifier operates at 2.6 GHz from a 1.8 V supply voltage. The input matching network is designed to transfer the amplifier input impedance to 50 Ω at the carrier frequency. The series of Ls-Cs is designed to
have a 2.6 GHz resonant frequency. The 50 Ω load resistance is down-converted by means of the Lm-Cm network. A fit value of the inductor Lx is selected to separate the drain voltage
waveform and the current waveform. The inductor Ls, Lx and Lm are integrated with an
internal inductor. The series of La-Ca is implemented to improve power efficiency [51]. A
way to minimize the power loss is to tune out the parasitic capacitances by the inductor La,
resonating parasitic capacitances on node P at the desired frequency of operation. A blocking capacitor Ca is inserted between the inductor La and ground. The RF choke is implemented by
a small dc-feed inductance using an internal inductor. Considering the electrical performance of internal inductors, they have an allowed current density of 1mA/µm at the temperature of 85°C, and the maximum metal width of 20 µm, the thickness of 2 µm. Therefore, avoiding the metal damage of Lck, the PA was designed to have an allowed current capacity. Hence, the
large output power and drain efficiency are not the major design targets in this amplifier. The aspect sizes of the transistor M1 and M2 are 1080/0.18 µm/µm.
Figure 5.1 Cascode Class E power amplifier.
5.1.2 Simulation Results
A performance comparison is accomplished between the design of cascode Class E power amplifier without compensation and with compensation. The signal power of 6 dBm is applied at the input of the Class E amplifier. For the Class E amplifier without compensation the voltage VGG is applied at 1.8 V and for with compensation the voltage VGG is applied by
VDD+VTH, where VTH is 0.5 V. The VDD is swept from 0 V to 1.8 V, per 0.1 V step. The
comparison of AM-AM and AM-PM is shown in Figure 5.2. The relationship between the supply voltage and the envelope of the RF output signal has been linearized when the amplifier with compensation. The phase error is also improved from 15° to 2° as the VDD is
swept from 0.5 V to 1.8 V. In other words, it can see that the operating supply voltage range has been extended. The simulated results of drain efficiency and dc current are reported in Figure 5.3. The PA without compensation has the maximum drain efficiency of 40%. Due to the low quality of internal inductors, the large resistive losses of inductors result in the low drain efficiency of amplifiers When the PA with compensation, the amplifier consumes the less dc currents in small supply voltage and therefore can have the maximum improved efficiency of 13% at the VDD of 0.6 V. Furthermore, the efficiency against the supply voltage
is nearly constant in the extended operating supply voltage range. The peak drain efficiency is reduced to 37% at the VDD of 1.8 V. The amplifier has a maximum power gain of 10 dB and a
maximum output power of 16 dBm as the VDD is 1.8 V, as shown in Figure 5.4. 5.1 CMOS CASCODE CLASS E PA DESIGN
Figure 5.2 Simulation results of the AM-AM and AM-PM distortion.
Figure 5.3 Simulation results of drain efficiency and dc current.
