Characteristic of Unclamped Inductive Switch (UIS)

Fig. 4-7 demonstrates the test circuit of UIS and Fig. 4-8 shows the typical waveform of UIS. The DUT in Fig. 4-8 is typical nLDMOS. The voltage pulse which amplitude is equal 5 V (VGS) is applied to gate pad through Rgs. The Rgs protects the gate oxide from direct damage which results from voltage pulse of V_GS. The voltage pulse width of VGS is named as Tp and the inductive current is named as Iswitch, as illustrated in Fig. 4-7 and Fig. 4-8. The waveform can be divided by nodes of t₁, t₂, and t3. The voltage pulse (VGS) is applied to gate pad through Rgs during the period of time between t₁ and t₂. The DUT is turned on and the drain current (I_ds) is equal to the Iswitch. Moreover, the Iswitch increases with time according to the equation (4.1) when the DUT is on. The I_switch reaches its maximum as shown in equation (4.2). Besides, the DUT is at the linear region where the drain voltage is proportional to drain current.

Consequently, the drain voltage slightly increases with increasing drain current during the time period between t1 and t2. gradually decreases with time according to the equation (4.3). The channel of DUT is off but forced to conduct the inductive current; hence, the DUT is compelled in a state of avalanche breakdown. In consequence, the drain voltage (Vds) reaches a maximum (V_ds,max). The drain voltage and drain current of DUT are simultaneously high during the period of time between t2 and t3. Equation (4.4) shows the total energy that the

DUT withstands during the inductive switch. The energy may results in catastrophic damage. To quantify the ability to withstand the avalanche energy during the inductive switch, it is defined that the maximum allowable UIS I_switch,max is the inductive current when the DUT reach is maximum allowable EAS.



^ increases with time during the period of time between t1 and t2. The DUT is at linear region; as a result, the drain voltage slightly increases with increasing I_ds. The drain current and drain voltage reach their maximum (Iswitch,max and Vds,max) at t2. In Fig. 4-9 (a), the drain current and drain voltage degrade with time during the period of time between t2 and t3. The drain current is equal to 0 A and the drain voltage is return to V_cc at t₃. If the unstable state is over the boundary of eSOA as illustrated in Fig. 4-9 (b), the DUT will enter the snapback region and the drain current will increase until the DUT is failed. Hence, it is important to ensure that operates the DUT inside the boundary of eSOA.

The aim of following test is to verify the equation (4.2). Fig. 4-10 shows the waveform of inductive current with different power supply (Vcc). The fixed parameters are T_p and L_ext. Hence, the I_switch,max is proportional to V_cc as illustrated in Fig. 4-11.

Fig. 4-12 demonstrates the waveform of inductive current with different pulse

width (T_p). The fixed parameters are V_cc and L_ext. The slope of current waveform during the period time between t1 and t2 is equal to a constant, as shown in equation (4.5). Accordingly, I_switch,max is proportional to T_p as illustrated in Fig. 4-13.

L c Slope V

ext cc 

 (4.5)

where c is a constant for fixed VCC and Lext. Fig. 4-14 demonstrates the waveform of inductive current with different inductive impedance (L_ext). The fixed parameters are Tp and Lext. According to equation (4.2), Iswitch,max is reciprocal to Lext

as illustrated in Fig. 4-15. Moreover, the DUT is failed when the inductive impedance is equal to 1 mH. Fig. 4-16 shows the waveform with Lext = 1 mH. The unstable state is outside the boundary of eSOA as shown in Fig. 4-9 (b) for L_ext = 1 mH. Hence, the drain current increases until the DUT is failed. The DUT is short and the drain voltage is equal to 0 V in the end.

VGS

Tp

Vcc

L

ext

I

_ds

I

switch

R

gs

Fig. 4-7. The test circuit of unclamped inductive switch [30].

Fig. 4-8. The waveform of unclamped inductive switch.

(a) (b)

Fig. 4-9. The circuit trajectory of unclamped inductive switch. The unstable state is (a) inside and (b) outside the boundary of eSOA.

-2 -1 0 1 2 3 4 5 6

Fig. 4-10. The waveform of inductive current with different power supply (Vcc).

0 25 50 75 100

DUT: typical SCR-nLDMOS_A Tp=1 s

Fig. 4-11. The inductive current with different power supply (V_cc).

-2 -1 0 1 2 3 4 5 6

Fig. 4-12. The waveform of inductive current with different pulse width (Tp).

0.0 0.2 0.4 0.6 0.8 1.0 1.2

DUT: typical SCR-nLDMOS_A Vcc=100 V

Fig. 4-13. The inductive current with different pulse width (T_p).

-2 -1 0 1 2 3 4 5 6

Fig. 4-14. The waveform of inductive current with different inductive impedance (Lext).

DUT: typical SCR-nLDMOS_A Tp=1 s

Fig. 4-15. The inductive current with different inductive impedance (Lext).

Fig. 4-16. The waveform of UIS when device is failed.

The energy stored in the inductor totally transfers into the DUT during the UIS stress. The maximum energy that the DUT can withstand during the UIS stress is constant. Moreover, the energy stored in the inductor is proportional to Lext as shown in equation (4.6).

2

= •

2 ext max ,

switch L

Energy I (4.6)

Hence, the max. allowable UIS Iswitch,max is reciprocal to the Lext, as shown in Fig.

4-17.

Fig. 4-18 and Fig. 4-19 respectively show the waveform of drain voltage and

drain current with different gate bias.

To investigate the influence of gate bias on the UIS characteristic, the UIS tests with different amplitude of gate voltage pulse. For the amplitude of gate voltage pulse is larger than 1.5 V, the Ids increases with time. User can adjust the parameters of Tp, V_cc, and L_ext to get the proper operating current. For the amplitude of gate voltage pulse is smaller than 1.5 V, the Ids is limited by the DMOS channel current. Hence, it can’t reach normal operating current at real application.

To take the accuracy of Iswitch into account, the UIS tests as illustrated in Fig.

4-20 and Fig. 4-21 is repeated with different sample whose device structure and layout parameters are the same. Table 4-1 lists the corresponding values of UIS I_switch,max and V_{ds, max} in Fig. 4-21 and Fig. 4-21. The standard deviation of UIS Iswitch,max is slight. The standard deviation of Vds, max is 6.4 V.

0 20 40 60 80 100

0 2 4 6 8 10

DUT: typical SCR-nLDMOS_A Vcc=100 V Rgs=15

Max. allowable UIS Iswitch,max (mA)

Lext (mH)

Fig. 4-17. The maximum allowable UIS Iswitch,max with different inductive impedance (Lext).

-2 -1 0 1 2 3 4 5 6

Fig. 4-20. The waveform of drain voltage (Vds) with different samples whose device structure and layout parameters are the same during UIS stress.

Fig. 4-21. The waveform of drain current (Ids) with different samples whose device structure and layout parameters are the same during UIS stress.

-4 -3 -2 -1 0 1 2 3 4 5 6

TABLE 4.1

The UIS tests with different sample

UIS Iswitch,max (mA) Vds,max (V)

Sample 1 8.8 204

Sample 2 8.8 192

Sample 3 8.6 194

Average 8.7 197

Standard deviation 0.1 6.4

在文檔中 高壓製程靜電放電防護元件設計與其安全操作範圍之研究 (頁 76-87)