ESD is an instantaneous discharging of electrostatic charges on IC pins. It take place under the situations such as a physical touch of a human body and an IC products, contact of manufacturing machines and wafers, or discharge of secondhand induced electrical field on an IC chips. According to the different discharge conditions and sources of electrostatic charges, ESD can be classified to human-body model (HBM), machine-model (MM), and charged-device model (CDM).
3.1.1 Human Body Model (HBM)
HBM is a common ESD event that arose from the contact of a charged human body and an IC product. The friction between human body and an object results in the charged human body, thus the electrostatic charge transfers into the IC products when the charged human body touches the IC products. To prevent the catastrophically failure on IC products, the human body model is established to simulate this kind of ESD event and quantify the IC robustness against the HBM ESD event. The equivalent circuit for HBM ESD event is shown in Fig. 3-1 [21], where the 1.5-k
resistor and the 100-pF capacitor represent the equivalent parasitic resistor and capacitor of a human body. The DUT represents the device under test. The HBM design eliminates the weak ESD protection designs and protects the susceptible devices. Commercial ICs are generally demanded to pass 2-kV HBM ESD stress at
least, which can generate ESD current with a peak value about 1.3 A and a rise time about 10 ns. Fig. 3-2 shows the typical HBM ESD waveform generated by the ESD HBM tester to a short wire [21]. In particular, most of the HBM ESD energy is concentrate on the time interval between 0 ns to 100 ns.
High-Voltage Pulse Generator
DUT Socket 100pF
1.5k
S1
S2
Fig. 3-1. The equivalent circuit of the human body model ESD event [21].
Fig. 3-2. Definition of the HBM pulse decay time (td) [21].
3.1.2 Machine Model (MM)
The MM ESD event arose from the contact of a machine and IC products. The equivalent circuit diagram of MM ESD event is shown in Fig. 3-3 [22], where there is no equivalent resistor on the equivalent discharging path because the electrostatic charge source is charged machine with 0-resistor.
High-Voltage Pulse Generator
DUT Socket 200pF
S1
S2 10k~10M
Fig. 3-3. The equivalent circuit of the machine model ESD event [22].
Fig. 3-4. The current waveform of a 400-V MM ESD stress through a short wire [22].
Fig. 3-4 shows the waveform of a 400-V MM ESD pulse generated by the MM ESD tester [22]. A commercial IC product is generally required to pass at least 200-V MM ESD stress, which can generate an ESD current with a peak value about 3.5 A and a rise time about 10 ns. The MM ESD level of a semiconductor device is generally 8 ~ 12 times smaller than its HBM ESD level due to the faster rise time and voltage resonance of a MM ESD pulse.
3.1.3 Charged Device Model (CDM)
The CDM ESD event happens under the condition of the contact of charged IC and external grounded object. The IC is charged through the mechanism of electrostatic induction, and most of the CDM charges are initially stored in the body (the p-substrate) of a CMOS IC. When one or more pins of this charged IC is touched by an external grounded object, CDM charges in the p-substrate will be discharged from the IC inside to the grounded object outside. There is no standard equivalent parasitic capacitor and resistor for the CDM ESD stress because different dimension of chips, different form and size of packages result in different values of the parasitic capacitor and resistor of IC chips. Fig. 3-5 shows the simplified CDM test circuit. Rd, Ld and Cd represents the equivalent parasitic resistor, inductor and capacitance of DUT.
The DUT is initially charged through the large resistor Rg with relatively small current, and then DUT contact the grounded object and discharge immediately. A commercial IC is generally requested to pass at least 1-kV CDM ESD stress, which can generate an ESD current with peak current value about 15 A within a rise time less than 200 ps [23]. Fig. 3-6 makes a contrast with the waveforms of a 2-kV HBM ESD stress, a 200-V MM ESD stress, and a 1-kV CDM ESD stress which has 4-pF equivalent capacitor of the device under test. Table 3.1 shows the commercial specification for the HBM, MM and CDM level.
V
ESDRg
Rd
Ld
Cd
Device Under
Test
Fig. 3-5. The equivalent circuit of the charged device model ESD event [23].
Fig. 3-6. The waveforms of a 2-kV HBM ESD stress, 200-V MM ESD stress, and a 1-kV CDM ESD stress.
TABLE 3.1
The commercial specification for the HBM, MM and CDM level.
HBM (kV) MM (V) CDM (kV)
Okay +/- 2 +/- 200 +/- 2
Safe +/- 4 +/- 400 +/- 1.5
Super +/- 10 +/- 1000 +/- 2
3.1.4 Transmission Line Pulse (TLP) System
The equivalent circuit of TLP system is shown in Fig. 3-7 The TLP system applied the voltage pulse, which pulse amplitude is Vin and the pulse width is t, to the device under test (DUT). The oscilloscope measured the voltage and current during the TLP stress, and then the source-meter measured the leakage under certain bias condition.
Device Under
Test
To scope RL
Vin
t
Source of energy
V I
-+
Fig. 3-7. The equivalent circuit of the TLP system.
The steps above are sequentially repeated with increasing TLP pulse amplitude until the device satisfies the failed criteria. In this thesis, the definition of failed criteria is Ileakage > 100* Ileakage, initial, where Ileakage is the leakage current measured after TLP zapping and Ileakage, initial is the leakage current of fresh transistor. The I-V curve measured by TLP system is shown in Fig. 3-8. Trigger point represents the triggering of parasitical bipolar junction transistor (BJT). Secondary breakdown current (It2) represents the maximum allowable current. In other words, the device is judged to failure as the current is higher than It2. Interestingly, the HBM ESD waveform reveals that the ESD energy is concentrate on the time interval between 0 ns to 100 ns and it is observed that the HBM level is proportional to It2 [24]. With the information provided by TLP system, IC designers can easy choose the direct device under the guide of design window, as illustrated in Fig. 3-9 [25].
Fig. 3-8. The I-V curve measured by 100-ns TLP system.
0 25 50 75 100 125 150 175 200
Fig. 3-9. The ESD protection design window of HV ESD protection devices [25].