On-Chip Dual-Level V BB Generator

Fig. 4.12 shows the schematic diagram of SRAM cells with the proposed VBB

generator, which comprises two substrate bias generators, two recovery circuits, and a high/low control circuit. The substrate bias generators have been introduced in Chapter 3, and the recovery circuits are used to return VBBN and VBBP to their original values. High/low control circuit controls input pumping signals and thus the output voltages.

Fig. 4.12 Schematic diagram of SRAM cells with on-chip dual-level VBB generator.

4.2.1.1 Substrate Bias Generator

There are two substrate bias generators that the voltage doubler is for VBBP and the negative charge pump is for VBBN. Please refer to Chapter 3 for detail schematics and operations.

4.2.1.2 High/Low Control

Fig. 4.13 shows the schematic and operating waveforms of high/low control circuit. A clocking signal is fed into the circuit and Low signal is used to control the swing of output signals, Vout0 and Vout1. When Low is pulled low, both the PMOS transistors are turned on and input clocking signals directly pass through the transistors. When Low signal is pulled high, the PMOS transistors are off and the NMOS are on. Consequently, the swing of output signals is smaller than input clocking signal by an amount of Vt. The operating waveforms clearly illustrate the

operations.

Fig. 4.13 Schematic of high/low control and operating waveforms.

4.2.1.3 Recovery Circuits

Reversed body-bias is applied to unselected rows to reduce subthreshold leakage.

Once the rows are selected some mechanisms must be done to cancel the body-bias.

Fig. 4.14 shows the recovery circuits for both VBBN and VBBP and their operating tables.

Fig. 4.14 Recovery circuits for VBBN and VBBP and operation tables.

4.2.2 Simulation Results

The SRAM cell arrays with on-chip VBB generators are simulated in TSMC 0.13um technology. Some power consumption and power saving information are

discussed below.

4.2.2.1 Waveform of V_BB Generator

Fig. 4.15 shows the simulated waveforms of the VBB generator for both high and low conditions. In high condition VBBN reaches –1.15V and VBBP reaches 2.35V, where VDD is 1.2V. On the other hand, VBBN reaches –0.92V and VBBP reaches 2.12V in low condition. Note that the pumping frequency and output loading are 5KHz and 10pF, respectively.

Waveform of V_BB generator

Time (ms)

Fig. 4.15 Simulated waveforms of VBB generator.

4.2.2.2 Average Power of V_BB Generator

Fig. 4.16 shows the average power of VBB generator and it reveals that the average power converges with time. Fig. 4.16 clearly illustrates this feature that the power consumption in steady state is less than transition state. That is, for a row of SRAM with sufficient time period in standby, the average power overhead of VBB

generator converges to about 1.6nW. Therefore, the factor of time period in standby

mode must be taken into account when evaluating the net power saving.

Average power of V_BB generator versus time

Time (ms)

Fig. 4.16 Average power of VBB generator versus time.

4.2.2.3 Net Power Saving of SRAM

Fig. 4.17 shows the net power saving of SRAM versus time period in standby mode. The net power saving is defined as the original SRAM leakage power minus the remaining part and the power overhead of VBB generators. Fig. 4.17 illustrates that the net power saving increases with the increase of time. This is because the power overhead of VBB generator decreases with time.

Fig. 4.17 also shows the curves of different wordline lengths. It can be seen that wider wordline lengths achieve larger net power savings and reach the break-even points in less time. Break-even point means the point that the saved leakage power is equivalent to the power overhead of VBB generator.

Fig. 4.17 strongly proves the statement mentioned above that the power saving is time dependent. If the time period in standby is 3 milliseconds, for example, a 64-bit row obtains positive net power saving but negative ones are achieved for 32-bit and 16-bit rows. This means that for 32-bit and 16-bit rows, the saved leakage power within 3 milliseconds is not enough to compensate the power overhead.

Net power saving versus time period in standby mode

Time period in standby mode (ms)

0 20 40 60 80 100 120

Fig. 4.17 Net power saving of SRAM versus time period in standby mode.

Composition of power sources V_BB generator's power

Fig. 4.18 Composition of power sources.

4.2.2.4 Composition of Power Sources

Fig. 4.18 depicts the composition of power sources of a wordline with VBB

generators. The leakage power of SRAM is proportional to wordline length and the power consumption of VBB generator increases slightly with the increase of wordline length. Wider wordlines save much more leakage power and with a small fraction of increased overhead. Therefore, more net power saving is achieved when wordline length increases. Fig. 4.19 further shows that the fraction of power overhead is getting relatively smaller with the increase of wordline length.

Fraction of power sources

Wordline lengths

16-bit 32-bit 64-bit

Normalized power

0 1

V_BB generator's power SRAM leakage power

95% 92% 89%

Fig. 4.19 Fraction of power overhead for different wordline lengths.

4.2.2.5 RBB V_BBN or V_BBP Alone

Fig. 4.20 and 4.21 show the power information of using RBB VBBN or VBBP

alone for a 32-bit wordline. The net power saving of applying both VBBN and VBBP is about 64%, while the net power saving of applying VBBN alone is about 64.5%. This result demonstrates that VBBP generator has less significant effect on leakage saving.

The information of applying VBBP alone shown in Fig. 4.20 and Fig. 4.21 supports this result.

Net power saving (32-bit wordline)

Time period in standby mode (ms)

0 20 40 60 80 100 120

Fig. 4.20 Effectiveness of net power saving for VBBN or VBBP alone.

Net power saving (32-bit wordline)

Conventional Both Vbb Vbbn only Vbbp only - 64% - 64.5%

+ 9%

Fig. 4.21 Power information for VBBN or VBBP alone.

Fig. 4.20 and Fig. 4.21 show that no positive net power saving is possible if RBB VBBP is applied alone, due to the remaining leakage power plus power overhead exceed the nominal leakage power. In comparison with the conditions of using both VBB generators and VBBN generator alone, the prior condition obtains more leakage power saving but more power overhead induced by VBB generators. Therefore, it’s another solution to apply RBB VBBN alone and the net power saving is slightly larger.