Chapter 5 Power-Gating Technique In Ultra-Low Power SRAM Cell Array
5.7 Three Typical Schemes for Comparison
5.7.8 Area Overhead Due to Extra Devices
Since the new scheme includes some extra devices, the area overhead must be taken into account. Fig. 5.25 compares the area of conventional and new scheme for several block sizes. Fig. 5.25 shows that the area for 8-bit block scheme is much larger than the others because of more AND gates and gating devices. Besides, the overhead percentage keeps constant with various lengths of wordlines.
Wordline length
Fig. 5.25 Area comparison of conventional and new scheme with different block sizes.
Fig. 5.26 summarizes the area overhead for different block sizes. For an 8-bit block wordline, about 54% area overhead comes from the AND gates since in this situation the gating devices are smaller, and totally a 20.7% area increase is presented.
For a 16-bit wordline, however, a total 12.1% area increase is obtained and about 44%
of it comes from the AND gates. Finally, for a 32-bit block wordline, a total 8.1% area overhead is induced and only 34% of it comes from the AND gates. Fig. Although the overall area overhead is getting less severe with larger block size, the influence of gating devices is getting severe and the AND gates are becoming less significant. This is because that the number of AND gates is becoming fewer while the sizes of gating devices are becoming larger.
Block size
Fig. 5.26 Summary of area overhead.
5.8 Conclusion
The design issues of gated-VDD SRAM are discussed and some prior designs are introduced in this chapter. Moreover, an ultra-low active-power gated-VDD SRAM architecture is realized.
The column/row co-controlled scheme divides the SRAM cells on the same wordline into blocks, and one gating device is responsible for one block. The cell active power of the scheme is much smaller than the other two schemes compared.
Simulation also shows that the scheme achieves a significant reduction of power-delay product. This demonstrates the effectiveness of this new scheme in reducing active power consumption with insignificant performance degradation.
The layout is implemented with 0.13um CMOS technology, and a SRAM cell occupies an area of about 2.40um x 1.91um. The new scheme has larger silicon area because of the extra AND gates and gating devices. About 20.7% and 12.1% area increases are obtained for 8-bit block and 16-bit block situations, respectively.
Besides, only 8.1% area overhead is induced for 32-bit block condition.
Chapter 6 Conclusions
As technology continues to scale down, subthreshold leakage is becoming worse and it has the potential to dominate the whole power consumption of a chip. Many researches and predictions have showed that leakage power is becoming comparable with dynamic power in nano-scale technologies. In the past, leakage currents are ignored because they are insignificant compared to dynamic currents, since threshold voltage is high. In the deep-submicron and nano-scale technologies, however, IC designers must pay much more attention to leakage currents and some circuit techniques and design considerations must be developed to control leakage currents in both active and standby modes.
The dominant leakage source, subthreshold current, increases exponentially with the scaling of threshold voltage. Therefore, many techniques that dynamically adjust threshold voltage by applying body bias are developed in recent decades. Threshold voltage is raised with reversed body bias, while it’s lowered with the application of forward body bias. Power gating is another popular technique to suppress leakage current in standby mode. It inserts sleep transistors between virtual and real power lines and those transistors are turned on in active mode and turned off in standby mode. In standby mode, the leakage currents are reduced due to the stacking of off transistors. All the low power design techniques have been reviewed in Chapter 2.
In this thesis dynamic body-biasing and power-gating techniques are investigated and applied to SRAM cell arrays to observe the effectiveness in suppressing leakage.
Notice that this thesis focuses on applying reversed body bias and the reduction of leakage currents. For the purpose of flexibility and reusability in SoC systems, a configurable scheme for generating multi-level body-bias voltages is presented in Chapter 3 and various voltage levels can be produced through control signals. For SoC designs, several supply and body-bias voltages are necessary for biasing different parts of the designs. Therefore, an on-chip configurable voltage generator is quite useful since no other kinds of voltage generators are required. Besides, another dual-level body bias generator is also constructed in Chapter 4 and it produces two voltage levels according to control signal. The dual-level body bias generator is applied to SRAM cell arrays and a great amount of leakage saving in standby mode is observed. Moreover, the net standby power saving is significant even the power overhead of body bias generator is included. The average power consumption of body bias generator converges with time so that the net power saving is time dependent.
Simulation results show that about 75% net power saving is achieved for 64-bit wordline and 64% for 32-bit wordline. A time-out-policy controller that monitors the
activities of wordline signals controls the body bias generator. The controller detects the activities of wordline signals and filters out short standby periods. Body bias generators are enabled if no active wordline occurs within predetermined time period.
In the rest of this thesis, power-gating technique is applied to SRAM cell array designs, and a low active and standby power SRAM scheme is presented. The gating devices are controlled by signals from both column and row decoders and only selected cells are power-on. The SRAM cells on the same wordline are divided into blocks and each block shares a common gating devices. For each read/write operation, only selected block is power-on and others are power-gated. Simulation results show that for 64-bit wordlines, 59% active power saving is achieved for 32-bit block, 79%
for 16-bit block, and 94% for 8-bit block conditions. However, this scheme induces area overhead since some extra AND gates and gating devices are added. About 20.7% and 12.1% area increases are obtained for 8-bit block and 16-bit block conditions, respectively. Besides, only 8.1% area overhead is induced for 32-bit block condition. Although the AND gates induce performance overhead, power-delay produces demonstrate that the influences are insignificant.
The configurable body-bias generator in Chapter 3 is simulated in TSMC 100nm technology, while the simulations and physical layout in Chapter 4 and 5 are based on TSMC 0.13um technology.
References
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Vita
PERSONAL INFORMATION Birthdate: September 19, 1980 Birthplace: Tainan, Taiwan, R.O.C.
Address: Department of Electronics Engineering National Chiao Tung University
1001 Ta-Hsueh Rd.
Hsinchu, Taiwan, 30050, R.O.C.
E-mail address: cruiser.ee91g@nctu.edu.tw
EDUCATION
B.S. [2002] Department of Electrical Engineering, National Central University.
M.A. [2004] Institute of Electronics, National Chiao-Tung University.