The Design and Analysis of Dual-Delay Path Ring Oscillators
3.3 Two Operation Modes in Dual-Delay Path Ring Oscillator
3.3.2 Common-mode oscillation
Figure 3.7 Schematic of the differential four-stage dual-delay path ring oscillator in common-mode oscillation.
In dual-delay path ring oscillators under common-mode oscillation the output waveform of each delay cell becomes in-phased instead of differential phased. As illustrated in figure 3.5(b), the output waveforms AI and A`I of figure 3.1 are in-phased, so are BI and B`I , AQ
and A`Q, BQ and B`Q. Refer to the delay cell schematic in figure 3.4, we expect the CMOS latch constructed by M5 and M6 to drive the delay cell outputs differentially. However in common mode each delay cells are found to be in-phased instead of differential phased, thus suppose the latching part of the delay cell is not working properly and a new main-delay path dominates the oscillation. In figure 3.7, the scheme of the differential four-stage dual-delay path ring oscillator operating in common mode is shown. We omitted the other half circuit since the outputs of each delay cells are in-phased and the other half circuit operates in a complete same manner.
Figure 3.7 can be further represented as figure 3.8. Where figure 3.8(a) shows a differential two-stage ring oscillator, the schematic of each delay cell block is shown in figure 3.8(b). Here we find a differential four-stage dual-delay path ring oscillator operating in common mode is equivalent to a differential two-stage ring oscillator with no additional-delay paths. The internal nodes in figure 3.1 are indicated in figure 3.8(a). Note in figure 3.8(b), the transistors M5 and M6 constructs diode connection and is equivalent to a positive resistance. But shown in figure 3.4, they construct a CMOS latch which is equivalent to a negative resistance in differential-mode oscillation. Moreover in figure 3.8(b), the transistors M7 and M8 constitute a CMOS latch but in differential-mode oscillation they constitute the additional-delay paths. Now, by applying the first-order
small-signal model, the oscillation frequency and oscillation criterion of the two-stage ring oscillator can be derived.
A`I A I
A Q
B I ( )B`I ( )
( )A`Q ( )B`Q B Q
(a)
Vcont
Vout+
V out-Vin+ M1 M3
M7 M5
VDD
Vcont
V in-M8 M6
M4 M2
(b)
Figure 3.8 (a) A differential two-stage ring oscillator. (b) Schematic of the delay cell.
−V
Figure 3.9 (a) Simple half circuit small-signal model of a delay cell. (b) The phasor diagram of the signals Vin,
Vout and currents I1, I7.
Figure 3.9(a) is the simple half circuit small-signal model of the delay cell shown in figure 3.8(b). Transistors M3 and M4 are neglected and not included in this model for simplicity. gm1 and gm7 represent the transconductance of M1 and M7, respectively. Req
represents the total equivalent output resistance at the output node, which includes the transistors drain resistance Ro in parallel with the diode connection resistance 1/gm5
presented by M5,6. CL represents the total loading capacitance at the output node. Vin and Vout are the input and output signal of a single delay cell. I1 and I7 are the drain currents of the two transistors M1 and M7, respectively. The phasor diagram of the signals Vin, Vout and currents I1, I7 in stable oscillation state is illustrated in figure 3.9(b). Refer to the parameters in section 3.2, since there is no additional-delay path in the two-stage ring
oscillator, gm2 equals to 0. Further, N equals to 2 and φ equals to π/2 here. Thus from (3.1), Vin1,I=Vin1e-j(π/2)cos(π/2), Vin1,Q= Vin1sin(π/2), hence gm1,I= gm1cos(π/2), gm1,Q= gm1sin(π/2).
Furthermore, θ represents the phase difference of IT with respect to I1, where IT is the vector summation of I1 and I7. Now, the transfer function H(jω) between Vin and Vout of the single stage delay cell in figure 3.9(a) can be derived as
eq
moreover the criterion for oscillation is expressed as
7
m eq 1
g ⋅R = . (3.20)
In summary, a two-stage ring oscillator requires equation (3.20) to be satisfied, and the oscillation frequency will be as derived in (3.19). To be noted, the gm7 term corresponds to
the strength of CMOS latch constructed by the transistors M7 and M8, in figure 3.8(b). As mentioned before if the latch becomes strong the delay time increases thus reduces the oscillation frequency, this can be interpreted in (3.19) as well.
Finally, from the above derivation, the frequency and oscillation criterion of both oscillation modes in a differential four-stage ring oscillator has been derived. It should be noted here, depending on the initial conditions and components in the system, the dual-delay path ring oscillator can generate a steady-state oscillation in either differential mode or common mode, even without the CMOS latch circuit constructed by M5 and M6, in figure 3.4. In order to insure a particular oscillation mode the system must satisfy two conditions [22]. First, it should have enough energy to force the system outside its initial region of attraction. The second condition is that the energy should be applied in such a way that the nonlinear dynamical system moves towards the intended steady-state stable mode. Therefore, if we wish to operate the oscillator in the differential mode, we can either apply initial conditions in the system or design the components in the oscillator to prevent common-mode oscillation. From (3.20), if the value gm7Ro is designed to be less than unity, common-mode oscillation will never occur. However, to insure gm7Ro less than unity gm7
will be small, but shown in (3.16), smaller gm7 reduces the oscillation frequency in differential-mode oscillation. Another choice is to design the circuit to have much larger
loop gain in differential mode than in common mode at the oscillation frequency of each case, from (3.15) and (3.18) that is
m1 o
5 m
m7 o
5 m
-1
1 2
g R
g g R
g //
//
⎛ ⎞
⋅ ⎜⎝ ⎟⎠ >> ⋅ ⎜⎛ ⎞⎟
⎝ ⎠
. (3.21)
In practice, 5 to 10 times for the ratio of the differential-mode to common-mode loop gain should be sufficient to ensure differential-mode oscillation.