Experimental Results

Digital Control Circuit Delay Line 1

vco

PFD + CP + LPF2 Divider

Figure 4.20 Die photo of the frequency synthesizer.

The proposed frequency synthesizer is fabricated in a 0.18-μm CMOS technology. The die photo of the chip is shown in figure 4.20. The die area is 0.92 mm × 1.15 mm (1 mm²) including the measurement pads. The chip is tested on an evaluation printed circuit board.

The total power consumption is 27.2 mW. All digital control signals are supplied through the three-wire serial interface, and the reference frequency used is 35 MHz.

The frequency synthesizer is tested in four different operation modes: without multiphase compensation method, multiphase compensation without DEM techniques, multiphase compensation with DWA and, multiphase compensation with DWAinc, respectively. Figure 4.21 shows the frequency synthesizer output spectrum in locked condition. Figure 4.22 shows the synthesizer output phase noise, with and without multiphase compensation. As shown in figure 4.22, with quantization noise compensation technique, a 10-dB reduction of phase noise at the offset frequency of 10 MHz from a 2.14 GHz carrier signal can be achieved. The 10-dB reduction rather than an 18-dB reduction is caused by the high noise floor at 10 MHz frequency offset rather than the quantization noise.

Figure 4.21 Output spectrum of the frequency synthesizer.

Figure 4.22 Phase noise measurement results, without multiphase compensation (light) and with multiphase

compensation (dark) and.

For the measurement results of multiphase compensation method with DEM techniques activated and deactivated, the measured in-band noise floor is -82 dBc/Hz for all three compensation modes. These measurement results correspond to an amount of up to 40%

delay mismatches. Therefore, possible noise sources, such like noise from CP current source, nonlinear PFD+CP I/O characteristic and, digital circuit noise, might have been folded back to low offset frequencies and thus dominates the in-band noise.

Although the in-band noise now dominates by various noise sources rather than multiphase mismatch, in order to demonstrate the effect of DEM techniques, the measured

phase noise performance improvement can be observed by manually setting signal Vc=0.7.

Note, in ordinary, Vc is generated by the locked delay-locked loop. The idea here is to manually lower the potential of Vc to increase the delay time mismatches, which has been verified in transistor-level simulations. Shown in figure 4.23(a), 10-dB in-band noise increment due to multiphase compensation without DEM technique is detected compared to the case with no compensation applied. In figure 4.23(b), shows a 4-dB in-band noise reduction due to DWA technique compared to the case with no DEM technique applied.

Also, a fractional tone ffref/2 appears when DWA is activated. Finally, in figure 4.23(c), compared to DWA a little in-band noise increment is shown in DWAinc technique with a 7-dB suppression on the ffref/2 tone. Table 4.2 summaries the measured performances.

(a)

(b)

(c)

Figure 4.23. Measurement results of output phase noise, with Vc manually set to 0.7 V. (a) No compensation

applied (light) and, compensation applied without DEM technique (dark). (b) Compensation applied without

DEM technique (light) and, Compensation applied with DWA technique (dark). (c) Compensation applied with

DWA technique (light) and, Compensation applied with DWAinc technique (dark).

Table 4.2 Measured performance summary.

4.6 Conclusion

In this work, a multiphase quantization noise suppression technique for fractional-N frequency synthesizers is proposed and demonstrated in 0.18-μm CMOS technology. The experimental results show the out-of-band phase noise contributed by the modulator is reduced by 10 dB, where the out-of-band phase is dominated by the quantization noise.

The phase noise cancellation technique relaxes the fundamental tradeoff between phase noise and bandwidth in conventional fractional-N frequency synthesizers and does not

require tight component matching. The measurement results show -82 dBc/Hz in-band phase noise within the loop bandwidth of 200 kHz, and -103 dBc/Hz and -132 dBc/Hz out-of-band phase noise at 1 MHz and 10 MHz offset from a 2.14 GHz center frequency.

The lock time is less than 25 μs.

Chapter 5 Conclusions

5.1 Conclusions

A dual-delay path ring oscillator is implemented. The oscillation frequency increment due to additional-delay paths in ring oscillators is derived. The two oscillation mode in differential four-stage dual-delay path ring oscillators is analyzed and demonstrated. The main difference of the two oscillation modes is the output waveform characteristic. Instead of typical differential outputs, the outputs of a delay cell become in-phased. Furthermore, the oscillation frequencies in the two oscillation modes are shown to be different. This dual-delay path ring oscillator is implemented by a 0.18-μm CMOS technology with an active area of 58×41 μm².

A multiphase quantization noise suppression technique for fractional-N frequency synthesizers is proposed. A re-quantized Σ-Δ Modulator is implemented to overcome the

nonidea effect of delay units gain error. Dynamic element matching techniques are also employed for element mismatch linearization. The phase noise cancellation technique relaxes the fundamental tradeoff between phase noise and bandwidth in conventional fractional-N frequency synthesizers and does not require tight component matching. This frequency synthesizer is implemented by a 0.18-μm CMOS technology with an area of 0.92

× 1.15 mm².

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