Dynamic Element Matching Technique

Refer to the subcircuit model shown in figure 4.4(b), ideally all the delay units are equal with a delay time τ, but due to mismatches, they have a random distribution. To simplify the analysis, only the effect of delay mismatch mi is considered. During each reference cycle, certain amount of subcircuits in delay line 1 is selected. The selected subcircuits operate with its slow path which contributes an additional delay time for compensating the quantization noise. A mismatch value m[k] can be defined as the deviation time from the ideal delay time at the output of delay line 1. Thus, m[k] can be equivalently derived by summing up all mi of the delay units in each selected subcircuit. A simplest way of choosing the subcircuits is by thermometer code. Therefore, the mismatch value at the delay line 1 output can be described as

-1

where pi[k] is a one-bit signal that controls the i^th subcircuit in delay line 1, and has the value of either 0 or 1. If pi[k] equals to 0, the subcircuit operates with its fast path, on the other hand, if pi[k] equals to 1, the subcircuit operates with its slow path. Assume p[k] is a random number, and the multiphase mismatch value m[k] in (4.20) can be modeled as a random process with white noise spectrum. Thus, the noise power caused by multiphase mismatch of delay line 1 can be obtained as

2 2

where σm represents the standard diviation of m[k]. And the effect of mismatch noise to the frequency synthesizer output can be derived as

ou

From (4.22), if the subcircuits are chosen by thermometer code, the mismatch noise m[k]

in spectrum will be a flat noise that causes in-band noise and spurious tones at the frequency synthesizer output.

p₁ p₂ p₃ p₄ p₅ p₆ p₇

Figure 4.8 (a) Example of data weighted averaging algorithm. (b) Example of data weighted averaging

algorithm with increased index.

Dynamic element matching is a technique for oversampled digital to analog converters to improve their linearity. The purpose of DEM is to select elements such that mismatch noise can be pushed away to high offset frequency where it can be removed by filtering.

As shown in figure 4.2 and figure 4.3, in the proposed multiphase compensation frequency

synthesizer with delay line 1, DEM techniques can be employed to select the subcircuit in delay line 1 to push the mismatch noise to high offset frequencies.

Many DEM algorithms, including random selection, individual level averaging, data weighted averaging [25], and segmented encoder [27], were reported. In the proposed frequency synthesizer, a DEM technique utilizing data weighted averaging (DWA) is employed to yield a first-order shaping of the mismatch noise. In figure 4.8(a), the selection of the subcircuits in DWA is shown. For convenience, eight subcircuits are used in this example. During each clock cycle, a number of subcircuit corresponding to the input code p[k] is selected clockwise, starting from the position indicated by a pointer ptr, with 0≦ptr<L, where L is the number of subcircuits in delay line 1. At each clock cycle, the pointer is updated by incremented modulo L with the input code. On the next cycle, the selection will start from the new position of the pointer. The concept is to select all the delay units in the fasted way, since the sum of the mismatch of all delay units is zero. This ensures the low frequency noise components to be minimized. Mathematically, the mismatch noise m[k] due to DWA selection can be expressed as [24] [25]

1 1 1

The function IM[ptr], called integral mismatch, corresponds to the mismatches of the delay units accumulated along the array up to the position of the pointer. Now the power spectrum of the mismatch noise in (4.23) can be written as

( )

Where, the integral mismatch function IM[ptr] is assumed to be white random process with a standard deviation σm. Therefore, the effect of mismatch noise to the frequency synthesizer output can be derived as

( )

While DWA has the advantage of noise shaping the spectrum of delay mismatches, it also creates spurious tone. A Fref/2 tone has been observed in behavioral simulations. This fractional tone occurs because the average number of subcircuits selected to operate with slow path in a reference cycle is L/2. Thus, all subcircuits in delay line 1 will be selected once in an average of two reference cycles. Further, since the sum of the mismatch of all delay units is zero, a periodic mismatch noise of period 2Tref occurs.

To resolve this problem, a simple modification in DWA mechanism has been presented, named data weighted algorithm with increased index (DWAinc). In figure 4.8(b), the selection of the subcircuits in DWAinc is shown. The algorithm of DWAinc is similar to DWA. In addition to the pointer ptr, another pointer ptri is applied, same with 0≦ptri<L.

Initially, ptri is set to zero, during each clock cycle, if ptr is not equal to ptri, the subcircuit selection will be the same as DWA. But if ptr equals to ptri at the beginning of a clock cycle, a random number will be assigned to both ptr and ptri, and the subcircuit selection will continue by the new ptr. For example, in figure 4.8(b), initially both ptr and ptri are 0, the selection starts from the subcircuit p0 and proceeds in a rotational manner such as DWA. However, in the fifth clock cycle, the subcircuit selection ends at p7 and sets ptr to zero. Therefore, at the beginning of the sixth clock cycle an equivalent value of ptr and ptri

is detected, thus a new random value 2 is assigned to them and the subcircuit selection proceeds from p2. In behavioral simulation, great reduction on the Fref/2 tone has been detected, with the expense of little in-band noise increment compared to DWA. But still much lower than those with no dynamic element match technique applied.

DWA / DWA_inc

Figure 4.9 Architecture of the proposed digital control circuit with DEM block.

T G(f )

Figure 4.10 Linear model of a multiphase compensation Σ-Δ frequency synthesizer.

Figure 4.9 shows the proposed digital control circuit with DEM block. The two DEM algorithms, DWA and DWAinc are both built in the digital control circuit. Finally, figure 4.10 shows a linear model of multiphase compensation Σ-Δ fractional-N frequency

synthesizers, including the effect of quantization noise, multiphase mismatch and delay unit gain error.