Chapter 3 Design of the Ultra-wideband LNA and Correlator
3.4 Conclusion
In this chapter we have designed and implemented a UWB LNA and a correlator individually. The LNA uses transformer feedback matching and current reuse technique
to achieve good input matching, noise figure, and gain performance. Because of complete layout consideration and post simulation, the measurement results of LNA show that they are similar to simulation results. It indicates that the transformer feedback topology is feasible for broadband matching. With respect to the correlator, bandwidth extension and dynamic gain control techniques are used in this design. Due to imperfect measurement consideration and signal source, the measured results are more different than simulations. However, it is convinced that these design concepts are suitable in the coherent receiver of IR-UWB systems.
Chapter 4
An Integrated Front-end Receiver for IR-UWB Wireless Communication Systems
4.1 Overview
In this chapter we present a fully integrated front-end receiver of System-On-Chip (SOC) implementation for impulse-radio UWB communication systems. The block diagram is shown in Fig.4-1. It comprises a wideband LNA, a pulse generator, and a correlator. The LNA with transformer feedback and current-reuse topology can accomplish good input matching, low noise figure, and low power consumption. The 2nd –order derivative Gaussian pulse generator used for generating template waveforms applied to correlate the received signal. The correlator works as multiplication and doubly integration to demodulate the received signals. The overall integrated circuit is fabricated by TSMC 0.18-μm 1P6M CMOS technology and has 19.96-mW total power consumption with 1.48 mm2 chip area. In this chapter, we only introduce the design concepts of pulse generator and correlator (for LNA has been demonstrated in Chapter 3). The clock timing of the coherent receiver must to be discussed because of synchronization. Finally, we also introduce the measurement environment and exhibit the simulation and measured results.
Baseband Signal Processor
TX/RX Switch
Figure 4-1 System architecture of IR-UWB transceiver (dash line indicates RX front end)
4.2 Switched 2nd-order derivative Gaussian Pulse Generator
In order to generate a local 2nd-order Gaussian pulse, the pulse generator (PG) comprises three cascade stages to realize the square, exponential, and second-order derivative functions, respectively [25]. The illustration is shown in Fig.4-2. Based on Fig.4-2, we propose that switched pulse generator (WSG) applied in this receiver. WSG has low-power property because there is nearly no static power consumption. The circuit is shown in Fig.4-3, including a clock shaping, a transient circuit, and a 2nd-order derivative circuit. First, in order to achieve a more ideal clock signal for next stage, the clock shaping network consists of four-cascaded inverters which can improve the rise/fall time of the clock signal in the sub-nanosecond range. The simulation waveforms are shown in Fig.4-4. The black line indicates non-ideal clock waveform, whose rise and fall time are both 1.5ns and period is 10ns. The modified clock by shaping circuit is presented in gray line and the rise time is less than 100ps. Although the amplitude of modified clock degrades slightly compared to the original clock signal, but it is enough to drive accurately for circuits of next stage. The simulation results shows the practical clock becomes more ideal clock by a shaping circuit made of four-cascaded inverters.
e
−x( )
2 d xdt
2
2 G t2( )
V t
in( )
Figure 4-2 Block diagram of the generation of the 2nd-order derivative Gaussian pulse
{ { {nd2
Figure 4-3 Schematic of 2nd-order derivative Gaussian pulse generator
Figure 4-4 Non-ideal clock and clock after shaping
As for the transient circuit, the common-gate stage (M1) works as a switch. When
clock is in negative half-period, turns on and the current only flows through
but not . When is changing from the negative to the positive state, becomes cut off and the impedance looking in is very small. At the short duration, the current flows through the series circuit and forms an impulse in [26].
The impulse is shown in Fig.4-5 and the width is about 200ps. The small resistor is used for reducing ringing of the impulse.
Vs
Finally, in the 2nd-order derivative circuit, is driven only when its gate voltage is at positive edge. The cascode stage does not have current flow for the rest of the impulse period. The main second-order derivation function is implemented by the network. The trans-impedance of the RLC network in the s-domain is derived as
If assuming the load impedance of as 50Ω and choosing proper LC values which satisfy with the UWB frequency range of interest, Equation (4-1) can be approximated by
Rp +sLp <<1/sC
R
p pI
ds3( ) s
(4-2)The output voltage represents the second derivative of the drain current . Besides, to generate the opposite pulses at the same time for the differential correlator, another parallel path is connected an extra inverter to form a negative pulse for PMOS cascode stage. The negative impulse is shown in Fig.4-6. network is added for the same purpose for network. The final positive/negative waveforms are shown in Fig.4-7 and Fig.4-8.
Vout_ Ids3
n n nLC R
Figure 4-5 Simulation positive impulse generated in Vx_p
Figure 4-6 Simulation negative impulse generated in Vx n_
Figure 4-7 Simulation positive 2nd –order Gaussian pulse
Figure 4-8 Simulation negative 2nd –order Gaussian pulse
4.3 Doubly-Integration, Inductorless, Wideband Correlator
In the previous chapter we have proposed a correlator based on a Gilbert-cell. With dominant pole at the internal node being cancelled, the bandwidth can be increased.
However, as a result of the three stacked layer used in the configuration, the Gilbert cell always includes issues of complex pole-zero arrangements, low signal swing, in-band flatness issues as well as bias issues [27]. Due to the transistor operation mode, power consumption is another issue and a new multiplier configuration is need for efficient implementation of UWB systems. To accomplish this design, we apply the four-quadrant multiplier implementation, inductor-less technique, and bandwidth enhancement for the UWB correlator. The simplified block diagram is shown in Fig.4-9.
Figure 4-9 Simplified diagram of the proposed correlator
Figure 4-10 Schematic of the proposed correlator
A fully differential four-quadrant multiplier and doubly-integrated mechanism has been proposed in this design. The schematic of circuit is shown in Fig. 4-10. In order to avoid extra single-to-differential balun between the LNA and the correlator, the negative RF input terminal is connected a DC voltage reference and a bypass capacitor is added in it. NMOS M1 to M4 operate in triode region and this kind of current is followers. The output current can be presented as [28]
(4-3)
Similarly, . According to the above equations we can get the
Consequently, the output comprises the product of two input signals where
DSP DS y
v =V + v , vDSN =VDS −vy, VDS is DC biasing when
v
x= v
y= 0
.The differential outputs of local template pulses are generated by the pulse generator. The capacitor is set up between the differential outputs of the quadrant multiplier. Switch resets the data at the later half-period waiting for the coming of the next data. The signal after first-time integration still has apparent drop and does not last for a long time, so we exploit zero-pole cancelling topology [29] to reach bandwidth extension and double integration simultaneously.
Cint
Figure 4-11 (a) Illustration of frequency compensation skill with zero-pole cancelling (b) Small-signal equivalent model
From Fig.4-11, the method is realized by and . The appropriate C value and transistor size of can be chosen for frequency compensation. Assume the transfer function
get
While is the equivalent linear resistor resulting from operating in triode region, the value is
According to these equations above, we can make the zero to cancel the dominate pole efficiently for bandwidth enhancement. Additionally, the second-time integration is accomplished simultaneously.
Figure 4-12 The biasing circuit for constant transconductance
In addition, to design a robust correlator, the active load of the operational amplifier must be of high stability. Therefore, a constant transconductance [30] circuit has been added to drive the active load, which is shown as Fig.4-12. The output DC voltage Vdc can be deduced as
(4-9)
The coherent receiver needs for very precisely timing. For example, the clock timing for the pulse generator, integrator, and ADC is illustrated in Fig.4-13. In each period, once the clock rising edge for the pulse generator is synchronized with the received pulse, the multiplied pulse is then produced and the integrator is synchronized with the received pulse, starting integrating operation. A half period of time is used for integration, and the rest time is used for discharging. By the way, the tracking time of the ADC is about one quarter of period ahead of the discharging time, so a stable sampling can be achieved.
Figure 4-13 The clock timing of the receiver circuit
4.4 Layout Consideration and Simulation Results
Aspect for simulation, we replicate a second-order derivative of Gaussian pulse as the input signal. From Fig.4-14 it shows that the received weak signals can be amplified by the LNA with little distortion. It means that the LNA with transformer feedback matching has broadband characteristic. The voltage gain of LNA is around 17dB. The simulation of differential waveforms of the pulse generator is shown in Fig.4-15(a). An extremely narrow pulse width of 260ps is resulted and the peak value is 220mV, which is suitable for high data-rate transmission. The spectrum spread by pulse is also shown in Fig.4-15(b). The simulation correlated waveform is shown in Fig.4-16. The peak value is 125mV, rise time is close to 1.0ns, fall time is 1.6ns, and hold time is 3.2ns when pulse repetition rate is 110MHz. The spectrum of output waveforms only has two dominant signals, which are DC and 110MHz. The result indicates that the coherent architecture is a type of direct-conversion receiver.
As for the layout plan, short metal-line connection is the prior consideration because of avoiding uncertainly parasitic effects. Fig.4-17 shows the layout of the integrated circuit. The distance between the transformer of LNA and other transmission lines is away from 50um at least. This manner is for reducing large coupling effect. The layout of PG is located at the lower section of Fig. 4-17. The proposed correlator is an inductor-less circuit, so it can minimize the overall chip area. In order to measure output waveform by the oscilloscope, the output resistance must be 50 ohm. The architecture of open drain is used for the sake of measurement. Serial MIM capacitors which replace transmission lines not only add by-pass capacitance but also reduce parasitic influence of long metal lines. The overall area occupies 1.23mm×1.2mm including pads.
Figure 4-14 Received pulse and amplified pulse by LNA
(a) (b)
Figure 4-15 (a) Differential output of pulse generator (b) Spectrum allocation
Figure 4-16 Output waveforms
Figure 4-17 Layout of the proposed front-end receiver
4.5 Measurement Results
4.5.1 Measurement Environment
Referring to measurement consideration, we adopt on-wafer probing. The overall measurement environment is shown as Fig.4-18. The LNA input port is fed by the 2nd-order Gaussian pulses generated from a practical generator, whose photo and experimental waveform is shown in Fig.4-19. The clock signal which amplitude is ± 1.8V feeding the input port of the pulse generator. The switch port is connected to the clock signal which delay half a period of the clock of pulse generator. The pulse repetition rate is 110MHz at the overall demonstrative measurement. Besides, in order to measure the output waveform, the output buffer adopts the open-drain stage to match
DC pads
DC pads S1
out+
out
-RF_in
clock
50Ω. Thence we must add extra bias-tee at the output port. The bias tee is a three port network; RF is fed into one port and DC into another, while RF and DC depart together from the third port. The bias-tee needs large driving current for good matching.
Figure 4-18 Diagram of measurement setup
(a) (b)
Figure 4-19 (a) Practical 2nd-order Gaussian pulse generator (b) Measured waveform
4.5.2 Measurement Results and Discussion
An integrated pulse based UWB receiver using the coherent architecture is fabricated by TSMC 0.18μm RF CMOS process. The die microphotograph is shown in
Fig.4-21 with chip size 1.48 . The measured differential output waveform is shown in Fig.4-22. We observe that the rise time is around 1.8ns, the fall time is 1.3ns, and the hold time is 2.2ns. The peaked amplitude of output waveform is 140mV when the input peaked value is 40mV. Except from the pulse shaping circuit of the pulse generator and the output buffer, the core power consumption is 19.96mW with 110MHz pulse repetition rate. The summary of the simulation and measurement results is list in Table 4-1. It can be observed that the rise time of simulation is faster than practical experiment, but the fall time of simulation is slower than experiment. The reasonable explanation may be that the actual parasitic capacitance at the charging path is more than the predicted value and leads to large RC time constant. At the discharging path, these switches consisting of transistors are controlled by an independent signal, so the practical fall time is shorter than simulation. However, we can still demonstrate that the front-end receiver works functionally.
mm2
Figure 4-20 Microphotograph of the proposed front-end receiver
Time (5ns/div)
-0.05 0 0.05 0.1 0.15 0.2
Amplitude (0.05V/div)
Figure 4-21 Measured output waveforms
Table 4-1 Comparison of simulation and measurement results of the receiver Simulation results Measurement results
Technology TSMC 1P6M 0.18μm
Supply voltage(VDD) 1.8 V
Operating frequency ~10GHz
Pulse repetition rate 110 MHz
Pulse width 260 ps
Max. Vout amplitude 126 mV 140 mV
Rise time 1.0 ns 1.8 ns
Hold time 3.2 ns 2.2 ns
Fall time 1.6 ns 1.3 ns
Power consumption (core)
@100MHz UWB pulse repetition rate
18.34 mW 19.96 mW
Chip area 1.228mm×1.205mm
Chapter 5
Conclusion and Future Works
5.1 Conclusion
Ultra-wideband is a promising technique which possesses low power consumption and high data rate. Due to the outstanding characteristics of UWB, we focus on researching the receiver design and implementation. In Chapter 3, the proposed LNA and correlator used in UWB systems are introduced. The LNA exploits transformer feedback matching instead of the conventional matching method to achieve broadband matching and acceptable noise performance. As to gain stage, current-reuse technique reduces dissipation and obtains adequate gain simultaneously. The measured results show that S11, S21, S22 are similar to simulation results. The average NF is 4 dB. The minimum IIP3 is -5 dBm. It illustrates that the topology is feasible in UWB system.
Referring to the correlator, the Gilbert multiplier is adopted and inductive peaking of the load stage is used for achieving wideband feature. Variable gain control is another feature at the correlator. Besides, double integration is used for longer hold time for circuits of the next stage. The practical measured results show that the rise time and hold time are inferior to simulation performance. The dynamic gain range of measurement is 36-89mV, which is also lower than simulation. The reason may be due to bond wire at each port or imperfect pulse source. But the performance has the trend to match the expectative result as well.
Finally, the integrated front-end receiver is presented in Chapter 4. The proposed front end of receiver which comprises a UWB LNA, a 2nd-order derivative Gaussian pulse generator, and a wideband correlator is presented. The switched pulse generator is applied for reducing static power dissipation. Differential output is designed for the
purpose as template pulse of the receiver. The double integration correlator has long enough hold time for next stage, and the inductorless architecture can reduce the overall chip area and achieve broadband characteristic simultaneously. The proposed receiver front end had been integrated in a single chip by TSMC 0.18μm process. The measured results demonstrate that the front-end receiver can achieve a transmission rate over to 110Mb/s, and it conforms to the characteristic of the desired transmission rate in the IR-UWB communication systems.
5.2 Future works
IR-UWB communication systems have many unusual advantages compared with conventional communication systems, such as low complexity, low duty cycle, high immunity to other interference and high security. These features are much deserved to research for advanced specification. Although IEEE 802.15.3a standard is announced that the task group disbanded in 2006, but many industrial and academic organizations still go for investigation in this field. It can be expected that UWB systems can be accepted extensively in wireless-communication life. In the short term, we will develop toward chip integration by the advanced CMOS process. In this thesis, a prototype of the front-end receiver of IR-UWB systems is proposed. We hope that the achievement can provide a good design guide of IR-UWB communication systems.
Reference
[1] Multispectral Solutions, Inc. History of UWB Technology, “A Brief History of UWB Communications,” http://www.multispectral.com/history.html
[2] IEEE 802.15 WPAN High Tate Alternative PHY Task Group 3a(TG3a)[Online].
Available: http://www.ieee802.org/15/pub/TG3a.html
[3] G. R. Aiello, G. D. Rogerson, “Ultra-wideband wireless systems,” IEEE Microwave Mag., vol.4, pp.36-47, Feb. 2003
[4] K. Siwiak, “Ultra-wide band radio: Introducing a new technology,” in Proc. IEEE Vehicular Technology Conf., 2001, pp. 1088-1093
[5] B. Razavi, T. Aytur, C. Lam, F. R. Yang, K. Y. Li, R. H. Yan, H. C. Kang, C. C. Hsu, C. C. Lee, “A UWB CMOS transceiver” IEEE J. Solid-State Circuits, vol. 40, pp.
2555 – 2562, Dec. 2005
[6] J. Ryckaert, M. Badaroglu, C. Desset, V. D. Heyn, G. V. D. Plas, P. Wambacq, B. V.
Poucke, S. Donnay, “Carrier-based UWB impulse radio: simplicity, flexibility, and pulser implementation in 0.18-micron CMOS,” in IEEE International Conference on Ultra-Wideband, 2005. pp.432 - 437
[7] Ian Oppermann, UWB theory and applications, John Wiley & Sons.
[8] Paul Withington, Impulse Radio Overview, Time Domain Corporation
[9] X. Chen and S. Kiaei, “Monocycle shapes for ultra wideband system,” IEEE Proc.
of Int. Symp. Circuits And Systems (ISCAS), vol.1, pp.597-600, 2002
[10] M. Z. Win and R. A. Scholtz, “UWB time-hopping spread-spectrum impulse radio for wireless multiple access communications,” IEEE Trans. vol. 48, no 4, April 2000
[11] H. Sheng, P. Orlik, A. M. Haimovich, L. J. Cimini, Jr., J. Zhang, “On the spectral and power requirements for ultra-wideband transmission,” IEEE International Conference on Communications, vol. 1, pp.738 – 742, 2003
[12] Y. Tong, Y. Zheng, Y. P. Xu, ”A coherent ultra-wideband receiver IC system for WPAN application,” in IEEE International Conference on Ultra-Wideband, 2005.
pp.60 - 64
[13] Y. Zheng, Y. Zhang, Y. Tong, “A novel wireless interconnect technology using impulse radio for interchip communications,” IEEE Trans. Microwave Theory Tech., vol.54, pp.1912-1920, June, 2006
[14] S. R. Duenas, X. Duo, S. Yamac, S.Yamac, M. Ismail, “CMOS UWB IR Non-Coherent Receiver for RF-ID Applications,” Circuits and Systems, 2006 IEEE North-East Workshop on , June 2006, pp.213 - 216
[15] D. J. Cassan, J. R. Long, “A 1-V transformer-feedback low-noise amplifier for 5-GHz wireless LAN in 0.18-um CMOS,” IEEE J. Solid-State Circuits, vol. 38, pp.
427 – 434, Mar. 2003.
[16] C. T. Fu, C. N. Kuo, “3~11-GHz CMOS UWB LNA Using Dual Feedback for Broadband Matching,” IEEE Radio Frequency Integrated Circuits (RFIC) Symp., pp.53 – 56, 2006
[17] S. C. Blaakmeer, E. A. M. Klumperink, D. M. W. Leenaerts, B. Nauta, “A wideband Noise-Canceling CMOS LNA exploiting a transformer,” IEEE Radio Frequency Integrated Circuits (RFIC) Symp., pp.137 – 140, 2006
[18] I. Cendoya, J. D. No, B. Sedano, A. Garcia-Alonso, D. Valderas, I. Gutierrez, “A New Methodology for the On-Wafer Characterization of RF Integrated Transformers,” IEEE Trans. Microwave Theory Tech., vol.55, pp.1046-1053, May, 2007
[19] J. R. Long, “Monolithic transformers for silicon RF IC design,” IEEE J.
Solid-State Circuits, vol. 35, pp. 2259-2268, Dec. 2000.
[20] T. H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits, 2nd ed., Cambridge University Press, 2004.
[21] A. Bevilacqua, A. M. Niknejad, “An ultrawideband CMOS low-noise amplifier for 3.1-10.6-GHz wireless receivers,” IEEE J. Solid-State Circuits, vol. 39, pp.
2259-2268, Dec. 2004.
[22] K.-H. Chen, C.-K. Wang, “A 3.1-10.6 GHz CMOS cascaded two-stage distributed amplifier for ultra-wideband application,” in Proc. APASIC, Aug. 2004, pp.
296–2991
[23] C. W. Kim, M. S. Kang, P. T. Anh, H. T. Kim, S. G. Lee, “An ultra-wideband CMOS low noise amplifier for 3-5-GHz UWB system,” IEEE J. Solid-State
[23] C. W. Kim, M. S. Kang, P. T. Anh, H. T. Kim, S. G. Lee, “An ultra-wideband CMOS low noise amplifier for 3-5-GHz UWB system,” IEEE J. Solid-State