Discussion

In section 3.2, we propose a novel UWB LNA and implement successfully by TSMC 0.18μm CMOS process. This circuit uses the transformer feedback topology to realize broadband matching and noise optimization. At the gain stage, it adopts current-reuse technique to have adequate gain performance under power consumption limits. A source follower with self-biasing can reduce extra bias voltage and achieve output matching. The measured results of S11, S21, and S22 are similar to the simulation results. The measured NF is close to simulation result at the low band and only higher than simulation result about 1dB at the high band. The reason may be that parasitic resistance affects apparently at the higher frequency band. As to linearity, the maximum IIP3 is -5dBm at 6GHz while is -14dBm. It can be observed that our UWB LNA with transformer feedback has competitive performances at I/O return loss, power gain, power consumption, and even chip area.

P₁dB

3.3 Analog Correlator with Dynamic Gain Control

This section describes the circuit design principle of a correlator suitable for UWB systems. The technique of dynamic gain control is inserted for a VGA-like architecture in this correlator. The simulation and measurement results are exhibited and discussed in the final of this section.

3.3.1 Design Concepts

The function of correlator is detecting and demodulating the received signal for the following A/D converter or comparator. Normally a correlator incorporates a separate multiplier and a separate integrator. There are some main problems in designing the correlator of pulse-based UWB receiver [24]. For instance, the multiplier should have very wide-band input frequency response, even the lower band UWB pulse is very large depending on data and applications. Therefore, though the DC offset current or 1/f noise current must be much smaller than the signal current, it can integrate on the integral capacitor for a much longer time the multiplied signal. Another problem is that after the pulse correlation, the output voltage should maintain for a long time for the ADC to sample, but the output impedance of the integrator normally is not large enough, and results in large leakage from the integrator. These ultra-wideband characteristics of the input pulses make the digital domain correlation not suitable in this application.

According to above discussions, we adopt the analog correlator in UWB system receiver.

Generally multipliers are much more difficult to design than mixers. For mixers, the gain doesn’t need to vary linearly with the LO signal, and only the first harmonics of the LO is needed to multiply with the input signal. Working in linear region makes the multiplier very difficult to bias. In this design of multiplier we apply a Gilbert-cell with bandwidth extension and linear adjustment for UWB systems.

Figure 3-16 A Gilbert multiplier

Gilbert-cell multiplier is the common architecture used in communication circuit [7]. Besides circuit simplicity and high isolation, double-balanced type also has some advantages about eliminating even-mode harmonic and common-mode noise. For example in Fig.3-16, the output differential current can be expressed as follow

7 8 3 5 4 6

Based on the Gilbert-cell, we design a novel correlator with dynamic gain control, whose overall schematic of circuit is shown in Fig.3-17. The additional transistors (M ,_C1

2

MC ) are added at the source of the transconductance stage. The additional transistors operating in triode region are used as resistors and each resistance value is

1 Fig.4-18 we can know that the overall resistance looking in the source of

ro

M1 is

s o

//

ds ds

R

=

r r

≈

r , and the overall transconductance is Gm=gm/1+gmR_s, where is the intrinsic transconductance of

gm M₁ . It means that is dominantly

controlled by . Moreover, the value of can be changed by . Thereby a tunability is achieved by changing the value of the control voltage at the gate of transistor

Gm

Vctrl

rds

c

rds

M . By adjusting the magnitude of transconductance, the amplitude of output waveforms can be controlled.

Figure 3-17 Schematic of the proposed correlator circuit

rd s

ro

Figure 3-18 The transconductance stage with source degeneration

As for loading end, the correlator needs wider frequency response for UWB systems. The zero-point frequency is generated purposely to cancel the dominant pole frequency for achieving wideband characteristic. There are four transistors connecting at the load-end of the first stage, so the parasitic capacitance is large enough to form the dominant pole. The PMOS (M_L1,M_L2) with diode connecting plays the role of the load resistors whose value are R =

gm1 r_o

/ / . There are two extra advantages about diode-connected PMOS as load. First, the cross voltage is V_ov +V_th, which can make sure the next stage at the on state. Second, the correlator can be viewed as a direct conversion architecture. The interference of the flicker noise of NMOS affects the received signal deeply. For the reason, PMOS is used at the loading stage due to the lower flicker noise than NMOS.

The function of integration is to spread the multiplied signal and hold for a long time for the next stage. Generally some references apply Gm-C-OTA integrator in UWB systems [12,13]. The benefits are low voltage variation and unapparent parasitic capacitance effect, which can stabilize the integration. In order to have faster integration and shorter rise time, this architecture must need large current to drive. Besides, another parallel transconductance is used to create a feed-forward path for compensating the high-frequency response and building the rapidly rising edge of the output signal. This

architecture is good but it cost large power because of multi-stage circuits. In this design we directly add a capacitor ( ) at the differential output of the multiplier. Because ofC₁

o u t o u t

I C d V

= d t and V_out = ¹ I_outdt

C

∫

, the integration results can be achieved at the differential output of the multiplier. The method not only reduces complexity of the circuit design but also avoids extra power dissipation of separate integrators.

It can be observed that the signal after integrating operation still has apparent drop and don’t hold for a long time. Two-stage architecture is proposed in this correlator because that the second stage can amplify and integrate signal again. The mechanism is also presented in Fig.3-17. is the second integrating capacitor and locates between the differential output of the second stage. Moreover, there is a switch parallel to . The purpose of the switch is resetting the output data by controlling voltage . When the switch turns off, the circuit works normally; when the switch turns on, the differential output is short. Voltage is a square pulse train with 1.8V amplitude.

The period of is similar to input data and the duty cycle is 50%.

C2

C2

Vrst

Vrst

Vrst

(a) (b)

Figure 3-19 (a) Gm-C-OTA integrators (b) The correlator with direct integration

Finally, in order to measure the output waveform, source followers are added at the final stage for 50Ω matching (not illustrate in Fig.3-17). Unfortunately, it may generate unnecessary parasitic capacitance and degrade performance. The buffer is not needed if the correlator integrates directly to other circuits.

3.3.2 Simulation and Measurement Results

Fig.3-20 illustrates that the input signal is an ideal Gaussian monocycle, which amplitude is ±0.4V. In simulation verification the pulse repetition rate is 100MHz. The reason is for the sake of verifying the feasibility of the correlator in high data rate. The simulation output waveform is shown in Fig.3-21. In the thesis we list the definitions about rise time, fall time, and hold time. The time required for a signal to change from a specified low value to a specified high value is rise time. Typically, these values are 10% and 90% of the peak value. Corresponsively, fall time is the value of 90% and 10%

of the height. Hold time is the duration when the amplitude of signal is over 90% of the peak value. It can be observed that the rise time, fall time, and hold time are 1.3ns, 3.0ns, and 1.1ns, respectively in Fig.3-21. Different output waveforms with variation are shown in Fig.3-22. The range of output amplitude is 0.08V to 0.131V while is 0.7V to 1.8V. The output amplitude is not proportional to because of nonlinear characteristics of transistor. As to linearity, the linear input range is from -0.17V to +0.17V and has been shown in Fig.3-23. A good linearity is obtained as well.

Vctrl

Vctrl

Vctrl

The practical input signal is a Gaussian monocycle generator implemented by schottky diodes and lumped elements on the PCB. The generator is for the purpose to converts square waves to Gaussian monocycles. The photo and waveform is shown in Fig.3-24. As for the measurement setup, the chip on the PCB by wire bonding is adopted because of limits of probes. The measured results of singly-ended output waveforms are shown in Fig.3-26, 3-27. In Fig.3-26, the peak value is 44.5mV and rise

time is close to 1.8ns while repetition data rate and are 100MHz and 1.8V, respectively. Fig.3-27 shows that the peak value is 18.1mV while is 0.7V. Fig.3-28 records the different differential output amplitude versus the control voltage ranging from 0.7V to 1.8V. It can be observed that the trend is similar to simulation. Fig.3-29 shows the chip microphotograph of correlator.

Vctrl

Vctrl

Figure 3-20 Input waveforms

Figure 3-21 Simulation output waveforms

(a) (b)

Figure 3-22 Simulation (a) different output waveforms with variation (V

=0.7V~1.8V) (b) output amplitude versus Vctrl

ctrl

ctrl

V

Figure 3-23 Simulation output amplitude versus input amplitude

(a) (b)

Figure 3-24 (a) Practical monocycle pulse generator (b) Measured waveform

Figure 3-25 Photo of chip on board with bonding wire

Figure 3-26 Measured single-end output waveforms (V_ctrl = 1.8V)

Figure 3-27 Measured single-end output waveforms (V_ctrl = 0.7V)

3.62E‐02

4.72E‐02

5.86E‐02

7.02E‐02

7.94E‐02

8.52E‐028.90E‐02

0.00E+00 1.00E‐02 2.00E‐02 3.00E‐02 4.00E‐02 5.00E‐02 6.00E‐02 7.00E‐02 8.00E‐02 9.00E‐02 1.00E‐01

0.7 0.9 1.1 1.3 1.5 1.7 1.8

Vctrl variation

Vctrl variation

Figure 3-28 Measured output amplitude versus V_ctrl (V_ctrl= 0.7~1.8V)

Figure 3-29 Microphotograph of the proposed correlator

Table 3-4 Comparison of simulation and measurement results of the correlator

Simulation results Measured results

Technology TSMC 1P6M 0.18μm

Supply voltage(VDD) 1.8 V

Chip area 0.74mm×0.88mm

Repetition data rate 100MHz

Max. V_out amplitude 133 mV 89mV

Vctrl control range 0.7V~1.8V

Tuning range of output amplitude 82~133mV 36~89mV

Rise time 0.82ns 1.8ns

Hold time 3.0ns 2.9ns

Linear input range ±0.17 V Power consumption

(exclude buffer) 10.26mW 8.78mW

3.3.3 Discussion

It can be observed that the measured results do not achieve expectation. We consider that the imperfect pulse generator (PG) is the dominant problem. The practical PG does not generate complete symmetrical Gaussian monocycle with slight ringings.

In addition, the pulse generator connects a single-to-differential balun to generate the differential pulses in order to make synchronization between the dual input ports.

However, the balun only has an operating bandwidth from 2 to 4 GHz. The output pulses of balun have more distortion than the primary ones. The distortion may result in measurement discrepancy. Moreover, the chip with wire bonding may be another potential problem. Although the measured results don’t accomplish primary result in the simulation, but the correlator still functionally work. We will consider carefully for later integration.

Due to the similar waveforms of dual inputs, the correlator can be regarded as a direct-conversion (zero-IF) architecture. According to the measured results, it can be observed that DC offset occurs. The generation of DC offset usually has several reasons, which like self-mixing, even-mode nonlinear distortion, and imbalance turn-on time between the positive end and the negative end. These reasons above may cause the output waveforms do not have good performance. Some resolutions can decrease the happen of DC offset. First, it can add extra a low pass filter to isolate high-frequency harmonic elements and make sure the low-frequency elements exist. Second, the mechanism of common-mode feedback (CMFB) can add at the differential output to degrade the imbalance of the differential pair.

3.4 Conclusion

In this chapter we have designed and implemented a UWB LNA and a correlator individually. The LNA uses transformer feedback matching and current reuse technique

to achieve good input matching, noise figure, and gain performance. Because of complete layout consideration and post simulation, the measurement results of LNA show that they are similar to simulation results. It indicates that the transformer feedback topology is feasible for broadband matching. With respect to the correlator, bandwidth extension and dynamic gain control techniques are used in this design. Due to imperfect measurement consideration and signal source, the measured results are more different than simulations. However, it is convinced that these design concepts are suitable in the coherent receiver of IR-UWB systems.

Chapter 4

An Integrated Front-end Receiver for IR-UWB Wireless Communication Systems

4.1 Overview

In this chapter we present a fully integrated front-end receiver of System-On-Chip (SOC) implementation for impulse-radio UWB communication systems. The block diagram is shown in Fig.4-1. It comprises a wideband LNA, a pulse generator, and a correlator. The LNA with transformer feedback and current-reuse topology can accomplish good input matching, low noise figure, and low power consumption. The 2^nd –order derivative Gaussian pulse generator used for generating template waveforms applied to correlate the received signal. The correlator works as multiplication and doubly integration to demodulate the received signals. The overall integrated circuit is fabricated by TSMC 0.18-μm 1P6M CMOS technology and has 19.96-mW total power consumption with 1.48 mm² chip area. In this chapter, we only introduce the design concepts of pulse generator and correlator (for LNA has been demonstrated in Chapter 3). The clock timing of the coherent receiver must to be discussed because of synchronization. Finally, we also introduce the measurement environment and exhibit the simulation and measured results.

Baseband Signal Processor

TX/RX Switch

Figure 4-1 System architecture of IR-UWB transceiver (dash line indicates RX front end)

4.2 Switched 2nd-order derivative Gaussian Pulse Generator

In order to generate a local 2^nd-order Gaussian pulse, the pulse generator (PG) comprises three cascade stages to realize the square, exponential, and second-order derivative functions, respectively [25]. The illustration is shown in Fig.4-2. Based on Fig.4-2, we propose that switched pulse generator (WSG) applied in this receiver. WSG has low-power property because there is nearly no static power consumption. The circuit is shown in Fig.4-3, including a clock shaping, a transient circuit, and a 2^nd-order derivative circuit. First, in order to achieve a more ideal clock signal for next stage, the clock shaping network consists of four-cascaded inverters which can improve the rise/fall time of the clock signal in the sub-nanosecond range. The simulation waveforms are shown in Fig.4-4. The black line indicates non-ideal clock waveform, whose rise and fall time are both 1.5ns and period is 10ns. The modified clock by shaping circuit is presented in gray line and the rise time is less than 100ps. Although the amplitude of modified clock degrades slightly compared to the original clock signal, but it is enough to drive accurately for circuits of next stage. The simulation results shows the practical clock becomes more ideal clock by a shaping circuit made of four-cascaded inverters.

e

^−x

( )

² d x

dt

2

2 G t₂( )

V t

_in

( )

Figure 4-2 Block diagram of the generation of the 2^nd-order derivative Gaussian pulse

{ { {

^nd2

Figure 4-3 Schematic of 2nd-order derivative Gaussian pulse generator

Figure 4-4 Non-ideal clock and clock after shaping

As for the transient circuit, the common-gate stage (M₁) works as a switch. When

clock is in negative half-period, turns on and the current only flows through

but not . When is changing from the negative to the positive state, becomes cut off and the impedance looking in is very small. At the short duration, the current flows through the series circuit and forms an impulse in [26].

The impulse is shown in Fig.4-5 and the width is about 200ps. The small resistor is used for reducing ringing of the impulse.

Vs

Finally, in the 2^nd-order derivative circuit, is driven only when its gate voltage is at positive edge. The cascode stage does not have current flow for the rest of the impulse period. The main second-order derivation function is implemented by the network. The trans-impedance of the RLC network in the s-domain is derived as

If assuming the load impedance of as 50Ω and choosing proper LC values which satisfy with the UWB frequency range of interest, Equation (4-1) can be approximated by

R_p +sL_p <<1/sC

R

_{p p}

I

_ds3

( ) s

(4-2)

The output voltage represents the second derivative of the drain current . Besides, to generate the opposite pulses at the same time for the differential correlator, another parallel path is connected an extra inverter to form a negative pulse for PMOS cascode stage. The negative impulse is shown in Fig.4-6. network is added for the same purpose for network. The final positive/negative waveforms are shown in Fig.4-7 and Fig.4-8.

Vout_{_} I_ds3

n n nLC R

Figure 4-5 Simulation positive impulse generated in V_{x_p}

Figure 4-6 Simulation negative impulse generated in V_{x n_}

Figure 4-7 Simulation positive 2^nd –order Gaussian pulse

Figure 4-8 Simulation negative 2^nd –order Gaussian pulse

4.3 Doubly-Integration, Inductorless, Wideband Correlator

In the previous chapter we have proposed a correlator based on a Gilbert-cell. With dominant pole at the internal node being cancelled, the bandwidth can be increased.

However, as a result of the three stacked layer used in the configuration, the Gilbert cell always includes issues of complex pole-zero arrangements, low signal swing, in-band flatness issues as well as bias issues [27]. Due to the transistor operation mode, power consumption is another issue and a new multiplier configuration is need for efficient implementation of UWB systems. To accomplish this design, we apply the four-quadrant multiplier implementation, inductor-less technique, and bandwidth enhancement for the UWB correlator. The simplified block diagram is shown in Fig.4-9.

Figure 4-9 Simplified diagram of the proposed correlator

Figure 4-10 Schematic of the proposed correlator

A fully differential four-quadrant multiplier and doubly-integrated mechanism has been proposed in this design. The schematic of circuit is shown in Fig. 4-10. In order to avoid extra single-to-differential balun between the LNA and the correlator, the negative RF input terminal is connected a DC voltage reference and a bypass capacitor is added in it. NMOS M₁ to M₄ operate in triode region and this kind of current is followers. The output current can be presented as [28]

(4-3)

Similarly, . According to the above equations we can get the

Consequently, the output comprises the product of two input signals where

DSP DS y

v =V + v _, v_DSN =V_DS −v_y, V_DS is DC biasing when

v

_x

= v

_y

= 0

.

The differential outputs of local template pulses are generated by the pulse generator. The capacitor is set up between the differential outputs of the quadrant multiplier. Switch resets the data at the later half-period waiting for the coming of the next data. The signal after first-time integration still has apparent drop and does not last for a long time, so we exploit zero-pole cancelling topology [29] to reach bandwidth extension and double integration simultaneously.

Cint

Figure 4-11 (a) Illustration of frequency compensation skill with zero-pole cancelling (b) Small-signal equivalent model

From Fig.4-11, the method is realized by and . The appropriate C value and transistor size of can be chosen for frequency compensation. Assume the transfer function

get

While is the equivalent linear resistor resulting from operating in triode region, the value is

According to these equations above, we can make the zero to cancel the dominate pole efficiently for bandwidth enhancement. Additionally, the second-time integration is accomplished simultaneously.

Figure 4-12 The biasing circuit for constant transconductance

Figure 4-12 The biasing circuit for constant transconductance

在文檔中 應用於超寬頻脈衝通訊系統之接收機前端電路設計與實現 (頁 47-0)