Measurement Results and Discussion

(a) (b)

Figure 4-19 (a) Practical 2^nd-order Gaussian pulse generator (b) Measured waveform

4.5.2 Measurement Results and Discussion

An integrated pulse based UWB receiver using the coherent architecture is fabricated by TSMC 0.18μm RF CMOS process. The die microphotograph is shown in

Fig.4-21 with chip size 1.48 . The measured differential output waveform is shown in Fig.4-22. We observe that the rise time is around 1.8ns, the fall time is 1.3ns, and the hold time is 2.2ns. The peaked amplitude of output waveform is 140mV when the input peaked value is 40mV. Except from the pulse shaping circuit of the pulse generator and the output buffer, the core power consumption is 19.96mW with 110MHz pulse repetition rate. The summary of the simulation and measurement results is list in Table 4-1. It can be observed that the rise time of simulation is faster than practical experiment, but the fall time of simulation is slower than experiment. The reasonable explanation may be that the actual parasitic capacitance at the charging path is more than the predicted value and leads to large RC time constant. At the discharging path, these switches consisting of transistors are controlled by an independent signal, so the practical fall time is shorter than simulation. However, we can still demonstrate that the front-end receiver works functionally.

mm2

Figure 4-20 Microphotograph of the proposed front-end receiver

Time (5ns/div)

-0.05 0 0.05 0.1 0.15 0.2

Amplitude (0.05V/div)

Figure 4-21 Measured output waveforms

Table 4-1 Comparison of simulation and measurement results of the receiver Simulation results Measurement results

Technology TSMC 1P6M 0.18μm

Supply voltage(VDD) 1.8 V

Operating frequency ~10GHz

Pulse repetition rate 110 MHz

Pulse width 260 ps

Max. Vout amplitude 126 mV 140 mV

Rise time 1.0 ns 1.8 ns

Hold time 3.2 ns 2.2 ns

Fall time 1.6 ns 1.3 ns

Power consumption (core)

@100MHz UWB pulse repetition rate

18.34 mW 19.96 mW

Chip area 1.228mm×1.205mm

Chapter 5

Conclusion and Future Works

5.1 Conclusion

Ultra-wideband is a promising technique which possesses low power consumption and high data rate. Due to the outstanding characteristics of UWB, we focus on researching the receiver design and implementation. In Chapter 3, the proposed LNA and correlator used in UWB systems are introduced. The LNA exploits transformer feedback matching instead of the conventional matching method to achieve broadband matching and acceptable noise performance. As to gain stage, current-reuse technique reduces dissipation and obtains adequate gain simultaneously. The measured results show that S11, S21, S22 are similar to simulation results. The average NF is 4 dB. The minimum IIP3 is -5 dBm. It illustrates that the topology is feasible in UWB system.

Referring to the correlator, the Gilbert multiplier is adopted and inductive peaking of the load stage is used for achieving wideband feature. Variable gain control is another feature at the correlator. Besides, double integration is used for longer hold time for circuits of the next stage. The practical measured results show that the rise time and hold time are inferior to simulation performance. The dynamic gain range of measurement is 36-89mV, which is also lower than simulation. The reason may be due to bond wire at each port or imperfect pulse source. But the performance has the trend to match the expectative result as well.

Finally, the integrated front-end receiver is presented in Chapter 4. The proposed front end of receiver which comprises a UWB LNA, a 2^nd-order derivative Gaussian pulse generator, and a wideband correlator is presented. The switched pulse generator is applied for reducing static power dissipation. Differential output is designed for the

purpose as template pulse of the receiver. The double integration correlator has long enough hold time for next stage, and the inductorless architecture can reduce the overall chip area and achieve broadband characteristic simultaneously. The proposed receiver front end had been integrated in a single chip by TSMC 0.18μm process. The measured results demonstrate that the front-end receiver can achieve a transmission rate over to 110Mb/s, and it conforms to the characteristic of the desired transmission rate in the IR-UWB communication systems.

5.2 Future works

IR-UWB communication systems have many unusual advantages compared with conventional communication systems, such as low complexity, low duty cycle, high immunity to other interference and high security. These features are much deserved to research for advanced specification. Although IEEE 802.15.3a standard is announced that the task group disbanded in 2006, but many industrial and academic organizations still go for investigation in this field. It can be expected that UWB systems can be accepted extensively in wireless-communication life. In the short term, we will develop toward chip integration by the advanced CMOS process. In this thesis, a prototype of the front-end receiver of IR-UWB systems is proposed. We hope that the achievement can provide a good design guide of IR-UWB communication systems.

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