Contents of Thesis - Introduction and motivation

Chapter 1: Introduction and motivation

1.4. Contents of Thesis

In the previous sections, the motivations for developing a fabrication process to create a lateral 2D p-i-n junction in a totally undoped heterostructures have been detailed, and we also summary up-to-date, as we known, lateral p-n junction fabrication schemes. In chapter 2 fabrication process of a lateral 2D p-i-n junction will report in detail. Chapter 3 and chapter 4 contain mask design and experiment results from single-gate and twin-gate devices, respectively. Finally, conclusions from the work presented are given and the opportunities for further work are discussed.

Chapter 2 Device Fabrication Techniques

This chapter contains a description of fabrication techniques of an induced lateral p-i-n diode in a wholly undoped GaAs/AlGaAs quantum well. The device fabrication deals with the fabrication techniques used in processing the lateral p-i-n diode. These are cleaning, patterning, gate dielectric deposition, etching, and metallization. The fabrication process is summarized with illustrations to explain the sequence of fabrication. One set of devices deals with single top gate, whereas the second deals with twin gate (top and surface gates) design. A very brief overview of the fabrication is given to highlight the differences in design of the lateral 2D p-i-n diode. Further details of these differences are given in single and twin gate device chapters, respectively.

2.1 Basic Principle of Formation an Induced 2DEG

In general, the 2DEG (or 2DHG) can be electrostatically induced in GaAs/AlgaAs quantum well by an external electric field, which may be controlled via isolated gate or Schottky gate. The basic principles underlying the formation of an induced 2DEG (or 2DHG) are illustrated in figure 2.1. The device is analogous to a capacitor; one plate of the device is connected to ground and the other has a fixed voltage applied to it. In this device, see figure 2.1, a Schottky gate acts as one plate, the undoped AlGaAs as the dielectric and the quantum well as the other plate. Electron (hole) gas are induced in quantum well by the application of a positive (negative) voltage on the Schottky gate.

Figure 2.1 Schematic diagram of an induced gas

Figure 2.2 illustrates the formation of 2D gas in undoped GaAs/AlGaAs quantum well with assumed that there is no background doping or surface state. In unbiased condition, see figure 2.2 (a), Fermi energy is at the midgap energy. There is no extrinsic carrier in quantum well. The application of the external field causes an offset in the Fermi energy. When a sufficient positive voltage is applied to bring Fermi energy above the conduction band, and above the electron energy of ground state in quantum well, electrons are injected into quantum well from ohmic contact and a 2DEG will form, as shown in figure 2.2 (b). A 2DHG will create when an enough negative voltage is applied to take Fermi energy below the valence band, and below hole bound state energy in the quantum well, see figure 2.2 (c).

Figure 2.2 Band structure of an induced gas with assuming no surface state and background doping. (a), unbiased condition; Fermi energy is at the midgap energy.

(b), positive voltage applied; Fermi energy is above the conduction band, a 2DEG will form. (c), negative voltage applied; Fermi energy is below the valence band, a 2DHG will be induced.

The ohmic contact and its relationship to the Schottky gate are decisive for fabrication of induced gas. Making contact to the gate is trivial but making contact to the channel while remaining isolation from the gate is very difficult. Figure 2.3 (a) demonstrates the typical “spike” profile of a diffused ohmic contact, as it is often assumed to be the case. In this case, there is separation between the ohmic contact and channel under the gate the potential cannot be defined and so the 2D gas will not form.

However, if the diffusion profile can be developed as shown in the figure 2.2 (b) a 2D gas can be induced.

Figure 2.3 The ohmic contact diffusion profile. (a), a standard diffusion profile is shown;

since this does not reach underneath the gate a 2D gas cannot be form. (b), the channel is contacted under the gate and so a 2D gas should create.

2.2 Device design

2.2.1 Sample Structure

The layer structure used for lateral junction fabrication is that of a GaAs/AlGaAs quantum well shown in figure 2.4. The sample was grown on a semi-insulating (100) GaAs substrate by using a solid-source MBE system. A 400 nm Al0.33Ga0.67As was grown on top of a 100 nm GaAs buffer layer, followed by a 10-period GaAs/Al0.33Ga0.67As (3 nm/3 nm) superlattice. A 20 nm GaAs quantum well between two Al0.33Ga0.67As barriers was grown as the conductive channel of the device. Finally, the sample was capped with a 5 nm GaAs layer. All the layers were completely undoped. Here SL was grown in order to improve device quality of the active layer, such as internal quantum effiency, high carrier mobility [40-42]. These improvements have been attributed to the capture of impurities, which could originate from either the substrate or from the AlGaAs epilayers,

or to automatically smoothing effect by the growth of AlGaAs/GaAs superlattice [40, 43, 44].

Figure 2.4 Schematic diagram showing GaAs/AlGaAs quantum well structure that was used to fabricate lateral p-i-n junctions.

2.2.2 Device design

The devices were fabricated in a completely undoped GaAs/AlGaAs quantum well which is described above. There are two designs for lateral 2D p-i-n junction, as shown in figure 2.5. In principle, two gates will induce 2DEG and 2DHG side by side in the quantum well under appropriate gate biases. Figure 2.5 (a) shows the schematic cross-section of the single-gate device design. There are two isolated gate, p-gate and n-gate, in this design.

With a negative voltage applied on the p-gate and a positive voltage applied on the n-gate, both 2DEG and 2DHG channels can be induced in the GaAs quantum well, so a lateral 2D p-i-n diode is formed. 2DEG and 2DHG are induced in the left and the right side of the quantum well, respectively. The schematic cross-section of the twin-gate device design is displayed in figure 2.5 (b). In the twin-gate devices, each gas (2DEG or 2DHG)

is controlled by two gates, surface gate (SG) and top gate (TG). The top gates, which overlap the source and the drain through the insulator spacer, control the carriers in the channel regions next to the source and the drain without having a leakage path between the gates and the ohmic contacts. Surface gate, which is very close to the channel; provide a very good control for the carriers in the channel.

Figure 2.5 Schematic diagram of a lateral 2D p-i-n junction. (a), single-gate device. (b), twin-gate device.

2.3 Process Flow

The fabrication processing starts with sample cleaning, followed by wet etching to form the photolithography markers and device isolation patterns. And then the ohmic contact region was then deﬁned and recessed down to the GaAs channel. Afterwards, the contact metal was deposited by E-gun evaporation and annealed in nitrogen gas. It further moves

on to explain the deposition of gate dielectric, formation of metal contacts and the subsequent lift off processes. Here similarities in fabrication process of all designs of the devices are highlighted. Finally, emphasis is given to explain the difference in design of single and twin gate devices.

2.3.1 Mesa Isolation

The process flow explains the sequence of device fabrication. Mesa isolation is carried out as the very first step after cleaning the substrate. In the Figure 2.6 (a) to (d) the processes are illustrated. Here cleaning of the sample and resist spinning are shown in (a), patterning of resist layer using mask aligner is presented in (b), wet etch of AlGaAs/GaAs using H3PO4:H2O2:H2O = 3:1:50 solution shown in (c). Here red color has been used for positive photo-resist Az6112 and the white pattern represents developed resist layer as shown in (b). Green layer is 20 nm-GaAs layer and gray layer is AlGAsAs layer. Finally in (d) the resist layer is removed.

Figure 2.6 Mesa isolation process

2.3.2 Contact Metallization and Thermal Diffusion

Contact’s metal deposition and diffusion are shown in figure 2.7. Here red color has been used for positive photo-resist Az6112. After mesa isolation, sample was pattern for selective p and n metal deposition in two separate steps. Each deposition processes (figure (a) to (e) refer to p-type deposition and (f) to (k) refer to n-type deposition) was followed by rapid thermal annealing in pure nitrogen gas to diffuse dopant into quantum well channel. Here in figure 2.7 (k) the cross-section of device isolation patterns, p-type and

type metals regions are shown. The solid fill blue and purple colors are corresponding for p- and n- metallization regions. These regions serve as p and n contacts of the diode.

Figure 2.7 p-type and n-type contact metallization

2.3.3 Single-Gate Devices

Following the contact’s metallization process, a photosensitive polyimide insulator (SU-8 2000.5, HD Microsystems) was then coated and patterned on the surface and cured for 30 mins at 200 ^oC in nitrogen, which gave a thickness of about 350 nm, as shown in figure 2.8 (a) – (b). And then, the metal Ti/Au (20 nm/100 nm) was deposited on top of the

polyimide layer to form the gate by E-gun evaporator, see figure 2.8 (c) – (g). Finally, the sample was processed for lift-off in acetone (figure 2.8(f)). Here diagonal line pattern area is illustrated for photosensitive polyimide. The dark yellow color has been used the insulated gate.

Figure 2.8 Fabrication steps of single-gate devices

2.3.4 Twin-Gate Devices

The initial fabrication process for the twin-gate devices follows the same steps as explained above up to the figure 2.7 (k). Recess surface gate processes are shown in figure 2.9 (a) to (d). The recess depth is 150 nm. Figure 2.9 (e) to (f) and (g) to (i) are illustrated fabrication process for polyimide insulator and top gate, respectively. These processes are the same as for single-gate devices. It is to be note that one part of top gate is overlap with ohmic contact and some other is overlap with surface gate, as shown in figure 2.9 (i). Here diagonal line pattern area is also illustrated for photosensitive polyimide. The top gates and surface gates both are presented by dark yellow color.

Figure 2.9 Fabrication steps of the twin-gate devices

2.4 Fabrication Procedures

In the earlier sections, fabrication steps are described, whereas in this section details of the processes and critical factors affecting the fabrication process are given.

2.4.1 Sample Cleaning

The surface cleaning of GaAs and other semiconductors involves two different aspects.

The ﬁrst is the removal of contaminants, such as organic compounds and metal ions. The

second is the removal of the native oxide to expose the bare semiconductor for subsequent processing such as metal contact deposition.

Device substrates require proper cleaning to remove contaminants and residues from prior process steps. Dust particles may also get on to substrates because of the sample cleaving process. There are always some organic vapors in the air of a clean room, and a wafer that has been exposed to them for even a moderate amount of time can become contaminated. Particulates can also arise as a result of certain fabrication processes, e.g. wet etching, dry etching, or metallization. Improper cleaning during fabrication processes may result in unwanted residue for the following fabrication step.

Substrate cleaning is performed using cleaning solutions i.e. acetone and isopropanol alcohol (IPA) in a proper order. Initially, the sample is soaked in acetone to remove oil and grease particles. As acetone has a very high evaporation rate, so the substrate might be left with a layer of contaminated acetone and therefore it requires a rinse in IPA, which is a powerful solvent for contaminated acetone. During each cleaning step, the sample is placed in a cleaning solvent such as acetone; in an ultrasonic bath for three minutes. Finally the substrate is rinsed in D.I water and is dried with a stream of nitrogen gas.

All the III–V semiconductors are readily oxidized by atmospheric oxygen, so the surface of GaAs and other compound semiconductors that have been exposed to air will be covered by a thin layer of native oxide. This is typically of the order of 1–2 nm after long-term air exposure. Immersion in either acidic or basic dilute solutions will dissolve the native oxide. In our some processes such as surface gate, ohmic contact fabrication, addition cleaning step is required to remove native oxide. The sample is dipped in an 1:10 HCl:H₂O solution in 30s to remove the oxide layer. The HCl/H₂O solution will also assist in the removal of organic and metallic impurities. So it also helps to improve the sample surface quality for subsequent processing.

2.4.2 Photolithography

Photolithography is the process of transferring geometric shapes on a mask to a light-sensitive chemical, called photoresist, on the surface of a wafer. The tone of the photo-resist may be either positive or negative. Use of the photo-photo-resist mainly depends upon the

mask used to transfer the pattern and the limitation of the fabrication process.

Furthermore, positive and negative photo-resists are used for dark field and light field masks, respectively. During the fabrication of these devices, we use Az 6112 and Az 5214E photoresist. Az 6112 is positive photoresist, so it is suitable for dry etch process.

Az 5214E has image reversal capability, thus it is suitable for processes that require lift-off.

* Positive photoresist

In positive photoresist, exposure to the UV light changes the chemical structure of the photoresist so that it becomes more soluble in the developer. Therefore, exposed resist is washed away in developer solution and unexposed resist remains on the wafer.

* Negative photoresist

In contracts to positive photoresist, exposure to the UV light causes the negative resist to become polymerized, and more difficult to dissolve. As a result, exposed resist stays and the rest of the resist get dissolved in the developer solution. Figure 2.10 Shows development of positive and negative photoresists.

Figure 2.10 Development of positive and negative photoresist

* Photolithography process

A typical photolithography process consists of resist coating, mask alignment, exposure, and development.

- Resist coating: The wafer is covered with photoresist by spin coater. A viscous, liquid solution of photoresist is dispensed onto the wafer, and the wafer is spun rapidly to produce a uniformly thick layer. Thickness of the thin resist layer is a function of spin

speed [ ].

- Mask alignment and exposure: Device fabrication involves multiple photolithography exposures. Therefore, alignment accuracy is important parameter for photolithography.

Alignment markers are used to expose the mask pattern exactly over the substrate pattern.

One the mask pattern is aligned to the substrate design, the photoresist is exposed to high intensity UV light for a specific time.

- Development: After exposure to UV light, sample was dipped in developer solution in a particular time.

In our processes, we used both negative (Az 5214E) and positive (AZ 6112) photoresist. The photolithography process of Az 5214E is as follows:

- Resist coating: a small amount of Az 5214E is applied on sample surface. Substrate is rotated at 1000 rpm in 10 s and then at 6000 rpm in 45 s.

- Hard bake: sample is baked at 90 ⁰C in 90 s. Thickness of the photoresist layer after baking is about 1300 nm.

- Exposure: After mask alignment, sample is exposed for 2.8 s.

- Reversal bake: 120 seconds at 120 ⁰C in nitrogen-flow oven. This is the most critical step.

- Flood exposure: 120 seconds

- Development: Sample is dipped in Az300 developer solution for 40 s, and then rinsed in D. I. water in 2 minutes.

- Post bake: sample is baked at 120 ⁰C in 120 seconds. This step is optional. The post bake solidifies the remaining photoresist, to make a more durable protecting layer in future processes such as, wet etch, dry etch. It also improves adhesion of the photoresist to the wafer surface, this will reduce undercut in wet etching.

The photolithography process of Az 6112 is as follows:

- Resist coating: Substrate is rotated at 1000 rpm in 10 s and then at 6000 rpm in 45 s.

- Hard bake: sample is baked at 90 ⁰C in 90 seconds. Thickness of the photoresist layer after baking is about 1200 nm.

- Exposure: After mask alignment, sample is exposed for 2.4 s.

- Post exposure bake: 90 ⁰C in 60 seconds.

- Development: Sample is dipped in Az300 developer solution for 40 s, and then rinsed in D. I. water in 2 minutes. formation and/or the formation of mesa isolation, etching will always be a critical part of their fabrication. There are two etching methods: wet etch and dry etch.

Wet etching is a material removal process that uses liquid chemicals or etchants to remove materials from a wafer. The specific patterns are defined by masks on the wafer.

Materials that are not protected by the masks are etched away by liquid chemicals. The mechanism for most of wet etching of GaAs is the oxidation of surface to form Ga and As oxides, and then these oxides are dissolved by liquid chemicals with bases or acids [45].

In dry etching, plasmas or etchant gasses remove the substrate material. The reaction that takes place can be done utilizing high kinetic energy of particle beams, chemical reaction or a combination of both [45]. Both approaches have their own advantages and disadvantages. Table 2 shows the comparison of wet and dry etching.

Table 2.1 Comparison between wet and dry etching

Wet etching Dry etching

Method Chemical solutions Ion Bombardment or

Chemical reactive Environment

and

Equipment

Atmosphere, bath Vacuum Chamber

In mesa isolation process and surface gate recess etching, wet etching was used.

To shadow etch AlGaAs and GaAs, the phosphoric acid family of etchants are prefer because they product smooth surfaces and can provide control of etch depths at level of tens of angstroms [46]. In addition, a good non-selective etch for AlGaAs is H₃PO₄:H₂O₂:H₂O with a 3:1:50 ratio. This chemistry etchs AlGaAs and GaAs at nearly equal rates of approximately 1.8 nm/s. It is important to note that etching solution can change composition with passage of time, with a resulting change in their associated etch rates. In general, etching rate reduces with time. In H₃PO₄:H₂O₂:H₂O system, etching rate varies if the solution is used too soon after it is mixed. After thermal equilibrium (around one hour), no change in etch rate is observed in next one week [45]. To reproducible process, it needs to note the age of the solution.

Fabrication of the ohmic contact is the critical step in our processes. Our device structure is totally undoped, so ohmic dopant need to lateral diffuse into channel to form self-align structure, as have explained above. Therefore controlling etching profile of the ohmic contact is important. To get vertical sidewall profile, dry etching was used. Dry etch processes can provide excellent proﬁle control. The energetic ion bombardment increases the etch rate on the exposed surface relative to those regions protected by the

mask, so vertical sidewalls with negligible undercutting are readily achieved. But in dry etching, the ion bombardment so essential to achieve this advantage simultaneously damages the near-surface region of wafer. To reduce degradation of electronic properties, we use an inductively coupled plasma (ICP) RIE system. This system uses two separate power supplies with one (ICP power) generating the plasma and the second one providing the RF power that controls the ion bombardment energy.

The ICP-RIE system provides semi-independent control of the plasma chemical species, both ions and neutrals, and the energy with which the ions hit the wafer surface.

Control over damage can be achieved by low ion energy (i.e., low RF power). Our dry etch process was done as follow:

- Sample with pattern photoresist on the surface was dipped in 1:10 HCl:H2O solution in 30 s to remove oxide layer on sample’s surface.

在文檔中無摻雜GaAs/AlGaAs量子井之橫向p-i-n二極體 (頁 29-0)