Current – Voltage Characteristics of the Single-Gate Diode

By biasing the n- and p-channel devices above their threshold voltages, the electrical characteristics of the p-i-n device were then measured with the setup schematically shown in the inset of the figure 3.6. The measurement was carried out at 1.5 K in a helium continuous-flow cryostat. The gate voltage of the p-channel device V_gp was set at -3 V and that of the n-channel device V_gn at +5 V. The current flows between the p-channel and the n-channel I_pn was measured as a function of the voltage applied between the p and n ohmic contacts Vpn. In the measurement setup, the gate voltages for the N channel were measured relative to the source (the ohmic contact on the left), and the voltage of the P gates were measured relative to the drain (the ohmic contact on the right). So with this setup, the channel condition for both the N channel and the P channel remains the same when Vpn is changed. Note that the current Ipn in figure 3.6 was plotted both in the linear

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and logarithmic scales for clarity. One can see clearly the rectifying behavior with a turn-on voltage of 1.53 V. This is in agreement with the theoretical calculatiturn-on of the built-in voltage V_bi = 1.535 V [50]. The turn-on voltage of the p-i-n diode, however, slightly depends on the gate voltage applied to the n-gate and the p-gate. From the band energy diagram in figure 3.3 and the built-in voltage V_bi (shown above), we can see that the turn-on voltage is approximately at the band gap energy and depends turn-on the carrier densities in 2DEG and 2DHG. The higher the gate bias (positive for the n gate and negative for the p gate) is, the higher the built-in potential is and, therefore, the higher the turn-on voltage is.

The current of the diode can go up to hundreds of µA. In the reverse bias, the leakage current is below 1 nA up to – 2 V.

Figure 3.6 Current – voltage characteristics of the lateral 2D p-i-n diode at temperature of 1.5 K with p-gate and n-gate biasing at V_gp = -3 V and V_gn = +5 V, respectively. Vpn is the operation voltage of the diode. The inset shows a schematic diagram of the measurement setup for the lateral 2D p-i-n junction.

41 3.4 Optical Characteristics

The electroluminescence (EL) emission of the p-i-n diode measured at 1.5 K is shown in figure 3.7. The device was measured under gate voltages of V_gn = 7 V and V_gp = -7 V, and a forward current I_pn = 200 µA. There are two peaks in the EL spectra. The peak at 1.529 eV (811 nm) with the full-width at half-maximum of 4.4 meV is, we believe, from the ground state emission of the 20 nm GaAs/AlGaAs quantum well. The results are in good agreement with the theoretical calculation. Using the infinite-well approximation, the ground state of electrons in the quantum well E_1n = 0.014 eV and the ground state of holes in the quantum well E1p = 0.002 eV. Otherwise, the band gap energy of GaAs at 1.5 K is 1.517 eV. Therefore, the energy of ground state excitons of the quantum well can be estimated to be approximately 1.533 eV (809 nm). The small peak at 831 nm is probably from the acceptor level in the quantum well. The positions of the peaks are independent of the diode current. The electroluminescence emission spectra of our devices are stable and much cleaner than those of previously reported lateral 2D junctions [4, 7, 27, 53]

which is important for using the device for further studies and applications.

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Figure3.7 Electroluminescence spectra of the lateral 2D p-i-n diode at temperature of 1.5 K with p-gate and n-gate biasing at Vgp = -7 V and Vgn = +7 V, respectively, and a forward current I_pn = 200 µA.

Furthermore, to confirm that the light was indeed emitted from the 2D p-i-n junction, EL intensities were measured as a function of position with a spatial resolution of 10 µm.

The device was inserted into the micro-photoluminescence (µ-PL) system, which is shown in figure 3.8. The stage can be controlled by using a Newport Universal Motion Controller ESP 300 with a step resolution of 0.5 µm. Thus, a spectrum of the diode is captured by Princeton camera ST-133 for each position of the device. All system was controlled automatically by labview program.

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Figure 3.8 Configuration of Micro Photoluminescence system

Figure 3.9 shows the contour plot of the integrated spectral intensity versus position.

The scanned area is 225 x 30 µm². The device was measured with I_pn = 100 µA, V_gp = -5 V, and V_gn = +5 V at 77 K. From the result, one can clearly see that the emitted light is indeed from the junction area (in the middle between the dashed guide lines), but close to the two sides of the device. The reason for such distribution is because the lowest resistive path is near the two sides. Additionally, the emitted light coming from the right corner is much stronger than that coming from the left corner. This is possibly attributed to the asymmetric gate geometry [see figure 3.2 (a)] and the resistance difference of the ohmic contacts.

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Figure 3.9 Contour plot of integrated spectrum intensity at temperature T = 77 K, gate bias V_gp = -5 V, V_gn = +5 V and forward current I_pn = 100 µA.

3.5 The Yield of n-channel and p-channel

The yield of the induced 2DEG and the induced 2DHG are approximately 60% and 80%, respectively. The yield of the induced 2DHG is higher than that of the induced 2DEG.

This is possibly due to p-type ohmic contacts are smoother than n-type ohmic contacts. In addition, AuZn/GaAs contact lacks the low-temperature lattice disrupting constituents common to n-type GaAs contacts [45]. There are several main causes of failure. One of these is leakage. The most common leakage is between the gate metal and the ohmic contact. This leakage occurs as soon as any voltage is applied. There is a main reason that lead to this leakage: spikes in the ohmic contact surface. To reduce possibility of spikes, ohmic metal deposition should keep stable at a reasonable rate, and lift-off and thermal

45

annealing processes should immediately done after sample was unloaded from the chamber.

Another reason for failure of the device can occur during processing of polyimide layer. This process is sensitive to humidity. The first and most obvious of these is that under high humidity conditions the polyimide does not form a continuous film on the sample. This problem has been improved somewhat by the addition of several steps to reduce the humidity locally. Between each processing step the samples are kept in a vacuum box with silica gel. Another problem, possibly occurred in curing of polyimide, is crack on the polyimide surface. Therefore, we should keep temperature increasing and surface), if etching depth is above or 40 nm below the quantum well, 2D gas cannot form.

A fourth reason for failure, involved with the measurement of these devices, should be mentioned. It should be appreciated that the measurement of these devices is different from that of doped samples in several ways. The first is that a gate voltage will always have to be applied to induce a 2D gas. Also the voltage required to form a 2D gas are far in excess of voltages typically used on doped gas. Therefore it has been found that the devices appear to have leakage problems when in fact it is the electrical contacts to the devices, via the probe, that are at fault. The devices should also be cooled in the dark.

This prevents the devices from turning on, possibly due to charging effects.

3.6 Disadvantages of Single-Gate Structure

We have developed a relatively simple method to fabricate high-quality lateral 2D p-i-n junctions. By using the MIS structure, 2DEG and 2DHG can be induced side by side in a completely undoped GaAs/AlGaAs quantum well. Our results show that the device is promising for applications in SAW-driven single-photon sources and probing the intrinsic spin Hall effect in low-dimensional systems by optical means. However, the gate control of the carriers in the quantum well is not very efficient because of the distant gate from

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the channel. As a result, the two top gates on the insulator could not be put too close to each other. This directly affects the carrier recombination in the i region. To solve this problem, we developed the present twin-gate structure, whose cross-section was shown in figure 2.5 (b) of the previous chapter. The surface gates provide a very good control for the carriers in the channel and at the same time can be put very close to each other. The top gates, which overlap the source and the drain through the insulator spacer, control the carriers in the channel regions next to the source and the drain without having a leakage path between the gates and the ohmic contacts. The characteristics of the devices will be reported in the next chapter.

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Chapter 4

Twin-Gate Devices

In this chapter two-dimensional lateral p-i-n junction devices with twin-gate design are described. These devices were based on MIS-architecture hybrid with Schottky-gate structure. Mask design is described, followed by a description of the device’s electrical and optoelectronic properties including current-voltage (I-V) characteristics, optical characteristics.

4.1 Mask Design

Figure 4.1 shows the mask design for twin-gate devices. The figure 4.1 (b) is an enlarged center region of the device. Mesa isolation etching is in white color. Purple and green colors present for n-type and p-type ohmic pads, respectively. Top gate metal is in dark yellow color. Two n-type ohmic contacts are in purple color and two p-type ohmic contacts are in green color. Surface gate metal is in blue color. The polyimide layer has two rectangular holes at two sides of polyimide layer to make pad contact to surface gate.

The distance between two surface gates is 2.0 µm. The length of the surface gate is 10 µm, and the width is 7.5 µm. Top gate (TG) overlaps part of the surface gate (SG) and part of ohmic contacts with polyimide in-between.

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Figure 4.1 Mask design for twin-gate devices

In the previous chapter, we have discussed a lateral p-i-n diode using a single-gated MIS structure. But the gate control of the carriers in the quantum well is not very efficient because of the distant gate from the channel. As a result, the two top gates on the insulator could not be put too close to each other. This directly affects the carrier recombination in the i region. To solve this problem, we developed the present twin gate structure, which was first introduced by Harrell et al. [39]. The surface gates provide a very good control for the carriers in the channel and at the same time can be put very close to each other. The top gates, which overlap the source and the drain through the insulator spacer, control the carriers in the channel regions next to the source and the drain without having a leakage path between the gates and the ohmic contacts.

4.2 Principle of Device Operation

Figure 4.2 (a) shows the schematic cross-section of device. Recessed surface gates are fabricated on AlGaAs and at the distance 150 nm from GaAs quantum well channel.

2DEG and 2DHG are induced in the left and the right side of the quantum well under appropriate gate biases, respectively. The top view of a finished device is shown in figure

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4.2 (b). The upper half is the p-channel device and the lower half is the n-channel device.

The fabricated device has a length of 10 µm and a width of 7.5 µm for both 2DEG and 2DHG channels. The distance between the n-SG and the p-SG, that is the length of i region, is 2 µm. Dark blue is polyimide. The devices are normally off because the epitaxy layers are totally undoped.

Figure 4.2 (a) Schematic cross-section of the devices. (b) Optical microscopy image of the finished device.

In our device layout, the n-SG and the p-SG are placed side by side with 2 µm spacing; see figure 4.1(b). With a negative voltage applied on the p-gates (SG and TG) and a positive voltage applied on the n-gates (SG and TG), both 2DHG and 2DEG

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channels can be induced in the GaAs quantum well, so a lateral 2-D p-i-n diode is created.

The operation of the devices is almost the same as the operation of the single-gate devices.

4.3 Electrical Characteristics

4.3.1 Single Channel

The device was mounted on a ceramic holder and wire-bonded, and then placed in a helium continuous-flow cryostat for electrical measurement. The device was cooled down to 4 K in the dark. The schematic of the measurement setup for the 2DHG and 2DHG channel is shows in figure 4.3. This setup is similar to that used for the single-gate devices with addition of a voltage source for surface gate. Current-voltage (I-V) characteristics of devices were measured with a Keithley 2602A Dual-channel System SourceMeter Instrument.

Figure 4.3 The schematic of the measurement setup for the 2DHG and 2DHG channel. V_tg (V^p_tg or Vⁿ_tg in text) and V_sg (V^p_sg or Vⁿ_sg in text) are top gate and surface biases, respectively.

Figure 4.4 shows the drain current versus p-TG voltage (denoted as V^ptg) curve for the p-channel with the drain-source (two p-type Ohmic contacts) voltage, Vds, set at 500 mV. The two different curves correspond to two different pSG voltages of 0.4 V and -0.6 V. The p-TG threshold voltage is -0.8 V, which stays constant for the two p-SG voltages. The transconductance is higher for V^p_sg = -0.6V as expected because more carriers are induced in the channel. The same measurements were performed for n-channel of the devices. The inset of figure 4.4 shows the drain current versus n-TG

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voltage curve of the n-channel with n-SG voltage Vⁿ_sg = 0.9 V and the drain-source (two n-type Ohmic contacts) voltage Vds of 500 mV. The threshold voltage of the n-TG is 3.2 V. The higher threshold voltage of the n-channel is probably due to the surface state pinning at the insulator/semiconductor interface [18].

Figure 4.5 Current – voltage characteristics of 2DEG and 2DHG with bias between two Ohmic Vds = 500 mV at temperature of 4 K. Current – TG voltage characteristics of 2DHG with different SG voltages, -0.4 V (dashed line) and -0.6 V (solid line). The inset shows current – TG voltage characteristics of 2DEG.

Figure 4.5 shows the drain current versus p-SG voltage V^p_sg for the p-channel at V_ds = 500 mV. Different curves correspond to different p-TG voltages. The p-SG threshold voltage is -0.2 V. The saturation current is higher for higher V^p_tg, because the series resistance between the channel and the source Ohmic contact is reduced when V^p_tg increases. The I_ds- Vⁿ_sg curve for the n-channel with Vⁿ_tg = 6 V and V_ds = 500 mV is shown in the inset of figure 4.5. The threshold voltage of the n-SG is 0.5 V.

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Figure 4.5 Current – voltage characteristics of 2DEG and 2DHG with bias between two Ohmic Vds = 500 mV at temperature of 4 K. Current – SG voltage characteristics of 2DHG with different TG voltages, -0.8 V (solid line), -1.0 V (dot line), and -1.2 V (dashed line). The inset shows current – SG voltage characteristics of 2DEG channel.

The gate leakage currents versus top gate voltage are presented in figure 4.6.

Leakage currents to gates were in scale of the system limit, about 100 pA. Therefore, the stability of the induced carriers is pretty good. The leakage of n-channel is more stable than that p-channel, this possibly due to lower threshold voltage of p-channel.

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Figure 4.6 Gate leakage currents versus top gate voltage. (a)Iⁿ_tg and Iⁿ_sg are leakage currents of n-type ohmic side top gate and surface gate. (b) Iⁿtg and Iⁿsg are leakage currents of p-type ohmic side top gate and surface gate.

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4.3.2 Current-voltage Characteristics of the Twin-Gate Diode

Measurement electrical characteristics of the twin-gate devices are similarity to that of the single-gate devices. By biasing the n- and p-channel devices above their threshold voltages, the electrical characteristics of the p-i-n device were then measured. The measurement configuration is shown in the inset of figure 4.7. The p-TG bias V^p_tg and p-SG bias V^p_sg of the p-channel device were set at -3 V and -0.6 V respectively and those of the n-channel device were Vⁿ_tg = +6 V and Vⁿ_sg = +0.9 V. The current flow between the p-channel and the n-channel, denoted as I_pn , was measured as a function of the voltage applied between the p and n ohmic contacts Vpn; see inset of figure 4.7. In the measurement setup, the gate voltages for the N channel were measured relative to the source (the ohmic contact on the left), and the voltage of the P gates were measured relative to the drain (the ohmic contact on the right). So with this setup, the channel condition for both the N channel and the P channel remains the same when Vpn is changed.

The current Ipn in figure 4.7 is plotted both in the linear and logarithmic scales for clarity.

One can see clearly the rectifying behavior with turn-on voltages of 1.73 V. Very good exponential behaviour was observed all the way down to the measurement limit. The current of the diode can go up to hundreds of microamperes. Two kinks occur in the I-V curve at Vpn = 1.48 and 1.70 V. The kink position slightly changes with the surface gate bias. Thus, they could be attributed to the potential barriers for hole at p-i junction and for electron at the n-i junction. However, further investigations are needed to address this issue.

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Figure 4.7 Linear and logarithmic current – voltage characteristics of the lateral 2-D p-i-n diode at temperature of 4 K with p-TG and n-TG biased at V^ptg = -3 V and Vⁿtg = +6 V, respectively, and p-SG and n-SG biased at V^psg = -0.6 V and Vⁿsg = +0.9 V, respectively. V_pn is the operation voltage of the diode. The inset shows measurement configuration.

Figure 4.8 shows the gate leakage currents versus the diode bias Vpn. We can see clearly that the gate leakage currents are very small. The leakage currents slightly increase when the diode bias is near threshold voltage. In fact, the gate leakage currents versus the diode voltage Vpn curves, however, change from device to device. But, the leakage currents remain very small in comparison with the diode current.

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Figure 4.8 Gate leakage currents versus the diode bias V_pn at temperature of 4 K with p-TG and n-TG biased at V^p_tg = -3 V and Vⁿ_tg = +6 V, respectively, and p-SG and n-p-SG biased at V^psg = -0.6 V and Vⁿsg = +0.9 V, respectively. Vpn is the operation voltage of the diode.

4.4 Optical Characteristics

4.4.1 Electroluminescence Spectrum

Electroluminescence of the devices was measured in micro-photoluminescence system (micro-PL), as shown in figure 3.8 of the previous chapter. The electroluminescence (EL) emission of the p-i-n diode measured at 4 K is shown in figure. 4.8. The device was measured under the surface gate voltages of Vⁿsg = +0.9 V and V^psg = -0.6 V, and the top gate voltages of Vⁿtg = 6 V and V^ptg = -3 V, and the junction voltage from Vpn = 1.6 V to 2.0 V with step of 0.05 V. The inset of figure 4.8 shows the measure photoluminescence (PL) of the sample. We clearly observe two peaks in the PL spectra at 1.5205 eV (815.5 nm) and 1.5239 eV (813.7 nm). The intensity ratio of the two PL peaks remains constant when the excitation power changes. Thus, the two peaks observed here are most likely due to the roughness of the quantum well interfaces [54]. There are also two peaks at

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1.5174 eV (817.5 nm) and 1.5207 eV (815.4 nm) in the EL spectra. The peaks have a 0.4 meV redshift when the junction bias Vpn increases from 1.6 V to 2.0 V. Full width at half maximum of the 1.5205 eV peak changes from 1.2 to 2.2 meV, and that of the other peak from 1.2 to 3 meV when V_pn increases from 1.6 V to 2.0 V. The narrow linewidths of the peaks demonstrate that the 2-D channel is of high-quality, which is essential for further applications such as electrically-driven single photon sources.

Figure 4.9 Electroluminescence spectra of the lateral 2D p-i-n diode at temperature of 4 K with with p-TG and n-TG biasing at V^p_tg = -3 V and Vⁿ_tg = +6 V, respectively and p-SG and n-SG biasing at V^psg = -0.6 V and Vⁿsg = +0.9 V, respectively and Vpn

from 1.6 V to 2.0 V with step 0.05 V. Inset shows photoluminescence spectrum at 4 K.

58 4.4.2 External quantum efficiency

Figure 4.9 shows the integrated intensity of the EL spectra (black curve with square symbol) against the junction bias V_pn. Light intensity increases linearly with diode

Figure 4.9 shows the integrated intensity of the EL spectra (black curve with square symbol) against the junction bias V_pn. Light intensity increases linearly with diode