Summary - CMOS Voltage References - Review of Voltage Reference

Chapter 2 Review of Voltage Reference

2.3 CMOS Voltage References

2.3.7 Summary

In this chapter, we know that voltage references are produced by VPTAT and VCTAT. Introducing bandgap references, and comparing BJT and MOS. Making sure that MOS is better than BJT under our requests. Afterward we introduce five architectures of voltage references and understand how they work. Finally, comparison is shown in the last section. After comparison, we choose voltage mode of VPTAT and VCTAT as our design architecture.

In the next chapter, two propose design architectures will be shown carefully. We will introduce principle, derivation, and simulation gradually, and my propose architectures compare with researches which is presented in the recent six years.

CHAPTER

3

Circuitry Architecture

In this chapter, proposed architectures will be shown and implemented. Before this, we should define specification explicitly. At least, proposed design can work in battery-operated system, and it still has high performance. Then, we start to find out VCTAT which must be produced by MOS, and using VCTAT produces VPTAT if it could be implemented. When having VCTAT and VPTAT, we can design voltage reference stage by stage. Two proposed architectures will be shown and simulated, and we discuss their advantages and problems. Finally, two proposed architectures compare to researches, and explain that proposed architectures are better then researches in the recent six years.

3.1 Design Process

First, we introduce two papers, and those are source of my proposed architectures. So we need to understand the two reference papers step by step. Then we will be clear to know how proposed architectures are designed.

3.1.1 Reference Paper

In Figure 3.1.1, all MOS work in subthreshold region, so VGS is VCTAT. See M8, VG8 is VDD and VGS8 is VCTAT, so we can know that VS8 will be VPTAT. But the current which pass through M7 and M8 changes VGS8 by the current function, so VS8 becomes VREF. We can design the bias circuit which produces VPTAT by this principle. In next section, the bias circuit will be presented and illustrated.

CTAT DD

PTAT V V

V = − (3-1)

Figure 3.1.1: Circuit Architecture of REF[8]

.1.2 V

_PTAT

(Proportional to Absolute Temperature) 3

VDD

GND

M3 M4

M1 M2

VPTAT IPTAT

Figure 3.1.2: Conventional VPTAT Circuit Architectur e

The conve circu

ntional method which produces VPTAT is shown Figure 3.1.2. The it composes of four MOS (M1~M4) and a resistor (R). M1 and M2 work in subthreshold region, and M3 and M4 work in saturation region. R is stable value which doesn’t change with temperature. The derivation is as follows:

Because M1 and M2 work in subthreshold region, the function is (3-2)

⎟⎟ Using (3-2) into (3-3) can be shown as follows:

PTAT

,then we get the function of (3-5)

⎥⎥

The function of (3-5) can be written as (3-6)

⎥⎥

is a positive value, VPTAT is in positive proportion to

temperature. And VPTAT=I2*R, we can know that I2=IPTAT. Therefore, we get VPTAT and IPTAT.

Although, the circuit is better than bandgap reference. But, it has some disadvantages. First, supply voltage is difficult below 1V. The minimum VDD = VGS4(saturation) + VGS1(subthreshold) + VPTAT, and VGS4 > VTH, VGS1 < VTH, VPTAT

should have a value. VTH is about 0.45V at TSMC 0.18μm process. Therefore, we can know that supply voltage will be more 1V. Second, resistor must be used, and it will cause additional inaccuracy and more area. Because VPTAT must reach a fixed value, the R and IPTAT should large enough. It means that area and power must choose one. In addition, someone change resistor to MOS which work in triode region as a resistor.

Indeed, the method could decrease a lot of area. But the method needs additional circuits, the power is possible to increase. So, I propose a simple circuit to solve those problems. I will explain proposed circuit of VPTAT in the next section.

Figure 3.1.3: The VPTAT Proposed Architecture

See Figure 3.1.3, it is proposed circuit of VPTAT. The circuit is composed of three NMOS (M1~M3). All MOS work in subthreshold region, so VGS is VCTAT which is a voltage of negative temperature coefficient. And, VDD is a stable value. Therefore, VPTAT is as follows:

1 DD CTAT DD GS

PTAT V V V V V

V = = − = − (3-7) VPTAT is gotten by two MOS which work in subthreshold region. The supply voltage

In the next section, the two proposed circuit of voltage reference is shown. We of proposed circuit can be lower than 1V because it stacks two MOS which are about 0.8V. And, the area of proposed circuit is very small because it has only two MOS. So, the proposed circuit could have advantages of both small area and low supply voltage.

will discuss principle, derivation, simulation, and problem. The relationship of proposed architectures will be illustrated.

3.2 All NMOSFET Voltage Reference (ANVR)

ture can be shown.

Its a

When we present new bias-circuit, the first proposed architec

bbreviation is ANVR which means All NMOSFET Voltage Reference. The proposed architecture will introduce principle, derivation, and simulation in the next section.

Figure 3.2.1: Architecture of ANVR

M1 M2 M3 M4 R(ohm)

4.976k

μm) 0.5 0.5 0.9 0.9

L(μm) 0.6 0.6 0.6 0.6

m 6 6 6 6

.2.1 Principle of ANVR

See Figure 3.2.1, the proposed architecture is composed of four NMOS (M1~M4)

3

and one resistor. All MOS work in subthreshold region. M1 and M3 are VPTAT

produced circuit which has been introduced in the above section, and it produces a stable VPTAT to mirror to next stage. M2 and M4 are VREF produced circuit. We use VGS4 to be VCTAT, and IPTAT multiple R to produce VPTAT. Then, VCTAT and VPTAT trade

off. By this, a stable VREF will be produced. Because we hope that ANVR can operate under 1V, we choose VTH of MOS around 0.48V. Besides, we hope that proposed architecture’s power can be lower than the power of PAPER [2]. Therefore, we decide that supply voltage is 0.8V and total current is about 500nA. The each current of ANVR is 250nA which is the same current at the architecture of PAPER [2]. Finally, we can know the size of MOS and the derivation can be shown in the next section.

3.2.2 Derivation of ANVR

The section will derivate VREF and illustrate every parameters. First, bias-circuit deriv

. Bias-circuit derivation

1 is shown as

(3-8) Using the current function of MOS works in weak inversion, the function of (3-8) can be written as

ation is shown, and VREF-circuit derivation will be shown by bias-circuit derivation later. Therefore we can decide (W/L) and resistor by the derivation.

First, the function of VGS

( )

T V V

( )

P is (W/L), VT is thermal voltage, and n is subthreshold slope factor. The function of (3-9) become as

Therefore the bias-circuit derivation is done, and VGS1 will be used latter.

(3-11) Using the current function of MO

can be written as

VREF-circuit derivation

REF can be written as the function V

( ) ( )

[

V T I T R

]

V_REF = _DD − _GS₄ + _D₂ ×

S works in weak inversion, the function of (3-11)

( ) ( ) ( )

the function of (3-12) can become as (3-13) by the function of (3-10)

( ) ( ) If we want VREF which does not change with temperature, dVREF/dT should be zero. n is subthreshold slope factor , P is (W/L), and

2 1

( ) ( ) ( )

_⎟⎟

⎠

⎜⎜ ⎞

⎝

⎛ −

× + +

=V T₀ KT1 T

V_th _th 2 1

V T

KT _bs (3-15)

And its differentiation is written as

( ) (

KT KT Vbs

)

dT^th T = 1+ 2× (

dV 3-16)

KT1 is temperature coeff

coefficient of the threshold volta TH

decided when (W/L) had been decided. Therefore, dVREF(T)/dT can be zero by desig

upply voltage is 0.8V which reaches below 1V. The circuit has only two NMOS to stack, and MOS work in subth

Simulation of ANVR

The layout of ANVR is shown in Figure 3.2.3. ANVR uses no PMOS, so the decrease area. M1 and M2 are lternate permutation, so it can decrease mismatch. IPTAT will mirror to M2 very well.

Beca

and all corners are shown in Table 3.4. Those gures are curve of VREF and temperature, and temperature range is wide enough to icient of the threshold voltage and KT2 is bulk-bias ge’s temperature dependence. dV (T)/dT can been ning P1~P4. When we decide the power, the current will be decided. Then, (W/L) is decided by the current. Finally, resistor can be chosen.

ANVR has many advantages. First, all MOS are NMOS. This method saves a lot area, because we don’t use the area of PMOS. Second, s

reshold region which means VTH < 0.45V. Therefore, we can decrease much power in the proposed architecture. Third, the performance is not bad, and it will be shown in next section.

3.2.3 Post-Layout

layout does not need PMOS region. It is good to a

use a resistor has larger derivation, we divide a resistor into eight resistors. The method can decrease resistor derivation. In addition, dummy technique has been used in the layout, and it is also used to decrease process variation. Figure 3.2.2 shows presim of ANVR, and we can compare with Figure 3.2.3 which shows postsim of ANVR. They are almost the same.

The post-layout simulation is shown in Table 3.3. The five corners are shown from Figure 3.2.4 to Figure 3.2.8,

reach -80℃~165℃. The inaccuracy is only ±1.5mV at Figure 3.2.3 when the corner is TT and TT_RES. In Table 3.3, temperature coefficient is lower than 166ppm/℃ in the worst case when temperature range is -80℃~165℃. We try to adjust the corners of proposed architecture, so temperature coefficient of the worst case can lower than 200 ppm/℃.

Temperature VS.Vref (TSMC 0.18um CMOS technology)

-100 -50 0 50 100 150 200

354.5 355 355.5 356 356.5 357 357.5 358

Temperature=-80 to 165 DEC-C

Vref(T) mv

356.25mV

Figure 3.2.2: Presim of ANVR

Table 3.1: Post-Layout S PAPER

(year)

VDD (V)

Temperature Range

Temperature Coefficient

VREF (mV)

Tech.

(μm)

AREA (mm²)

PSRR (dB)

POWER (W) imulation of ANVR

(℃) (ppm/℃) ANVR

(TT S) -40~125

0~100 356.7

(3 ²

@100kHz 403.2n ,TT_RE

0.8 -80~165 34.4 27.7 16.7

356 356.7

0.18 0.00108

0*36)μm 7.5

Figure 3.2.3: Layout of ANVR in TSMC 0.18um CMOS Technique

A. Post-Layout Simulation Results (VREF):

-100 -50 0 50 100 150 200

354.5 355 355.5 356 356.5 357 357.5

Temperature=-80 to 165 DEC-C

Vref(T) mv

Temperature VS.Vref (TSMC 0.18um CMOS technology)

356mV

354.5mV

357.5mV

Figure 3.2.4: TT TT_RES Corner of ANVR

-100 -50 0 50 100 150 200 344

346 348 350 352 354 356

Temperature=-80 to 165 DEC-C

Vref(T) mv

Temperature VS.Vref (TSMC 0.18um CMOS technology)

349.75mV

344mV 355.5mV

Figure 3.2.5: FF TT_RES Corner of ANVR

-100 -50 0 50 100 150 200

354 355 356 357 358 359 360 361

Temperature=-80 to 165 DEC-C

Vref(T) mv

Temperature VS.Vref (TSMC 0.18um CMOS technology)

357.15mV

354.2mV

360.1mV

Figure 3.2.6: SS TT_RES Corner of ANVR

-100 -50 0 50 100 150 200 355

356 357 358 359 360 361

Temperature=-80 to 165 DEC-C

Vref(T) mv

Temperature VS.Vref (TSMC 0.18um CMOS technology)

357.75mV

355.1mV

360.4mV

Figure 3.2.7: SF TT_RES Corner of ANVR

-100 -50 0 50 100 150 200

346 347 348 349 350 351 352 353 354 355

Temperature=-80 to 165 DEC-C

Vref(T) mv

Temperature VS.Vref (TSMC 0.18um CMOS technology)

354.8mV

346mV 350.4mV

Figure 3.2.8: FS TT_RES Corner of ANVR

B. Post-Layout Simulation Results (VREF):

Table 3.2: Corners of ANVR Post-Layout Simulation (VREF) Corner Resistance

Corner

Temperature Coefficient

(ppm/℃) (0℃~100℃)

Temperature Coefficient

(ppm/℃) (-40℃~125℃)

Temperature Coefficient

(ppm/℃) (-75℃~165℃)

Temperature Coefficient

(ppm/℃) (-80℃~165℃) TT TT 16.7(0.6) 28(1.65) 32.7(2.8) 34.4(3)

FF 23.7(0.85) 33.1(1.95) 36.8(3.15) 38.4(3.35) SS 22.4(0.8) 30.6(1.8) 37(3.2) 36.7(3.2) FF TT 153.1(5.4) 137.9(8) 137(11.5) 134.2(11.5)

FF 113.5(4) 103.4(6) 103.7(8.7) 101.1(8.7) SS 193.5(6.5) 169.5(9.8) 170.5(14.1) 165.3(14.1) SS TT 72.5(2.5) 72.8(4.3) 66.4(5.6) 67.4(6)

FF 75.3(2.8) 76.2(4.5) 50.1(6.1) 73.1(6.4) SS 64.2(2.4) 67.8(4) 63(5) 61.8(5.4) SF TT 64(2.2) 64.2(3.8) 59.3(5) 60.5(5.3) FF 69.5(2.5) 71(4.2) 66.3(5.6) 67.3(5.9) SS 55.7(2) 57.5(3.4) 54.7(4.6) 56(4.9) FS TT 167.7(4) 103.4(6) 103.4(8.8) 102.5(8.8)

FF 79.1(2.9) 73.8(4.3) 76.9(6.6) 76.6(6.6) SS 141.8(10.9) 131.3(7.6) 132.5(11.1) 129.8(11.1) ( ) is derivation of voltage reference, and its unit is mV.

3.2.4 Discussion of ANVR

The performance of proposed architecture is good, but PSRR is lower than the most researches. VREF will shake easily when supply voltage shakes. And ANVR has used resistors which have a derivation. Besides, the circuit needs to have a stable mechanism which can stabilize bias circuit. The three issues deserve to discuss, and we need to find solutions. In the next section, NPVR is presented to solve the above issues.

3.3 NMOSFET and PMOSFET Voltage Reference (NPVR)

When we advance problem from ANVR, the second proposed architecture can be shown to solve the problem. Its abbreviation is NPVR which means 3.3

NMOSFET and PMOSFET Voltage Reference. The proposed architecture will introduce principle, derivation, and simulation in the next section.

Figure 3.3.1: Architecture of NPVR

M1 M2 M3 M4 M5 M6 M7 M8

W(μm) 1 1 1 1 1 1 0.5 0.92

L(μm) 0.2 0.2 0.2 0.2 0.2 0.2 0.2 0.2

m 8 8 8 8 16 16 8 8

3.3.1 Principle of NPVR

The circuit is composed of NMOS and PMOS. M1~M4, M7, and M8 are NMOS, and M5~M6 are PMOS. All MOS work in subthreshold region. The principle is like

ANVR. We use VGSp of M6 to produce VCTAT, and VDD subtract VCTAT to produce VPTAT. VPTAT is VGS3. Therefore, the current IPTAT is mirrored from M3 to M7. Beside, VGS8 is VCTAT. Finally, M*IPTAT and VGS8 trade-off, and a stable VREF is produced.

Because we hope that NPVR can operate under 1.5V, we choose VTH of MOS around 0.49V. Besides, we hope that proposed architecture’s power can be lower than the power of PAPER [2]. Therefore, we decide that supply voltage is 0.8V and total current is about 105nA. The each current of NPVR is about 35nA which is the same current at the architecture of PAPER [8]. Finally, we can know the size of MOS and the derivation can be shown in the next section.

3.3.2 Derivation of NPVR

The section will derivate VREF and illustrate every parameters. First, bias-circuit derivation is shown, and VREF-circuit derivation will be shown by bias-circuit derivation later. Therefore we can decide (W/L) and resistor by the derivation.

A. Bias-circuit simulation

M1~M6 are bias-circuit, and it is used to produce VPTAT. The function can be written as

( )

T V

( )

T V

( )

V_G₃ = _GS₁ + _GS₃ (3-17) Using the current function of MOS works in weak inversion, the function of (3-17) can be written as

( ) ( ) ( ) ( ) ( )

Therefore the bias-circuit derivation is done, and VG3 will be used latter.

VREF-circuit derivation

VREF can be written as the function

So we can bring (3-19) into (3-23), then the function of (3-24) will be shown.

( ) ( ) ( ) If we want VREF which does not change with temperature, dVREF/dT should be zero. n is subthreshold slope factor , P is (W/L), and

evK

And its differentiation is written as

( ) (

th KT KT V

dT T

dV = 1+ 2×

)

(3-27)

KT1 is temperature coefficient of the threshold voltage and KT2 is bulk-bias coefficient of the threshold voltage’s temperature dependence. dVTH(T)/dT can been decided when (W/L) had been decided. Therefore, dVREF(T)/dT can be zero by designing P1~P8.

3.3.3 Post-Layout Simulation of NPVR

The layout of NPVR is shown in Figure 3.3.3. The bias circuit is alternate permutation, so it can decrease mismatch. IPTAT will mirror from M3 to M7. NPVR has not used resistors, so it will be no resistor derivation. Because no resistors, the area is lower than (37*24)μm². In addition, dummy technique has been used in the layout, and it is also used to decrease process variation. Figure 3.3.2 shows presim of ANVR, and we can compare with Figure 3.3.3 which shows postsim of ANVR. They are almost the same.

All corners are shown from Figure 3.3.4 to Figure 3.3.8, and Table 3.3 shows Corner Post-layout Simulation Results of VREF. The inaccuracy of VREF can be lower than 0.5mV at TT corner, and temperature coefficient is 8.6 ppm/℃ at -80℃~165℃.

Beside, the inaccuracy of VREF can be lower than 0.1mV at TT corner, and temperature coefficient is 1.5 ppm/℃ at 0℃~100℃. The temperature coefficient of worst case is lower than 84 ppm/℃ at -80℃~165℃ in FS corner. See Table 3.4, it is specification of NPVR. Indeed, it reaches my goal.

-100 -50 0 50 100 150 200

237.6 237.7 237.8 237.9 238 238.1 238.2 238.3

Temperature=-80 to 165 DEC-C

Vref(T) mv

Temperature VS.Vref (TSMC 0.18um CMOS technology)

237.93mV

Figure 3.3.2: Presim of NPVR

Table 3.3: Post-Layout Simulation of NPVR PAPER

(year) VDD

(V)

Temperature Range

(℃)

Temperature Coefficient

(ppm/℃)

VREF (mV)

Tech.

(μm)

AREA (mm²)

PSRR (dB)

POWER (W)

NPVR 0.8 -80~165 -40~125

0~100

8.6 6.3 3.7

237.9 237.9 237.9

0.18 0.000888

(37*24)μm² 18

@10MHz 83n

Figure 3.3.3: Layout of NPVR in TSMC 0.18um CMOS Technique

A. Post-layout Simulation Results (VREF):

Figure 3.3.4: TT Corner of NPVR

Figure 3.3.5: FF Corner of NPVR

Figure 3.3.6: FS Corner of NPVR

Figure 3.3.7: SF Corner of NPVR

Figure 3.3.8: SS Corner of NPVR

B. Post-Layout Simulation Results (VREF):

Table 3.4: Corners of NPVR Post-Layout Simulation (VREF) Corner Temperature Range

(℃)

Temperature Coefficient (ppm/℃)

TT -80~165 8.6(0.5) -40~125 6.3(0.25) 0~100 3.7(0.09) FF -80~165 46.9(1.8)

-40~125 48.1(2) 0~100 43.7(1.2) SS -80~165 69.1(3.4)

-40~125 48.5(1.8) 0~100 51.1(1.2) SF -80~165 75(4.4)

-40~125 63.9(2.7) 0~100 62.4(1.6) FS -80~165 83.1(4.3)

-40~125 85.1(3.1) 0~100 81.6(1.9) ( ) is derivation of voltage reference, and its unit is mV.

3.3.4 Discussion of NPVR

NPVR reaches three goals. First, double mirror is used to stabilize VPTAT

produced circuit. Second, PSRR arise from 6.5dB to 10dB. NPVR has three MOS stack, and VPTAT is produced from M3. By this, VREF can resist the shake from VDD. Third, the area of NPVR decreases a little because we do not use resistors. Therefore, the performance of NPVR is better than ANVR. In Table 3.6, temperature coefficient, area, PSRR, and power consumption become better in NPVR.

Although NPVR has not bad performance, it still has two problems. First, start-up circuit is needed. Second, PSRR should improve. In next section, we will discuss the two problems carefully.

Table 3.5: Comparison between ANVR and NPVR PAPER

(year) VDD

(V)

Temperature Range

(℃)

Temperature Coefficient

(ppm/℃)

VREF (mV)

Tech.

(μm)

AREA (mm²)

PSRR (dB)

POWER (W)

NPVR 0.8 -80~165 -40~125

0~100

8.6 6.3 3.7

237.9 237.9 237.9

0.18 0.000888

(37*24)μm² 18

@10MHz 83n ANVR 0.8 -80~165

-40~125 0~100

34.4 27.7 16.7

356 356.7 356.7

0.18 0.00108

(30*36)μm² 7.5

@100kHZ 403.2n

3.4 NMOS PMOS and Capacitor Voltage Reference (NPCVR)

When we advance problem from NPVR, the second proposed architecture can be shown to solve the problem. Its abbreviation is NPCVR which means voltage reference with NMOS, PMOS, and capatitor. The proposed architecture will introduce principle, derivation, and simulation in the next section.

VDD

M2 M1

M4 M3

M6

M5 M7

M8

V

REF VPTAT

IPTAT1

IPTAT2

C1

C2

GND

Figure 3.4.1: Voltage Reference uses NMOS, PMOS, and Capacitor (NPCVR)

M1 M2 M3 M4 M5 M6 M7 M8 C1 C2

W(μm) 1 1 1 1 1 1 1 1.4 1pF 4pF

L(μm) 0.2

m 16

3.4.1 Start-up Circuit of NPCVR

In the Chapter 4, the measurement result of NPVR can discover that we can not measure VREF sometimes. It means that NPVR needs start-up circuit. Therefore, we use C1 to be start-up circuit. When supply voltage is zero, voltage of all points is zero.

Then supply voltage becomes 0.8V, M5 is PMOS and it will turn on. The current flows through M5, so VD5 and VG5 will be high. M5 turns off, but the current flows through C1 and VG4 become high which means that M4 turns on. Therefore, proposed architecture will keep working.

3.4.2 Power Supply Reject Ratio (PSRR)

ro4

Figure 3.4.2: Small Signal of NPCVR

In Figure 3.4.2, it is small signal of NPCVR. If we want to know PSRR, we should derivate the value of Vref/Vdd. The derivation is shown as follow.

Vref can be shown as the function of (3-28).

( )

Therefore, Vref/Vdd is about 10dB, and it means PSRR is 10dB in zero frequency.

It is a disadvantage at proposed architectures, and it is hard to change. But we still can pull up PSRR at higher frequency. A capacitor which is put in output is a method to

pull up PSRR. We know that pole is 1/(R*C) and main pole is in output. If we put a capacitor which is 4pF in output, the main pole will move to lower frequency. By this, PSRR will pull up at higher frequency. See Figure 3.4.3, PSRR is shown from 0Hz to 10MHz, and PSRR of NPCVR is better than NPVR.

Figure 3.4.3: PSRR of NPCVR

3.4.3 Post-Layout Simulation of NPCVR

The performance of NPCVR is shown at Table 3.6. Although, the area and power of NPCVR is bigger than NPVR. But they are still smaller than other papers, and the comparison will be shown in the next section. Layout of NPCVR is shown at Figure 3.4.4 and the area is (105*95)μm². All corners are shown at Figure 3.4.5~Figure 3.4.9.

Table 3.6: Post-Layout Simulation of NPCVR PAPER

(year) VDD

(V)

Temperature Range

(℃)

Temperature Coefficient

(ppm/℃)

VREF (mV)

Tech.

(μm)

AREA (mm²)

PSRR (dB)

POWER (W)

NPCVR 0.8 -40~125 0~100

14.68 10.39

228 228

0.18 0.001mm² (105*95)μm²

47dB

@10MHz 152n

Figure 3.4.4: Layout of NPCVR A. Post-layout Simulation Results (VREF):

-40 -20 0 20 40 60 80 100 120 140

227.65 227.7 227.75 227.8 227.85 227.9 227.95 228

Temperature=-40 to 125 DEC-C

Vref(T) mv

Temperature VS.Vref (TSMC 0.18um CMOS technology)

227.82mV

Figure 3.4.5: TT Corner of NPCVR

-40 -20 0 20 40 60 80 100 120 140 235.5

236 236.5 237 237.5 238

Temperature=-40 to 125 DEC-C

Vref(T) mv

Temperature VS.Vref (TSMC 0.18um CMOS technology)

236.7mV

Figure 3.4.6: FF Corner of NPCVR

-40 -20 0 20 40 60 80 100 120 140

203.5 204 204.5 205 205.5 206 206.5 207 207.5

Temperature=-40 to 125 DEC-C

Vref(T) mv

Temperature VS.Vref (TSMC 0.18um CMOS technology)

205.5mV

Figure 3.4.7: FS Corner of NPCVR

-40 -20 0 20 40 60 80 100 120 140 249.5

250 250.5 251 251.5 252 252.5

Temperature=-40 to 125 DEC-C

Vref(T) mv

Temperature VS.Vref (TSMC 0.18um CMOS technology)

251mV

Figure 3.4.8: SF Corner of NPCVR

-40 -20 0 20 40 60 80 100 120 140

218 218.5 219 219.5 220 220.5

Temperature=-40 to 125 DEC-C

Vref(T) mv

Temperature VS.Vref (TSMC 0.18um CMOS technology)

219.4mV

Figure 3.4.9: SS Corner of NPCVR

C. Post-Layout Simulation Results (VREF):

Table 3.7: Corners of NPCVR Post-Layout Simulation (VREF)

Corner Temperature Range

(℃)

Temperature Coefficient (ppm/℃) ( ) is derivation of voltage reference, and its unit is mV.

3.4.4 Discussion of NPCVR

As shown in Table 3.9, it is shown that PSRR is pull up to 47dB at 10MHz. The performance does not change very much, and PSRR becomes high a lot. Otherwise, NPCVR has start-up circuit to improve the question of NPVR. In the next section, we will show all papers and proposed architectures to compare the performance.

Table 3.8: Comparison between NPVR and NPCVR PAPER

0.18 0.001mm² (105*95)μm²

0.18 0.000888 (37*24)μm²

@100kHZ 83n

3.5 Comparison

Three proposed architectures and researches are compared at Table 3.10.

Obviously, the performance of proposed architectures is good by comparing all researches. Let’s see the performance one by one.

1. Supply Voltage: Supply voltage of proposed architectures is the lowest voltage in all researches. We know that power is supply voltage to multiply total current, so low supply voltage is easy to get low power. It means that proposed architectures can apply to low power systems.

2. Temperature Range: Proposed temperature range is the widest temperature range which is -40℃ ~ 125℃ in all researches. Even it can apply at the space.

在文檔中操作於弱反轉層場效電晶體之極低功率損耗與極小面積CMOS參考電壓之設計與實現 (頁 35-0)