Chapter 3 Circuitry Architecture
3.3 NMOSFET and PMOSFET Voltage Reference (NPVR)
3.3.4 Discussion of NPVR
NPVR reaches three goals. First, double mirror is used to stabilize VPTAT
produced circuit. Second, PSRR arise from 6.5dB to 10dB. NPVR has three MOS stack, and VPTAT is produced from M3. By this, VREF can resist the shake from VDD. Third, the area of NPVR decreases a little because we do not use resistors. Therefore, the performance of NPVR is better than ANVR. In Table 3.6, temperature coefficient, area, PSRR, and power consumption become better in NPVR.
Although NPVR has not bad performance, it still has two problems. First, start-up circuit is needed. Second, PSRR should improve. In next section, we will discuss the two problems carefully.
Table 3.5: Comparison between ANVR and NPVR PAPER
(year) VDD
(V)
Temperature Range
(℃)
Temperature Coefficient
(ppm/℃)
VREF (mV)
Tech.
(μm)
AREA (mm2)
PSRR (dB)
POWER (W)
NPVR 0.8 -80~165 -40~125
0~100
8.6 6.3 3.7
237.9 237.9 237.9
0.18 0.000888
(37*24)μm2 18
@10MHz 83n ANVR 0.8 -80~165
-40~125 0~100
34.4 27.7 16.7
356 356.7 356.7
0.18 0.00108
(30*36)μm2 7.5
@100kHZ 403.2n
3.4 NMOS PMOS and Capacitor Voltage Reference (NPCVR)
When we advance problem from NPVR, the second proposed architecture can be shown to solve the problem. Its abbreviation is NPCVR which means voltage reference with NMOS, PMOS, and capatitor. The proposed architecture will introduce principle, derivation, and simulation in the next section.
VDD
M2 M1
M4 M3
M6
M5 M7
*M
M8
V
REF VPTATIPTAT1
IPTAT2
C1
C2
GND
Figure 3.4.1: Voltage Reference uses NMOS, PMOS, and Capacitor (NPCVR)
M1 M2 M3 M4 M5 M6 M7 M8 C1 C2
W(μm) 1 1 1 1 1 1 1 1.4 1pF 4pF
L(μm) 0.2
m 16
3.4.1 Start-up Circuit of NPCVR
In the Chapter 4, the measurement result of NPVR can discover that we can not measure VREF sometimes. It means that NPVR needs start-up circuit. Therefore, we use C1 to be start-up circuit. When supply voltage is zero, voltage of all points is zero.
Then supply voltage becomes 0.8V, M5 is PMOS and it will turn on. The current flows through M5, so VD5 and VG5 will be high. M5 turns off, but the current flows through C1 and VG4 become high which means that M4 turns on. Therefore, proposed architecture will keep working.
3.4.2 Power Supply Reject Ratio (PSRR)
ro4
Figure 3.4.2: Small Signal of NPCVR
In Figure 3.4.2, it is small signal of NPCVR. If we want to know PSRR, we should derivate the value of Vref/Vdd. The derivation is shown as follow.
Vref can be shown as the function of (3-28).
( )
Therefore, Vref/Vdd is about 10dB, and it means PSRR is 10dB in zero frequency.It is a disadvantage at proposed architectures, and it is hard to change. But we still can pull up PSRR at higher frequency. A capacitor which is put in output is a method to
pull up PSRR. We know that pole is 1/(R*C) and main pole is in output. If we put a capacitor which is 4pF in output, the main pole will move to lower frequency. By this, PSRR will pull up at higher frequency. See Figure 3.4.3, PSRR is shown from 0Hz to 10MHz, and PSRR of NPCVR is better than NPVR.
Figure 3.4.3: PSRR of NPCVR
3.4.3 Post-Layout Simulation of NPCVR
The performance of NPCVR is shown at Table 3.6. Although, the area and power of NPCVR is bigger than NPVR. But they are still smaller than other papers, and the comparison will be shown in the next section. Layout of NPCVR is shown at Figure 3.4.4 and the area is (105*95)μm2. All corners are shown at Figure 3.4.5~Figure 3.4.9.
Table 3.6: Post-Layout Simulation of NPCVR PAPER
(year) VDD
(V)
Temperature Range
(℃)
Temperature Coefficient
(ppm/℃)
VREF (mV)
Tech.
(μm)
AREA (mm2)
PSRR (dB)
POWER (W)
NPCVR 0.8 -40~125 0~100
14.68 10.39
228 228
0.18 0.001mm2 (105*95)μm2
47dB
@10MHz 152n
Figure 3.4.4: Layout of NPCVR A. Post-layout Simulation Results (VREF):
-40 -20 0 20 40 60 80 100 120 140
227.65 227.7 227.75 227.8 227.85 227.9 227.95 228
Temperature=-40 to 125 DEC-C
Vref(T) mv
Temperature VS.Vref (TSMC 0.18um CMOS technology)
227.82mV
Figure 3.4.5: TT Corner of NPCVR
-40 -20 0 20 40 60 80 100 120 140 235.5
236 236.5 237 237.5 238
Temperature=-40 to 125 DEC-C
Vref(T) mv
Temperature VS.Vref (TSMC 0.18um CMOS technology)
236.7mV
Figure 3.4.6: FF Corner of NPCVR
-40 -20 0 20 40 60 80 100 120 140
203.5 204 204.5 205 205.5 206 206.5 207 207.5
Temperature=-40 to 125 DEC-C
Vref(T) mv
Temperature VS.Vref (TSMC 0.18um CMOS technology)
205.5mV
Figure 3.4.7: FS Corner of NPCVR
-40 -20 0 20 40 60 80 100 120 140 249.5
250 250.5 251 251.5 252 252.5
Temperature=-40 to 125 DEC-C
Vref(T) mv
Temperature VS.Vref (TSMC 0.18um CMOS technology)
251mV
Figure 3.4.8: SF Corner of NPCVR
-40 -20 0 20 40 60 80 100 120 140
218 218.5 219 219.5 220 220.5
Temperature=-40 to 125 DEC-C
Vref(T) mv
Temperature VS.Vref (TSMC 0.18um CMOS technology)
219.4mV
Figure 3.4.9: SS Corner of NPCVR
C. Post-Layout Simulation Results (VREF):
Table 3.7: Corners of NPCVR Post-Layout Simulation (VREF)
Corner Temperature Range
(℃)
Temperature Coefficient (ppm/℃) ( ) is derivation of voltage reference, and its unit is mV.
3.4.4 Discussion of NPCVR
As shown in Table 3.9, it is shown that PSRR is pull up to 47dB at 10MHz. The performance does not change very much, and PSRR becomes high a lot. Otherwise, NPCVR has start-up circuit to improve the question of NPVR. In the next section, we will show all papers and proposed architectures to compare the performance.
Table 3.8: Comparison between NPVR and NPCVR PAPER
0.18 0.001mm2 (105*95)μm2
0.18 0.000888 (37*24)μm2
18
@100kHZ 83n
3.5 Comparison
Three proposed architectures and researches are compared at Table 3.10.
Obviously, the performance of proposed architectures is good by comparing all researches. Let’s see the performance one by one.
1. Supply Voltage: Supply voltage of proposed architectures is the lowest voltage in all researches. We know that power is supply voltage to multiply total current, so low supply voltage is easy to get low power. It means that proposed architectures can apply to low power systems.
2. Temperature Range: Proposed temperature range is the widest temperature range which is -40℃ ~ 125℃ in all researches. Even it can apply at the space.
3. Temperature Coefficient: It is important authority of performance. Temperature coefficient of NPCVR is 14.68 ppm/℃ at -40℃ ~ 125℃. It is very low temperature coefficient and very wide temperature range. Even temperature coefficient has still 10.39 ppm/℃ at 0℃ ~ 100℃.
4. Area: The area of proposed architectures is low to several hundreds μm2. Indeed, it reaches the goal which is that proposed architectures can apply in battery-operated systems.
5. Power: The power of proposed architectures is low to several dozens nW. It truly achieves low power, and it is very suitable to apply in any low power systems.
The whole said that the performance of proposed architectures is better than the most researches. The result proofs that proposed architectures achieve our goal.
Table 3.9: Comparison of All Voltage Reference’s Architectures PAPER
0.18 0.001mm2
(105*95)μm2 47dB 152n NPVR 0.8 -40~125
0.18 0.000888
(37*24)μm2 18 83n
0.18 0.00108
(30*36)μm2 7.5 403.2n Voltage Mode of PTAT and CTAT * is that research has experimental result
*[1]2004 4.5~5 25~90 347 1320 0.18
*[2]2005 0.9 0~100 39 514 0.35 0.12 22 780n
*[3]2005 2 0~70 62 579 0.35 0.126 84 4.6u
*[4]2006 0.9~4 0~80 10 670 0.35 0.045 40 63n
[5] 2004 1.1~2.2 -10~70 85 504 0.18 176u
[6] 2005 3.3 0~150 26 711 0.35
[7] 2006 1.3 -50~130 9 546 0.18 100 80u
[8] 2006 0.5 -40~100 2.2 319 0.13 0.0002 14 40n Current Mode of PTAT and CTAT
*[9]2003 1.2 -25~125 119 295 1.2 0.23 40 4.32u
*[10]2006 0.85 -20~120 194 221 0.18 0.0238 3.3u
[11] 2003 0.6 -40~100 93 400 0.13
[12] 2003 1.5 -40~125 37.88 800 0.13 120u
[13] 2003 0.6~1.8 0~80 80 405 0.18 0.1 82 25u
[14] 2004 3~5 -60~100 4 1165.4 1.2 0.18 30u
[15] 2004 1 -20~80 200 400 0.35 3u
[16] 2004 0.8 0~100 33 592 0.6 0.05 50 0.88u
[17] 2005 1 -40~125 66.7 225 0.5 4u
[18] 2005 1.8 0~70 32.5 615.1 0.18 0.1 35 1.6u
[19] 2006 1.2 -20~90 61.64 718 0.09 1.6u
[20] 2006 0.8~2.6 -20~120 64.2 278 0.18 0.04 5.4u Voltage Reference Uses Parallel Voltages
*[21]2003 1.4 0~100 36.9 309 0.6 0.055 20 13.58u
*[22]2004 5 -10~80 32 2670 0.5 0.0936 970u
*[23]2005 1.5 0~80 25 168 0.35 0.08 59 3.6u
*[24]2006 1.5~4.3 0~80 12 891.1 0.35 0.015 59 300n [25] 2005 0.6~1.8 0~75 70 332 0.18
[26] 2006 0.9~3.3 -40~100 33 181 0.35 1.1u
ZTC
*[27]2001 3~3.3 -20~100 15 799 0.35 0.0204
[28] 2004 1 -50~150 4 640 0.18
[29] 2005 3.3 -50~120 50 821&1264 0.35 36.3u
Voltage Reference Uses Non-standard Process
*[30]2003 1 -50~100 80 410 0.6u
*[31]2004 2.8~5.5 -20~100 54.6 0.8~1.5 0.5 0.081 80 500u
*[32]2005 4.5~9 -40~85 1 1250~5000 1.5 1.6 67 3.15u
*[33]2006 1.2 -60~140 130 400 0.35 0.0022 40u
3.6 Summary
This chapter shows proposed architectures and discusses the proposed architectures. We simulate proposed architectures, and the performance is good at HSPICE simulation. But it does not mean that experimental results of chips are as good as HSPICE simulation. So the three proposed architectures had taped out in TSMC 0.18μm process. In the next chapter, experimental results will be shown.
CHAPTER
4
Measurement
Proposed design architecture ANVR and NPVR are taped out in TSMC 0.18um CMOS process technique. In this chapter, the measurement environment and method are shown first. Then experimental results of ANVR and NPVR are presented by figures and data. A comparison by proposed design architectures and researches is presented. Finally, we will illustrate the derivation between post-layout simulation and experimental results.
4.1 Measurement Set-up
In Figure 4.1, measurement environment is shown. The chip is put in a temperature and humidity chamber and other electronic devices which are batteries, voltage-stabilizer circuit, and oscilloscope is put outside. By this, the temperature variation only affects the measured chips and does not affect other electronic devices.
That is because we only want to know the effect of VREF which is measured from the chip when temperature changes from -40℃ to 125℃. If the other electronic devices are also affected by temperature, the measured VREF will be incorrect. Beside measurement environment mentions a temperature and humidity chamber. It can adjust and stabilize temperature from -75℃ to 165℃ and the deviation of temperature is lower than 0.1℃. It will be useful to measure a correct voltage reference.
Figure 4.1: Block Diagram of Measurement Environment
In Figure 4.2, it shows a voltage-stabilizer circuit which is composed of a IC(LM317), resistors, capacitors, inductors, and a diode(1N5402). Because proposed design architectures need 0.8V to be a supply voltage, the voltage-stabilized circuit must to have two parts. First part is conventional voltage-stabilized circuit which can produce and stabilize a voltage of 1.2V. Second part is series voltage-stabilized circuit which further decreases 1.2V to 0.8V. Of course, it has also the function of voltage-stabilized. By this, a stable supply voltage provides to the measured chips.
Figure 4.2: Block Diagram of Voltage-Stabilized Circuit
Measurement environment is shown in Figure 4.3. The right side of Figure 4.3 is a temperature and humidity chamber and the PCB is put inside. The PCB is shown at
the under side of Figure 4.3. One PCB has four chips because it can save measurable time.
Figure 4.3: The Pictures of Measurement Environment
4.2 Experimental Result
In this section, experimental results will be presented and illustrated. Then a comparison which has proposed design architectures and researches is shown by table.
By this, it can prove that proposed design architectures are suitable for battery-operated system.
4.2.1 Experimental Result of ANVR
Experimental results of proposed design architecture ANVR is shown at Figure 4.4. The lowest voltage is 354mV and the highest voltage is 360mV at the different chips. The largest derivation is lower than 6mV and it is the worst case. The experimental results show temperature range of -40℃~125℃. Although temperature range of post-layout simulation is -80℃~165℃, the HSPICE model only support temperature range of -40℃~125℃.
Figure 4.4: Experimental Result of ANVR Table 4.1: The Derivation for VREF of ANVR
Temperature(℃) -40~125 0~100
Simulation(mV) 356.67±0.82 357.2±0.3
CHIP 1-9(mV) 357.08±1.85 358.16±0.77
CHIP 1-11(mV) 356.64±1.57 358.2±0.67
CHIP 1-12(mV) 356.32±2.03 357.47±0.88
CHIP 1-14(mV) 357.22±2.04 358.62±0.62
CHIP 1-15(mV) 357.27±1.92 358.4±0.93
CHIP 1-16(mV) 358.1±2.1 359.32±0.87
Table 4.1 shows the derivation of VREF for proposed design architecture ANVR.
The best case is CHIP 1-11 which derivation is only ±1.57mV and ±0.67mV when temperature range is -40℃~125℃ and 0℃~100℃. Although experimental results are not better than simulation, the voltage derivation has only several milli-Volt at temperature range of -40℃~125℃. Table 4.2 shows experimental results of ANVR.
The power is not larger than 450nW, and PSRR is about 10dB. The worst temperature
coefficient is 70ppm/℃, and it is not as good as post-layout simulation. Beside measurable error, we need to find out the source of inaccuracy.
Table 4.2: Experimental Results of ANVR
Simulation 1-9 1-11 1-12
Supply voltage 0.8v
Temperature range -40℃~125℃
0℃~100℃
Temperature coefficient 27.7ppm/ ℃ 16.8ppm/ ℃
Power 403.2nA 436nA 436nA 445nA
Area 0.00108mm2
Tech. 0.18μm
Simulation 1-14 1-15 1-16
Supply voltage 0.8v
Temperature range -40℃~125℃
0℃~100℃
Temperature coefficient 27.7ppm/ ℃ 16.8ppm/ ℃
Power 403.2nA 428nA 431nA 423nA
Area 0.00108mm2
Tech. 0.18μm
See Table 4.3, it shows resistor variation which may cause the inaccuracy of VREF. We use P+ Poly w/i Silicide as a resistor of ANVR. However, every 7.9 ohm has ± 2.5 ohm variation that is large error to affect VREF. Therefore, resistor variation is possible source of VREF derivation.
Table 4.3: Resistor Variation
Film Valid
Width
Rsh
Mean/Range
Unit
P+ Poly w/i Silicide
W≥2.0 7.9± 2.5 Ω/sq
4.2.2 Experimental Result of NPVR
Experimental results of proposed design architecture NPVR is shown at Figure 4.6.
The derivation is lower than several milli-Volt, but it does not match with post-layout simulation. The lowest voltage is 236mV and the highest voltage is 238mV at the different chips. The largest derivation is lower than 2mV and it is the worst case. The experimental results show temperature range of -40℃~125℃. Although temperature range of post-layout simulation is -80℃~165℃, the HSPICE model only support temperature range of -40℃~125℃.
-40 -20 0 20 40 60 80 100 120 140 236
236.5 237 237.5 238 238.5
Temperature=-40 to 125 DEC-C
Vref(T) mv
Temperature VS.Vref (TSMC 0.18um CMOS technology)
2-9
2-14 2-16 Simulation
2-10
Figure 4.5: Experiment Results of NPVR Table 4.4: The Derivation of VREF for NPVR
Temperature(℃) -40~125 0~100
Simulation(mV) 237.8±0.125 237.7±0.05
CHIP 1-9(mV) 237.2±0.66 237.59±0.27
CHIP 1-14(mV) 236.81±0.63 237.09±0.35
CHIP 1-16(mV) 236.89±0.77 237.22±0.45
The best case is CHIP 1-9 which derivation is only ±0.66mV and ±0.27mV when temperature range is -40℃~125℃ and 0℃~100℃. Although experimental results are not better than simulation, the voltage derivation has only several milli-Volt at temperature range of -40℃~125℃. Table 4.5 shows experimental results of NPVR.
The power is not larger than 120nW, and PSRR is about 20dB. The worst temperature coefficient is 40ppm/℃, and it is not as good as post-layout simulation. Beside measurable error, we need to find out the source of inaccuracy.
Table 4.5: Experimental Results of NPVR
33.7ppm/℃ 32.25ppm/℃
29.52ppm/℃
237.12 236.81 237.09
Power 83nA 113nA 105nA 102nA 117nA
Area 0.00088mm2
Tech. 0.18μm
When measuring VREF, we sometimes measure no value. The source is that NPVR needs a start-up circuit. It can make NPVR work in right situation. The start-up circuit had been illustrated at Chapter 3.
Table 4.6: Process Variation of VREF
-40~125 M1 M2 M5 M6
0% variation 0.26mV 0.26mV 0.26mV 0.26mV
1% variation 2.3mV 2.6mV 2.3mV 2mV
We do Monte Carlo Analysis for NPVR, and we discover that process variation is easy to affect M1, M2, M5, and M6, in Figure 4.6. The issue causes that voltage derivation increases a lot, and temperature coefficient of experimental results is not match temperature coefficient of post-layout simulation. We use Monte Carlo analysis which we give 1% variation to simulate M1, M2, M5, and M6, and Table 4.6 shows the result of Monte Carlo analysis. If width and length has no variation, the derivation is 0.26mV when temperature range is -40℃~125℃. However we give width of M1, M2, M5, and M6 1% variation, the derivation of VREF will become from 0.26mV to
2.6mV. The derivation only has several milli-Volt, but temperature coefficient will become from 6.3ppm/℃ to 40 ppm/℃. This might be the source of inaccuracy, and it caused the derivation of VREF.
Figure 4.6: Process Variation of NPVR
4.2.3 Discussion of ANVR and NPVR
In Chapter 3, NPCVR uses capacitors which are put in output to increase PSRR.
When measuring, we can add a capacitor in output of chip in order to prove the method being useful. See Table 4.7, the measured PSRR of every chips are higher than 54dB, and the results prove the method to be useful.
Table 4.7: PSRR of NPVR (4pF in output)
Simulation 1-9 1-10 1-14 1-16 average PSRR 54dB
@10MHz
57dB
@10MHz
56dB
@10MHz
58dB
@10MHz
57dB
@10MHz
57dB
@10MHz
4.2.4 Comparison of ANVR and NPVR
We have post-layout simulations and experimental results now, so their comparison is shown at Table 4.8. Experimental results are chosen from the best chips as the compared target. We can know that temperature coefficient of measurement is lower than that of simulation. The performance of measurement is not better than that of simulation indeed, but we have illustrated the source at the above section. The next section will compare between experimental results of proposed architectures and researches. Proposed architectures still have many advantages after comparing.
Table 4.8: Comparison of Post Layout Simulation and Experimental results Proposed
Table 4.9: Comparison of Taped-out Voltage Reference’s Architectures
0.18 0.000888
(37*24)μm2 20.2 113n
0.18 0.00108
(30*36)μm2 11.1 436n
Current Mode of PTAT and CTAT
*[9]2003 1.2 -25~125 119 295 1.2 0.23 40 4.32u
*[10]2006 0.85 -20~120 194 221 0.18 0.0238 3.3u
Voltage Reference Uses Parallel Voltages
*[21]2003 1.4 0~100 36.9 309 0.6 0.055 20 13.58u Voltage Reference Uses Non-standard Process
*[30]2003 1 -50~100 80 410 0.6u
*[31]2004 2.8~5.5 -20~100 54.6 0.8~1.5 0.5 0.081 80 500u
*[32]2005 4.5~9 -40~85 1 1250~5000 1.5 1.6 67 3.15u
*[33]2006 1.2 -60~140 130 400 0.35 0.0022 40u
A comparison of taped-out voltage reference’s architectures is shown at Table 4.8.
It lists researches of voltage reference which has taped-out in the recent six years and proposed design architectures. See the Table 4.9, proposed architectures have many advantages. First, supply voltage is lower than others. Second, temperature range is the widest range. Third, temperature coefficient is not smaller than others though. But we have illustrated the source in the above section. Forth, the areas of proposed architectures are the smallest. Fifth, power is lower than the most researches, and it
only consumes several hundred nano-Watt. Therefore, it is feasible that proposed architectures can be used in battery-operated systems. And, the performance of proposed architectures is better than the most researches.
4.3 Summary
The section introduces measurable method and experimental results of proposed design architectures. Then we illustrate the source of bad temperature coefficient, and a comparison is shown and is discussed. But proposed design architectures have many advantages which are low-power, wide temperature range, and low-area. It is more adaptable to use proposed design architectures in battery-operated system. In the next chapter, conclusions will be shown and future works will be illustrated.
CHAPTER
5
Conclusion and Future Works
In the above chapter, experimental results were shown and illustrated. A comparison of proposed architectures and researches is presented after showing experimental results. Now, this chapter will arrange conclusions and future works.
And all references are shown below conclusions and future works.
5.1 Conclusion
On the beginning this theis, we review bandgap reference, and a comparison between BJT and CMOS. After illustrating their advantages and disadvantages, we choose CMOS as the device which is used to design voltage reference. In the recent several years, CMOS voltage reference has many different design architectures. They are assorted five types, and the classified basis is the produced method of CMOS voltage reference. After comparison, voltage mode of VPTAT and VCTAT is more suitable than other architectures. Therefore, proposed architectures are designed in accordance with this type.
In this thesis, proposed architectures have been fabricated by TSMC 0.18um 1P6M process technique and they are introduced in chapter 3. We know that proposed architectures have reached successfully several goals. First, Low Power- The power consumption of ANVR and NPVR are 403.2nW and 83nW. Small Area- The area of ANVR and NPVR are 1080um2 and 888um2. Wide Temperature Range- The valid
temperature range is from -40℃ to 125℃, and temperature derivation is lower at temperature range from 0℃ to 100℃. High Accuracy- Temperature derivation has only several mV at temperature range from 0℃ to 100℃.
Because those goals are accomplished, proposed architectures can apply successfully in battery-operated systems. We can discover that the most demands are better than the goal which was presented in the Chapter 3.1. However, temperature coefficient does not reach the goal. The issue has been illustrated in Chapter 4.
Although temperature coefficient is not good enough, the derivation is only several mV. It is sufficient to apply in battery-operated system.
Although proposed architectures have been accomplished the above goals, they still have some problems which need to be improved. In the next section, these issues will be illustrated and discussed.
5.2 Future Works
In this section, we discuss the insufficiencies which need to be improved at proposed architectures. First, process variation is easy to affect voltage reference.
Because ALL MOS work in subthreshold region, process variation is very serious.
Second, PSRR is lower, and it causes that voltage reference is easy to change with supply voltage. If the issues can be solved, the experimental results will become better.
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