Up-Conversion Mixer

The concept of the current-operated self-switching up-conversion mixer comes from [19]. The concept diagram of the designed mixer is shown in Fig. 3.2. Two current signals of IF and LO are summed together. The summed current signal is then passed through the self switch. This switch is called self switch because the summed current signal is not only its input but its control signal. Therefore, the switch is turned

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on if the level of the summed current signal is larger than turn-on threshold current ITH

of the switch. Therefore, only the current signal larger than ITH is appeared at the output of the switch. The fully balance structure which is composed of Path-A and Path-B is selected to eliminate non-ideal effect. Consequently, the mixing function can be achieved, and it can be applied to realize a differential up-conversion mixer.

The operation principle in terms of waveform for this designed mixer is illustrated in Fig. 3.3. According to the Fig. 3.2, the input signals are one low-frequency current signal IF (iif+ or iif–) and one high-frequency current signal LO (ilo+ or ilo–) in each path, as shown in Stage-I in Fig. 3.3. The adding signal (iif+

+ i

lo+ or iif–

– i

lo–) shown in Stage-II is the linear combination of these two current signals. The output signals of self switch (irf1 and irf2) are given by the Stage-III. Because of the characteristics of the self switch, the specific period of waveform that their amplitudes are larger than the ITH will be remained and pass through the self switch. After linear combined these two signals, the mixing function can be done as shown in Stage-IV. Larger (Fig. 3.4) or smaller ITH (Fig. 3.5) will produce worse performance. The extremely case is shown in Fig. 3.6. The switches always turn off or turn on and the resultant output is eliminated.

Therefore, the biasing condition must be carefully considered in order to guarantee the ITH level the same as in Fig. 3.3.

The detailed description is derived in (3.1)–(3.8). The Path-A and Path-B signals in Stage-I are shown in (3.1)–(3.2), respectively. In (3.1), A is the amplitude of the IF signal, ωIF is the frequency of the IF signal, B is the amplitude of LO signal, and ωLO is the frequency of the LO signal. The adding signals in Stage-II are (3.3)–(3.4). After the adding signals of IF and LO go through the self switch, the output signals of the switch,

i

rf1

(t) and i

rf2

(t), can be regarded as the adding signals multiplied by repeating 1,0,1,0,...

pulse with the LO signal cycles. After Fourier transforming, irf1

(t) in Stage-III can be

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expressed as (3.5) where the IF and LO signals are given by (3.1). Similarly, signal

i

rf2

(t) in path-B can be expressed by (3.6). Thus the adding signal i

rf

(t) (= i

rf1

(t) + i

rf2

(t))

in Stage-IV can be expressed by (3.7), just like the mixing waveform irf

(t) illustrated in

Fig. 3.3. After output LC tank, the output signal remains only the mixing term in (3.8).

According to the equations above, it is obvious that this mixing concept can be implemented in current-mode operation.

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The circuit realization is given by Fig. 3.7–3.9. I-V transfer and current-adding circuits are shown in Fig. 3.7. I-V transfer-function for IF and LO signals are implemented by PMOS (M1) and NMOS (M2), respectively. Because of the current-mode operation, these two current signals are added at the drain terminal of M1

and M2 (node A1) in a wired-OR manner without any extra circuits. Comparing to two common-source NMOS, the DC current can be re-used and resultant power consumption of whole transmitter front-end can be lower. The self-switching function is realized by M3 in Fig. 3.8, where the iif+

(t) and i

lo+

(t) are given in (3.1) and I

IFB/ILOB

is the DC current of IF/LO.

The source terminal of the transistor M3 is also connected to this terminal. IIFB and ILOB are set to IIFB = –ILOB so that M3 is turned off when iif+

(t) and i

lo+

(t) are not applied.

This condition means ITH = 0 in Fig. 3.2 and Fig. 3.3. Furthermore, M3 is turned on when IF and LO signals are input and iif+

(t) + i

lo+

(t) > 0. This indicated that the

transistor M3 detects the polarity of iif+

(t) + i

lo+

(t) and is switched on by the polarity. In

this way, the current adding and self-switching circuits is realized using current-mode operations.

Because of the characteristics of self-switching transistor M3, any drifted ITH level result in the VGS of switch transistor M3 will affect its characteristic and degrade the performance of this mixer as shown in Fig. 3.4–Fig. 3.6. Thus some extra circuits are adopted in order to fix the biasing point of the internal node A1. The negative feedback is realized by OPAMP, as shown in Fig. 3.9.

The schematic of the designed mixer is shown in Fig. 3.10. The IF and LO frequency are 100 MHz and 23.9 GHz, respectively, in this designed mixer. M1,4 and M2,5 are operated in the saturation region and functioned as transconductors that transform the voltage signals of IF and LO into current signals. For maximizing

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conversion gain, “VDD/2” is chosen for VA1 and VA2, the DC bias of the internal nodes A1 and A2. The gate biasing points for these four transconductors are chosen by the optimal linearity for each of them. The gate-to-source voltage of M3 and M6, VGS3 and VGS6, are designed to equal to their respective threshold voltage VTH3 and VTH6 such that the characteristic of self switch can be achieved. Because the different value of VGS, no matter higher or lower, will reduce amplitude of output RF signal, the VGS of M3 and M6 must be fixed. The DC biases VB1 and VB2 are carefully designed in order to achieve the condition of VGS=VTH. Besides, two operational amplifiers (OPAMPs) with the configuration of differential input single-ended output shown in Fig. 3.11 are used to implement negative feedback loops so that the DC bias of the internal nodes VA1 and VA2 are virtual short to the biasing voltage VREF. Therefore, the DC biasing points of the sources of M3 and M6 can be fixed, and the voltage of VREF is chosen as VREF=VB2–VTH3,6. The schematic and the results for simulating this feedback loop are shown in Fig. 3.12 and Fig. 3.13, respectively. According to Fig. 3.13, the phase margin of this loop is large than 50^o.

For transconductors M1,4 and M2,5, larger size of them can provide larger transconductance. In RF systems, however, serious parasitic effect comes up with large transistor’s size. For low-IF or direct conversion receiver front-end circuits, it can be resonated out simultaneously by only one inductor because the frequency of input signals RF and LO are almost the same. Unfortunately, this situation will never occur in transmitter front-end unless the impractical specification that IF and LO frequencies are exactly equal to half of the RF frequency. That is, the IF and LO frequencies are too different to simultaneously resonate out the parasitic capacitance at nodes A1 and A2 simultaneously. Therefore, large transistor provides large transconductance, but a huge and un-removable parasitic capacitance is also donated to the circuit. Because

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any parasitic capacitance can be regarded as an equivalent short path for high frequency, it may degrade RF signal by leakage RF signal to ground. The optimized sizes of these four transistors are determined by largest amplitude of current signals after I-V conversion.

In order to provide lower impedance that the adding signal of IF and LO can easily flow into self-switching circuit, the dimension of self-switching transistors M3

and M6 are designed as large as possible. However, just like the transconductance transistors, these self-switching transistors are suffered from the same situation that large size can provide lower impedance for adding signal but serious and un-removable parasitic problem at their source terminals. The sizes of these two transistors are optimized by the largest current amplitude of RF signal at output node of mixer.

The LO input matching network is composed of R1, R2, XFMR2, C3, and the parasitic capacitance of the LO input pad CPAD3. Input matching network for 100-MHz IF signal is not integrated on chip. Instead, as shown in Fig. 3.14, two off-chip biased-tees (C1, C2, L1 and L2) and an off-chip transformer (XFMR1) are required during measurement. The inductor L3 and parasitic capacitance at output node, drain terminals of M3 and M6, are implemented for output LC tank that functions as a filter and only passes desired RF signal to power amplifier.

The voltage headroom required at the nodes A1 and A2 is “2×VDSAT +ΔV”, which ΔV is signal voltage swing. It is the same as the nodes B1 and B2 in conventional Gilbert mixer shown in Fig. 3.15. In Gilbert mixer, however, the output node is high impedance node and directly proportional to its conversion gain. Thus the voltage swing at the output node of Gilbert mixer must be large. In designed current-operated self-switching mixer, the node A1 and A2 are low impedance nodes because that the

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sizes of M3 and M6 are large enough so that the current signal can pass though them.

Because the signal information is mainly carried by the current swing, the voltage swing is much smaller that that in Gilbert mixer. That is, the required ΔV is much smaller than that in Gilbert mixer. Comparing with the conventional Gilbert mixer, consequently, the designed current-operated self-switching mixer has better linearity if the supply voltage is the same, or supply voltage can be reduced if the linearity specification is the same. Thus the self-switching mixer in current-mode approach has great potential to operate in low supply voltage in advanced nanometer CMOS technology.

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