Power Amplifier

As to power amplifier, the most critical node is its output because high output power and resultant large voltage and current swing are required. Large output power which implies to large DC bias means the reliability such as metal current density must be considered. Besides, large voltage and current swing which implies to large-signal operation must be considered instead of small-signal operation. Therefore, for RF systems’ power amplifiers, the output impedance transformation networks (output matching networks) are always implemented by load-line or load-pull analysis instead of traditional conjugate match.

The traditional conjugate match can provide maximal power transfer only under the condition of no current and voltage swing limitation. It is always true for small-signal operation. That is why most of RF systems, such as receiver, adopt traditional conjugate match for their matching networks. However, transmitter front-end, especially for output of power amplifier, is large-signal operation. It is because that power amplifiers always produce high output power, the current or voltage swing always reaches the limitation of its supply. Therefore, instead of

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traditional conjugate match, the output matching networks of power amplifiers are usually determined by two methods – load-line or load-pull.

A quantitative description is given by Fig. 3.16 for the difference of optimal load if the voltage and current swing are limited. For traditional conjugate match, the load resistance RL is chosen to equal to RS. If the voltage and current swing are limited, however, it is clear that the “VMAX/IMAX” load resistance have maximal output power than any other load resistance.

The load-line analysis on a common-source transistor I-V curve is illustrated in Fig. 3.17. The load-line shown by black color is the optimal load resistance determined by load-line analysis. It is obvious that the load-line has maximal output power under this voltage and current swing limitation. Any load resistance which is smaller than the optimal resistance will have the same current swing but smaller voltage swing and resultant smaller output power. Any load resistance which is larger than the optimal resistance will have the same voltage swing but smaller current swing and resultant smaller output power. The hand-calculated procedure for load-line analysis can be accessed through (3.9)–(3.10). The transistors’ sizes (in terms of DC current) and optimal load resistance can be calculated as long as the required output power is given.

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From the figures and equations of load-line analysis above, it is not difficult to notice that load-line analysis can be used for quickly determining optimal load resistance, but not reactance. Because load-line analysis bases on I-V curve, the junction parasitic effect is exclusive. That is, only the real part of the load impedance (ZL) can be determined by this analysis, the effect of imaginary part cause by the parasitic effect of the circuit will be completely neglected. Unfortunately, the parasitic effect induce lose for high frequency signal. Besides, the larger size of the transistor it is, the parasitic effect is worse and cannot be ignored.

Comparing to load-line, load-pull analysis can be used to determine the load impedance ZL, both real and imaginary part, of power amplifiers. The load-pull analysis, shortly, is to sweep ZL to see how PAs perform. The analysis procedure is：

First, add a load tuner at the output of power amplifier. Second, sweep the value of load tuner (ZL) to see the difference of output power (POUT) and PAE. Because of each point on Smith chart is a reflection coefficient, and the reflection coefficient and impedance are one-to-one mapping for 50-ohm characteristic impedance, the swept data can be used to construct constant POUT and constant PAE contours. Third, choose one reflection coefficient (load impedance) on Smith chart by trade-off between constant POUT and constant PAE contours. Using load-pull analysis to determine ZL

has several advantages. Because the constant POUT and PAE contours are drawn on the same Smith chart, it is easy and obvious to trade-off between them. Besides, because of the one-to-one mapping characteristic, both real and imaginary part of ZL can be determined as soon as the trade-off point has been chosen.

Another difficulty for designing power amplifier is the parasitic effect. Because high output power is required, a cumbersome size of each transistor and resultant seriously parasitic effect are inevitable. Large parasitic capacitance CGD provides a

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short path between input and output at high frequency in common-source amplifier.

Therefore, a resonated inductor (LRES) must be used between these two nodes shown in Fig. 3.18 for resonating parasitic capacitance CGD and improving reverse isolation.

The small-signal model for a common-source amplifier is shown in Fig. 3.19.

Because the S-parameter S12 is desired, input phasor E2 is placed at port 2 (drain).

According to the definition of S12 shown in (3.11) [22], the term “VO1/E2” can be expressed by (3.12). Although (3.11) and (3.12) can show the effect for value of ZX, it is not obvious. In order to further simplify this equation, the matched condition at output node is assumed. This condition is always true for RF systems. The S22 of common-source amplifier can be calculated through (3.13) to (3.14). α and β are the substituted variables for the numerator and denominator in (3.13), respectively. Under the matched condition, the condition “ZO2β=α” can be derived as shown in (3.15).

Thus (3.12) can be further simplified by this derived condition and the final result for S12 of common-source amplifier is shown in (3.16).

For a traditional common-source amplifier, ZX is “1/jωCGD” and S12 will become (3.17). Thus larger the transistor size it is, larger the value of parasitic capacitance CGD

it has and worse the reverse isolation it becomes. For extremely case of infinitely large CGD value, the S12 will become the equation shown in (3.18) and equal to 1 (or 0 dB) in general for RF circuits (for ZO1 = ZO2 = ZO = 50 ohm, general case in RF circuits).

0-dB S12 means this circuit has no any reverse isolation or the equivalent circuit for this two-port network is short circuit. It is reasonable because the infinitely large CGD

provides a zero-impedance short path between port-1 and port-2.

If the resonated inductor LRES is adopted and placed between gate-drain, the impedance ZX in (3.16) will become (3.19). Thus S12 can be zero as long as the

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condition in (3.20) is achieved. That is the reason why a resonated inductor is always adopted for large-sized common-source amplifier.

O2 O1

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For RF system, an ideal inductor is equal to a short path for DC because its impedance is “jωL”. Therefore, as long as the resonated inductor is implemented, a blocking capacitor is always used for blocking unnecessary DC path. This blocking capacitor, CB, comes from the consideration during measurement. The cable inherent resistance between probe and DC power supply is around 3 ohm. It’s not a serious issue for small-signal systems such as receiver front-end. However, for hundreds milli-ampere transmitter front-end, it may cause milli-volt or even several volts drop during measurement. Because such voltage drop may downgrade internal biasing points by different levels, DC current may be sunk into unexpected path when measurement. In order to avoid this phenomenon, a capacitor must be added to block DC current from stage to stage.

Fig. 3.20 is the equivalent network between gate-drain of common-source transistor. Because CB is used for DC blocking, its value is much larger than parasitic capacitance CGD and the resonating frequency of LRES and CB is much lower than the resonating frequency of LRES and CGD. After the resonating frequency of LRES and CB, the series LRES and CB can be equivalent to an inductance L^’RES and its value is shown in (3.21). Therefore, the equivalent network between gate and drain can be express in Fig. 3.21. The impedance between gate and drain in Fig. 3.21 is given by (3.22). Thus

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if the inductance value must be chosen to satisfy the condition in (3.23), the parasitic capacitance can be resonated and the reverse isolation can be improved.

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Shown in Fig. 3.22 is the designed 2-stage cascaded current-mode PA that has been published by the present author [20]. The proposed PA consists of two cascaded current-mirror amplifiers to amplify the current signal.

By (3.9)–(3.10), the transistors’ dimensions and optimal load resistance can be roughly predicted by hand calculation. Two stages are adopted for the budget of PA’s output power and power gain. Because the biasing is fixed to VDD, the variable for transistor itself is size. The transistor’s size of output stage (2^nd-stage) is determined by the required output power. The size of driving stage (1^st-stage) is determined by the required power gain which amplifies mixer output signal to the level of input signal required by PA’s 2^nd-stage.

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Three on-chip inductors, L4–L6, are used to resonate out the parasitic capacitance of the drain (that is, node B1, B2, and B3). Because of large transistors and resultant seriously parasitic capacitance, two on-chip inductors, L7 and L8, are used to resonate out the gate-drain parasitic capacitance CGD,M8 and CGD,M10 of transistors M8 and M10, respectively.

The inductors L4 and L5, which are used for resonating parasitic capacitance of the internal nodes of power amplifier (B1 and B2), are determined and simulated with core circuit of power amplifier during the load-pull analysis. So if the performance of these resonated inductors is affected by the output impedance transformation network, which is determined by load-pull analysis, then these inductors have to be modified after the output impedance transformation network has been implemented. However, the chosen ZL and its corresponding transformation network are for previous circuit – core circuit of PA with non-modified inductors, load-pull analysis has to be simulated again for modified inductors. Because load-pull analysis has to be simulated again as long as any part of circuit is modified, iterative simulations may be needed to determine the values of resonated inductors and output impedance transformation network. For iterative procedure, it is endless if it is not convergent. From this point of view, the better way is to increase reverse isolation so that these resonated inductors need no any modification when the output impedance transformation network is connected to the circuit. That is the reason why both two inductors (L7 and L8) are used between gate-drain for both stages of PA.

Two capacitors, C4 and C5, are adopted to cut out unnecessary DC paths provided by L7 and L8. R3 is used for stability consideration. In fact, both M8 and M10 could form Colpitts oscillators. First stage is stable because node B2 is low-impedance node.

However, node B3 is high impedance at low frequency. Therefore, R3 is designed to

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decrease the loop gain of Colpitts oscillator. The sweep value of R3, shown in Fig. 3.23, shows the larger value of R3 can further degrade the loop gain and more stable. This figure also shows the node B3 is high impedance before it becomes negative resistance.

Considering the process variation, 5-ohm R3 is chosen. It is realized by 6-μm length, 2-μm width, 5-paralleled poly resistor and degrades power gain less than 1 dB. Its effect, in terms of k and b factor, is shown in Fig. 3.24–3.25.

The output impedance transformation network determined by load-pull analysis is composed of C6, L9, L10, and the parasitic capacitance of the output pad CPAD4.

In order to minimize chip area, internal nodes such as PA’s input (connected to mixer) and the node between PA’s 1^st and 2^nd stage are not implemented any matching networks. Instead, shunt inductors are adopted to resonate out the parasitic capacitance of these nodes. Because any parasitic capacitance is equivalent as a short path for high frequency, it may degrade RF signal by leakage RF signal to ground. The output node, however, is connected to external 50-ohm impedance probe during measurement.

Therefore, output transformation network is needed and implemented by load-pull analysis. Fig. 3.26 is the constant POUT, constant PAE contours and the chosen ZL by trade-off between them. Fig. 3.27 is the impedance transformation network, which transfers 50-ohm port to chosen ZL determined by the load-pull analysis. The transferred load impedance seen by power amplifier is shown in Fig. 3.28.