Experimental Results

Because the LO signal will increase the gate biases of M2 and M5. If mismatch occurs, the drain biases of these two transistors will be different. In this proposed current-operated self-switching mixer, mismatch will result in large ITH or small ITH

and degrade desired signal. In order to check the mismatch, the OPAMPs are turned off and the gates of M1 and M4 are biased through Bias-Tees at the beginning. The figure of different DC bias versus DC current is shown in Fig. 4.3. It is obvious that this circuit does not suffer from mismatch problem.

The measured results of the proposed transmitter front-end are given by Fig.

4.4–Fig. 4.10. The S-parameter of the transmitter front-end shows in Fig, 4.4–Fig. 4.6.

Near the IF, LO, and RF frequency, the S11 at 100 MHz, S22 at 23.9 GHz, and S33 at 24 GHz are –1.4 dB, –3.3 dB, and –6.3 dB, respectively. Because the center frequency drifts to 22 GHz in measured results, –2.6-dB S22 at 21.9 GHz and –15.8-dB S33 at 22 GHz has also been measured.

The measured results of sweep LO input power and input frequency are given in Fig. 4.7–Fig. 4.8 with –30-dBm, 100-MHz IF signal. The LO input power in measurement cannot larger than 15 dBm because of the equipment limitation, as shown in Fig. 4.7. By comparing with the simulation results, it is obvious that the

６５

required LO input power is increased from 4 dBm to 9 dBm. The center frequency of the transmitter is drifted from 24 GHz to near 22 GHz.

Under this conditions, the 1-tone and 2-tone test for linearity are shown in Fig.

4.9 and Fig. 4.10, respectively. In 1-tone test, the cable loss of 2.5 dB at IF port and 4.8 dB at both LO and RF ports are calibrated already. Besides, 9-dBm, 21.9-GHz LO and 100-MHz IF are adopted for input. The measured results for 1-tone test shows that the proposed transmitter front-end has 11.5-dB power gain, –20-dBm IP1dB, and –9.5-dBm OP1dB shown in Fig. 4.9.

For 2-tone test, the cable loss at LO and RF ports are the same as the 1-tone test.

However, because the two tones IF must be input to the transmitter, extra cables and off-chip components such as power combiner and adaptor must be used. Therefore, the total loss of IF input is increased to 9 dB. The LO input power is 9 dBm and LO input frequency is 21.9 GHz, the same as the condition in 1-tone test. The frequencies for IF are 75 MHz and 125 MHz. The measured results for 2-tone test illustrated in Fig. 4.10 shows the measured IIP3 is –5 dBm and OIP3 is 4 dBm. The summary and comparison table with other transmitter-related papers are given by Table 4.1.

4.4 Discussion

It is obvious that the measured results are quite different from the results shown in post simulation. From Table 4.1, it is clear that the degraded measurement results can not achieve the targets. The performance degradation can be categorized into three parts. One of them is the required LO input power becomes higher. Others are the degradation of the power gain and the drift of the center frequency. After re-checking

６６

the circuit and design procedure, few mistakes are found. The detailed explanation will be introduced as follows.

The Increment of the Required LO Input Power

The Smith charts given by original post-simulation and by measurement are given by Fig. 4.11. It is clear that the Smith chart given by post-simulation is matched to near 50 ohm. However, the measured result shows that the LO input matching is located on the 50-ohm circle at the desired frequency but lacks for series capacitance. After re-check the layout of the designing transmitter, a mistake of missing capacitor has been found. This mistake comes from doing the LVS process. Because the on-chip transformer at the LO input port is re-drawn and cannot be found in the symbol provided by the TSMC, the transformer must be removed or disconnected during the LVS process. That is, this transformer and the following series capacitor were floated at that time. Nevertheless, the mistake occurred because that only the transformer had been replaced but not the following capacitor after the LVS process. The original placement of the series capacitor in schematic and layout and the difference between the LO input match with and without this capacitor are shown in Fig. 4.11. This mistake will increase the reflection at the LO input. In order to obtain the same level of LO input power in core circuit, the signal generator must be provided larger power than simulation at the LO input PAD. That is the reason why LO input power required during the measurement is much higher than that in post-simulation.

The Degradation of the Power Gain and the Frequency Drift

In general, the frequency drift comes from the parasitic effect. Because the parasitic effect had been considered for long metal line as shown in Fig. 3.30–Fig. 3.32, it is possible to underestimate the parasitic effect of other nodes. Therefore, the revised

６７

post-simulation has been done by considering full chip EM effect and simulated by HFSS. The layout view and 3-D model in HFSS are shown in Fig. 4.12. Besides, the DC current in measurement is much lower than original one. Because this phenomenon is usually caused by higher temperature or worse corner, an infrared thermometer is used for temperature measurement. The result in Fig. 4.13 shows that the chip temperature is about 72^oC. According to the parameters reported by CIC, on the other hand, the circuit characteristic is SS corner. Therefore, the DC currents for different temperature and SS corner are simulated and given by Table 4.2. It is obvious that the measured DC current matches to the DC current under the conditions of SS, 75^oC. Thus the revised post simulation is done by setting the simulation conditions of SS, 75°C, layout mistake, and replacing each SNP file produced by EM simulation in HFSS.

Revised Post-Simulation Results

The revised simulation results, comparing with the original post-simulation results and measurement results, are shown in Fig. 4.14–Fig. 4.20. The comparison of S11, S22, and S33 are given by Fig. 4.14–Fig. 4.16. The S-parameter of revised post-simulation is similar to the measured one. The sweep LO input power and input frequency are shown in Fig. 4.17–Fig. 4.18. The required LO input power increases to 9 dBm and the center frequency drifts to 22 GHz, the same with the measured results.

Comparing to the original post-simulation, it is obvious that the 1-tone and 2-tone test shown in Fig. 4.19–Fig. 4.20 of revised post-simulation results close to the measured results. The summary and comparison table are given by Table 4.3. According to the revised post-sim results, the required LO input power is the same as measured LO input power. Besides, the center frequency in revised post-sim results is also the same

６８

as the center frequency in measurement. Although the gain of revised circuit is also degraded, it still has 4-dB difference from measured gain.

4.5 Re-Design

Because several factors such as the parasitic effect simulated by Fig. 3.30–Fig.

3.32, corner, and temperature are underestimated, the performance is quite degraded in measurement and revised post-sim results. Therefore, the purpose of the re-design circuits is to match the original targets but under the revised conditions.

Under the worse conditions, the DC current, transistor’s gm, linearity, and power gain are degraded. Therefore, not only the passive components, the dimensions of active components have to be modified to improve the performance. The components which have modified their dimensions are shown by red color in Fig. 4.21, the summary of these dimensions are given by Table 4.4.

The performance of the re-design version, including the detailed EM simulation of modified layout in Fig. 4.22, SS or TT corner, and 75^oC temperature, are simulated.

The results of re-design version, comparing with original targets and revised post-sim results, are shown in Fig. 4.23–Fig. 4.36.

The S-parameter shown in Fig. 4.23–Fig. 4.25 express the S-parameter of re-design is similar to original one except S33. S33 comes from the output of the power amplifier and determines by the load-pull analysis. Because the sizes of the transistors in 2-stage PA have been rearrange, the optimized load impedance determined by load-pull is different from original one. It is obvious that the required LO input power and frequency in Fig. 4.26–Fig. 4.27 are equal to the original design.

６９

The 1-tone and 2-tone tests, given by Fig. 4.28–Fig. 4.29, show that the power gain and the linearity of the re-design are almost the same as the original.

The performances under the TT corner, 75^oC temperature also have been simulated and expressed by Fig. 4.30–Fig. 4.36. Because the DC currents are larger than the DC current in SS corner, the results are almost the same with the SS corner except the power gain and saturated output power. The performances for all corners are shown in Fig. 4.37–Fig. 4.43.

The summary and the comparisons are given in Table 4.5 and Table 4.6.

Comparing to other voltage-mode power amplifier in Table 4.5, it shows the proposed current-mode power amplifier has better OP1dB and OIP3 under lower supply voltage.

Comparing to other voltage-mode transmitter circuits in Table 4.6, the proposed transmitter front-end circuit has lower supply voltage. Although the total power consumption is larger than other works, this proposed transmitter front-end can deliver 16.8-dBm output power, which is quite larger than others. Under the same output power level, therefore, this proposed current-mode transmitter can have lower power consumption than voltage-mode transmitter circuits.

From the original design, the VREF is chosen for maximizing conversion gain. For transmitter front-end circuits, however, the signal comes from base station and can be large. Thus the mixers’ conversion gain in transmitter is not necessary to be very large.

On the other hand, however, the linearity requirement is strict. From Fig. 4.44 and Table 4.7, it is obvious that the 0.6-V VREF can obtain maximized conversion gain and the 0.4-V VREF can have best OP1dB. Therefore, the 0.4-V VREF should be chosen for designing up-conversion mixer in the future.

７０

The 1-tone test by different LO input power of proposed transmitter front-end is shown in Fig. 4.45. For small IF level, 4-dBm LO input power has maximal conversion gain. It is also the original design consideration. For large IF level, however, 6-dBm or even 8-dBm can deliver higher output power. Considering the real case in transmitter front-end, the large IF signal should be adopted and resultant large LO input power should be chosen in the future.

７１

Table 4.1 Summary of measurement results

Post-Sim (Original) Measurement Targets Technology 0.13-μm CMOS -

７２

Table 4.2 DC consumption for different corners and temperatures

IVDD (mA) IVDPA1 (mA) IVDPA2 (mA) IVDPA3 (mA) TT, 25^oC 15.26 1.04 58.1 201 SS, 25^oC 5.72 0.616 48.9 169 SS, 50^oC 5.58 0.605 47.4 164 SS, 75^oC 5.42 0.6 46 159 SS, 100^oC 5.22 0.599 44.6 154 Measurement 5.3 0.84 45 147

７３

Table 4.3 Summary of revised post-sim results

Post-Sim

(Original) Measurement Post-Sim

(Revised) Targets

IF (GHz) 0.1 0.1 0.1 0.1

LO (GHz) 23.9 21.9 21.9 23.9

RF (GHz) 24 22 22 24

Power (mW)

Mixer 18.8 7.3 6.9 -

Power Amplifier 311.7 231.1 246.6 -

Total 330.5 238.4 253.5 -

TX Front-End

S11 / S22 / S33 (dB) –8.9 / –16.4 / –9.5 –1.4 / –2.6 / –15.8 –13.2 / –2.3 / –5.4 - Gain (dB) 25.2 11.5 15.5 >20 OP1dB / IP1dB (dBm) 9.1 / –15 –9.5 / –20 –0.5 / –15 -

POIP3 / PIIP3 (dBm) 20 / –5 4 / –5 9 / –5 - Max. POUT (dBm) 14.4 –2.5 7.1 >10

７４

Table 4.4 Dimensions summary of the re-design version

Dimension (μm) M1 2.5*28/0.13 Æ 2.5*40/0.13 M2 2.5*12/0.13 Æ 2.4*14/0.13 M8 2.5*20*2/0.13 Æ 2.5*20*3/0.13 MOP,P1–2 2*2/0.13 Æ 1.5*2/0.13

Value

L34 215 pH Æ 69 pH L5 215 pH Æ 67 pH L7 1.24 nH Æ 563 pH L9 104 pH Æ 128 pH

Value

C3 88 fF Æ 79 fF

C6 431 fF Æ 399 fF

７５

Table 4.5 Comparison with voltage-mode power amplifier

Post-Sim (Revised) Post-Sim (Re-Design) [6]JSSC 2005 Technoogy 0.13-μm CMOS 0.18-μm CMOS

Methodology Current-Mode Voltage-Mode