When the switches of dc-dc converter are implemented by using current-unidirectional semiconductor, there would be discontinuous conduction mode (DCM) introduced. The discontinuous conduction mode arises when the switching ripple of inductor current is large enough to cause the polarity of the applied switching current to reverse, such that the reversed current occurred. The DCM is commonly observed in dc-dc converters and rectifiers.
Discontinuous conduction mode typically occurs with large inductor current ripple at light loading and contains current-unidirectional switches. Since it is usually required that converters operate with their loads removed, DCM is frequently encountered. Moreover, some converters are purposely designed to operate in DCM mode for all loads.
A simple asynchronous buck converter shows in Fig. 15. The inductor current waveform
I
L, diode current waveformI
D and the power MOS currentQ1
I
of switching regulators are sketched in Fig. 16. The inductor current contains a dc component IL(avg) with an amplitude of switching ripplei
L.Fig. 15. The asynchronous buck converter
When the load resistance RL is increased, the dc load current IL(avg) also decreased. As the dc component of inductor current IL(avg) decreased, the ripple magnitude will still remain unchanged. If we continue to increase RL, eventually the boundary is reached
2 ⋅ ∆ i
LFig. 16. The current waveform of inductor, diode and power MOS(IQ1)
( ) o
Fig. 17. Inductor current are CCM operation at heavy and medium loads
where
I
L avg( )= i
L, illustrated in Fig. 17. It can be seen that the inductor currentI
L and diode remainder of the switching period neither the transistor nor the diode conduct. The converter operates in discontinuous conduction mode.Fig. 18. Inductor current are CCM and DCM operation at heavy and light loads
Formulation (31) suggests a way to fine the boundary between the continuous and discontinuous conduction modes. It can be seen that, for buck converter, the diode current is positive over the entire interval
DT
s < <t T
s provided thatI
L avg( )> i
L. Hence, the conditions for operation in the continuous and discontinuous conduction modes are:Where IL(avg) and
i
L are found assuming that the converter operates in continuousconduction mode. Insertion of Eqs (29) and (30) into Eq. (31) yields the following condition for operation in discontinuous conduction mode:
Simplification leads to:
This can also be expressed in:
The dimensionless parameter K is a tendency measure of a converter to operate in discontinuous conduction mode. Large values of K lead to continuous mode operation, while small values lead to the discontinuous mode for different parameters. The critical value
crit( )
K D
is a function of duty cycle, and equals toD
' for the buck converter.The critical value
K
crit( )D
versus duty cycle is plotted in Fig. 19. For the figure shown, it can be seen that the converter operated in DCM at low duty cycle, and CCM at high duty cycle. The Fig. 20 shows the switching converter in CCM mode with heavier loads. Namely, the load resistance RL is reduced, such that K is larger. If K is greater than one, then the converter operates in continuous conduction mode for all duty cycles.'
Fig. 19. Operation boundary of CCM and DCM modes
It’s simple to express the mode boundary in terms of the load resistance RL, rather than
Fig. 20. Switch converter operates in CCM mode for all duty
The conclusion can be formulated as below:
A similar mode boundary analysis can be performed for other converters. The boost and buck-boost converters are analyzed in the same manner. The results are listed in Table 3, for basic dc-dc converters.
Table 3 CCM-DCM mode boundaries for buck, boost, and buck-boost converters Converter
K
crit( )D
Chapter 3
Derivation and Circuit Implementation of High-Efficiency Slope Compensation Technique
So far, we know that the current programmable controlled converter requires the slope compensation technique to eliminate the sub-harmonic oscillation phenomenon. Hence, the use of artificial ramp adding to the sensed inductor current is a useful and popular method in control circuits. As shown in Fig. 21, the Current-Sensor circuit connects to the Vx node that located between High-side PMOS and Low-side NMOS and introduces Vsense signal. The Slope
Compensator circuit introduces V
slope_comp signal periodically. The both signals Vsense andV
slope_comp go through the voltage-to-current (V-I) circuits to introduce Isense and Islope_compFig. 21. Slope compensation diagram of current mode buck converter
signal, respectively. The both signals Isense and Islope_comp flow into the resistor Rsum and generate the Vsum signal. The signal Vsum will define the duty cycle of switching converter.
This paper introduced the operation modes with pulse width modulation (PWM) and pulse frequency modulation (PFM) in heavy load and light load condition, respectively [19][20].
However, there is a significant problem that how to decide the suitable transition time from PWM to PFM mode. Therefore, in conventional mode-transition method, shown in Fig. 22, there is a Mode Detector & PFM Controller circuit that consists of Zero-Current Detector,
ZCD Counter, Mode Selector and PFM Controller.
When the converter operates in light loading and the inductor current ripple is larger than the average load current, it’s occurred reversal flowing. The Vx voltage touched the zero voltage to generate the one-shot signal (ZCD signal) in the output of Zero-Current Detector.
The ZCD signal accessed into the ZCD Counter to identify, whether the converter changes into PFM mode or not. Then, the signal accesses into Mode Selector circuit to decide the operation mode and able or disable the PFM Controller immediately.
Unfortunately, the VX signal has poor noise immunity and is easy to be coupled by turning on/off of power MOSFETs. Especially, this scenario is deteriorated in high switching
∑
Fig. 22. Conventional mode-transition detection architecture
randomly transits between PWM and PFM modes. Therefore, this paper presents a method using the output voltage (VC) of error amplifier as a detection signal rather than the VX voltage in Fig. 23. The output voltage of error amplifier can be input independent parameter by means of the proposed HSC controller. The signal VC only depends on load current condition. Thus, the new detection signal VC with robust immunity to noise contains load current information to identify the operation mode immediately without using the Zero-Current Detector. Thus, in the following descriptions, we will introduce the control issues of proposed high-efficiency slope compensation circuit and circuit implementations.
3.1 Concern Issues of Proposed Slope Compensation Technique
High-efficiency slope compensation technique, shown in Fig. 24, as the supply voltage (VIN) changes from high to low, the duty cycle (D) changes from low to high. Thus, the output voltage (VC) of error amplifier will raise a voltage difference (∆V). If we use the VC voltage as
∑
Fig. 23. Conventional mode-transition detection architecture
a detection signal to identify the operation mode, the voltage difference (∆V) makes the load current identification with wrong state. Figure shows that the duty cycle increases as the supply voltage decreases, the raising voltage difference (the red dash line) touches the boundary of operation mode (VPFM_S) and turns on the PFM mode operation. For example, 200mA of load current is the boundary of mode transition. Due to the voltage difference rising, the load current drops to 150mA to change mode. It implies that the PFM mode is delay to turn on. Oppositely, the duty cycle decreases as the supply voltage increases, the falling voltage difference (the blue dash line) touches the boundary of operation mode (VPFM_S) and turns on the PFM mode operation. It implies that the PFM mode is early to turn on. Owing to the supply voltage variation, the output voltage (VC) of error amplifier would be disturbed by a voltage difference (∆V). Therefore, the next section will introduce the proposed high-efficiency slope compensator to overcome the above problems.
Moreover, the simple architecture of current mode buck converter is shown in Fig. 25.
The sensed voltage from current sensing circuit and the compensated ramp from sawtooth generator flow into the V-I Pair circuit and introduce the summation signal Vsum. The Vsum signal and the Vc signal, which comes from error amplifier; connect to the comparator CMP to generate the Reset signal. The both signal CLK and Reset feed through the Pulse-Generator circuit to define the PWM duty cycle of switching period. When the Vsum signal varied with
Fig. 24. Duty cycle variation due to supply voltage variation and mode transition diagram
duty cycle, the Vc signal will also follow the Vsum signal to define equivalent duty width as the same previous switching period because of duty cycle is only dependent on Vin and Vout voltages.
According to theory of the Vc signal varies with the Vsum signal, we can use the Vsum signal to control the Vc signal on our way. As the Vc signal is changed by output load current variation only, it had current information of heavy or light loadings. Thus, we can use the Vc signal to identify, what is the suitable opportunity for changing the operation mode. Hence, we have to design the Vsum signal independently with supply voltage and dependents on load current variations. Therefore, the Vsum signal is controlled by the load current variation specifically. We used the Vc signal to decide the suitable transition time from pulse width modulation (PWM) into pulse frequency modulation (PFM) mode.
Driver
Fig. 25. Simple architecture of current mode buck controller in different loads