具高效能斜率補償器及與輸入電源無關之負載電流識別機制的電流模式直流/直流降壓電源轉換器

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電機與控制工程學系

具高效能斜率補償器及與輸入電源無關之負載電流

識別機制的電流模式直流/直流降壓電源轉換器

High-Efficiency Slope Compensator (HSC) with

Input-Independent Load Condition Identification in

Current Mode DC-DC Buck Converters

研究生:賴 韋 任

指導教授:陳 科 宏 博士

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具高效能斜率補償器及與輸入電源無關之負載電流識別機制的電

流模式直流/直流降壓電源轉換器

High-Efficiency Slope Compensator (HSC) with Input-Independent

Load Condition Identification in Current Mode DC-DC Buck

Converts

研 究 生:賴韋任 Student:Wei-Jen Lai

指導教授:陳科宏 Advisor:Ke-Horng Chen

國 立 交 通 大 學

電 機 控 制 工 程 學 系

碩 士 論 文

A Thesis

Submitted to Department of Electrical and Control Engineering

College of Electrical Engineering

National Chiao Tung University

in partial Fulfillment of the Requirements

for the Degree of

Master

in

Electrical and Control Engineering

October 2008

Hsinchu, Taiwan, Republic of China

中華民國九十七年十月

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具高效能斜率補償器及與輸入電源無關之負載電流識別機制的電

流模式直流/直流降壓電源轉換器

研究生:賴韋任

指導教授:陳科宏博士

國立交通大學電機與控制工程研究所碩士班

在消費性電子產品中,尤以手持式產品的應用上,需求越來越廣泛。擁有高效能與 小型化的電源轉換器日趨重要。為了有效使用有限的電池能量,電源管理系統為非常重 要的元件。故本文提出一個切換式穩壓器在斜率補償上的應用單元,以期在模式切換時 有最好的效能表現。 論文中,降壓式轉換器適當的操作於脈波寬度調變模式(PWM)以及脈波頻率調變模 式(PFM),分別應用於重電流負載及輕電流負載。然而在電流控制模式下,當工作周期 大於二分之一的全周期時,會發生所謂的次諧波震盪導致系統不穩定。所以在傳統控制 中,加入補償斜率來克服次諧波震盪。然而此一傳統斜率補償電路會造成誤差放大器的 輸出電壓(VC)隨供應電源(VIN)而改變,產生控制上的困擾。 利用本文所提出的高效能斜率補償器(HSC),可達到誤差放大器的輸出電壓(VC)與 供應電源(VIN)互為獨利因子,僅與負載電流成正相關。此外為防止電源轉換器有逆向電 流的產生,本文使用零電流偵測器(ZCD)來偵測逆向電流的發生,以提高系統效能表現。 所以在傳統控制上,是偵測逆向電流保護電路的輸出訊號來判定切入脈波頻率調變模式 的時機。然而傳統零電流偵測器的輸入訊號對抗雜訊能力較差,無法操作於高頻切換電 路。所以本文利用已提出的誤差放大器的輸出電壓(VC)當成切換依據,達到克服雜訊以 及負載電流識別機制的功能。 本論文所提出的內容,非以逆向電流保護電路的輸出訊號當作判別依據,是以誤差 訊號放大器的輸出端訊號(VC)來判斷。藉由誤差訊號放大器的輸出電壓(VC)隨負載電流 變化而不隨供應電源改變的特性,來達到高效率的模式轉換。 本論文根據不同負載情況適當地切換這於此兩種模式間,整體系統效率可維持百分 之八十以上。本電路架構以世界先進股份有限公司點三五微米製程來實現,其模擬結果 與效能值亦包含在文中。

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High-Efficiency Slope Compensator (HSC) with Input Independent Load

Current Identification in Current Mode DC-DC Buck Converters

Student: Wei-Jen Lai Advisor: Dr. Ke-Horng Chen

Department of Electrical and Control Engineering

National Chiao-Tung University

ABSTRACT

Today’s portable and battery powered products such as cellular phones, personal digital assistant (PDA), tablet PC, etc are increasingly demanded more and more. The system’s operation time is an important issue to enhance the worth of electronic devices. Therefore, the power management systems provide solutions to overcome the above problems.

In switching converters especially in current mode systems, there is a slope compensation circuit to prevent the occurrence of sub-harmonic oscillation that caused the system unstable. Designers proposed a sawtooth ramp adding to the sensed inductor current to eliminate the sub-harmonic oscillation. But conventional sawtooth ramp makes the output voltage of error amplifier (VC) unpredictable as the supply voltage changes.

A high-efficiency slope compensator (HSC) is presented to achieve power reduction in current-mode control and provide input-independent load condition identification for mode switch in hybrid PWM/PFM system. That is, according to load condition, an adaptive mode transition can be decided by the HSC circuit and not varied by the variation of input voltage. Therefore, for a hybrid PWM/PFM system, the power conversion efficiency can be kept high over a wide load range. Besides, the pulse-ramp generator prevents the current-mode DC-DC converter from having the sub-harmonic oscillation problem and reduces power dissipation of the slope compensator. Simulation results show that the mode transition is accurately decided at the optimum point without being affected by the variation of input voltage. The power conversion efficiency is improved about 5% in PWM/PFM transition region.

The proposed technique is based on current-mode dc-dc buck controller. The circuit implementation is fabricated by VIS 0.35-

µ

m CMOS technology and the overall efficiency is larger than 80% at all load conditions.

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在兩年的學習路上,受過非常多朋友的幫助,致使本論文能如期完成。

首先誠摯的感謝指導教授-陳科宏老師,在就學期間給予無私的指導及教

誨。無論是在課業上的疑惑,或是生活經驗上的傳承,皆給予學生極大的

啟發。對學問執著與嚴謹的態度,更是學生效法的對象。

感謝實驗室的夥伴們,在研習的過程中相互勉勵與扶持。及堅強的博

士班陣容,宏瑋學長、紹章學長、心欣學姊、小契學長、銘信學長、俊禹

同學,給予學業上及生活上的諮詢。感謝逢哥、國林、小柯,在電路佈局

上熱忱的指導,於一個對電路佈局一知半解的我來說,受益良多。

感謝同儕家祥、佳麟、維倫、鼎容、勇志。大家在一起修課、討論,

相互切磋及勉勵、成長及鼓勵。感謝畢業學長姐,德賢學長、奐箴學長、

詠竣學長、立家學長、琨瑋學長、宗龍學長、永欣學姐、玓玓學姊、玉惠

學姊平時的照顧。感謝 802 實驗室所有夥伴以 701、703 實驗室的學弟們。

亦感謝專案合作的台達電子工程師,在討論中不吝提問及指教,使我進步

良多。

最後想感謝我的父、母親及家人,因為有你們在生活上、經濟上的幫

助,使能無後顧之憂的專注於學業,順利取得畢業證書。謹以此文獻給關

心我、愛我及我愛的家人、朋友們。因為有你們的參與使本文增色不少,

謝謝你們。

韋任 于 拾月 秋 國立交通大學 中華民國九十七年十月

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Contents

Chapter 1 ...1

Introduction ...1

1.1 Background of Regulators ...1

1.2 Classification of Power Supply Circuit ...2

1.2.1 Linear Regulators ...2

1.2.2 Switching Capacitor Circuits...3

1.2.3 Switching Regulators...4

1.3 Thesis Organization ...8

Chapter 2 ...9

Definition and Operation Principle of Current Mode Buck Converters...9

2.1 General Specifications...9

2.1.1 Load Regulation ...10

2.1.2 Line Regulation ...10

2.1.3 Transient Response ...10

2.1.4 Losses and Efficiency...13

2.1.4.1. Conduction Loss ...13

2.1.4.2. Switching Loss ...13

2.1.4.3. Static Loss...15

2.1.4.4. Efficiency...15

2.2 DC Model for Current Mode Buck Converter in CCM Analysis...16

2.3 DC Model for Current Mode Buck Converter in DCM Analysis...23

Chapter 3 ...28

Derivation and Circuit Implementation of High-Efficiency Slope Compensation Technique.28 3.1 Concern Issues of Proposed Slope Compensation Technique ...30

3.2 Design Theorem of Proposed Slope Compensation Technique ...33

3.3 Circuit Implementation of Proposed Slope Compensation ...47

3.3.1 Pulse-Signal Generator ...47

3.3.2 Pulse-Ramp Generator...48

Chapter 4 ...50

Circuit Implementations and Simulations ...50

4.1 DC/DC Buck Converter with PWM/PFM Mode ...50

4.2 Current Mode Buck Converter with PWM Mode ...51

4.2.1 Bandgap Reference...53

4.2.2 Comparator ...55

4.2.3 Operational Amplifier...56

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4.2.6 Current Sensing Circuit ...61

4.2.7 Clock and Sawtooth Generator...63

4.2.8 Percent Duty and Quadratic Ramp Generator ...65

4.2.9 Voltage Adder ...66

4.2.10 Zero Current Detector...67

4.2.11 Pulse-Width Generator ...69

4.2.12 Non-overlapping Circuit...70

4.3 Current Mode Buck Converter with PFM Mode...71

4.3.1 Architecture of PFM Mode Controller ...71

4.3.2 Current Fitting Curve Generator...72

Chapter 5 ...74

Simulation Results and Conclusions ...74

5.1 Simulations of Monolithic Buck Converter in PWM Mode...74

5.1.1 Simulation Results of Input Voltage Variations...75

5.1.2 Simulation Results of Load Transient Response ...77

5.2 Simulations of Monolithic Buck Converter in PFM Mode ...79

5.3 PMW/PFM Mode Transition ...81

5.4 System Efficiency...83

5.4.1 Adaptive Mode-Transition Control ...84

5.5 Conclusions ...86

5.5.1 Whole Chip Layout Diagram ...86

5.6 Future Works ...88

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Figure Captions

Fig. 1. The block diagrams of personal digital assistant (PDA) with power management ICs..2

Fig. 2. The schematic of a low drop-out linear regulator ...3

Fig. 3. The schematic of a close loop switching capacitor voltage doubler ...4

Fig. 4. The simple architecture of buck converter...5

Fig. 5. The periodic waveform in Fourier analysis...5

Fig. 6 System diagram of buck converter with dynamic load response ... 11

Fig. 7. Transient waveform of output voltage at load current variation...12

Fig. 8. Transient waveform of VDS and ID curve in switching losses on power MOSFET...14

Fig. 9. The block diagram of current mode buck converter ...17

Fig. 10. Inductor current at stable and unstable oscillation in current-mode converter ...17

Fig. 11. The perturbation waveform of inductor current ...18

Fig. 12. Current-mode control signal with the compensation ramp and inductor current...20

Fig. 13. Steady-state and perturbed inductor current waveforms with compensation ...20

Fig. 14. Inductor current with compensation ramp for few periods ...22

Fig. 15. The asynchronous buck converter...23

Fig. 16. The current waveform of inductor, diode and power MOS(IQ1) ...24

Fig. 17. Inductor current are CCM operation at heavy and medium loads ...24

Fig. 18. Inductor current are CCM and DCM operation at heavy and light loads ...25

Fig. 19. Operation boundary of CCM and DCM modes ...26

Fig. 20. Switch converter operates in CCM mode for all duty...27

Fig. 21. Slope compensation diagram of current mode buck converter ...28

Fig. 22. Conventional mode-transition detection architecture ...29

Fig. 23. Conventional mode-transition detection architecture ...30

Fig. 24. Duty cycle variation due to supply voltage variation and mode transition diagram...31

Fig. 25. Simple architecture of current mode buck controller in different loads ...32

Fig. 26. The slope compensation diagram of current mode buck converter ...33

Fig. 27. Inductor current in DC and AC analysis ...34

Fig. 28. Current sensing circuit ...36

Fig. 29. Sawtooth waveform with clock pulse ...37

Fig. 30. The microcosmic waveform of sawtooth ramp...37

Fig. 31. Duty cycle with percent duty control ...38

Fig. 32. The simple diagram of the slope controller...39

Fig. 33. The Iramp current is charging only with 10% pulse...40

Fig. 34. The Vslope_comp function is a linear equation with respect to duty cycle...41

Fig. 35. The schematic of voltage adder...42

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Fig. 38. The combination voltage of both signal Vsense and Vslope_comp...44

Fig. 39. Matlab diagram of Vsense, Vslope_comp and Vsum signals ...45

Fig. 40. Slope compensation values in reasonable range ...46

Fig. 41. Percent duty pulse generator ...47

Fig. 42. Timing diagram of percent duty generator...48

Fig. 43. Quadratic ramp generator controlled by VS pulse ...49

Fig. 44. The Iramp current is charging into the capacitor with 10% duty ...49

Fig. 45. The architecture of current mode buck converter with PWM controller ...51

Fig. 46. The principle of bandgap reference...53

Fig. 47. The conceptual block diagram of bandgap voltage reference...54

Fig. 48. The simulation waveforms of the bandgap reference with temperature variation...55

Fig. 49. The schematic of comparator without hysteresis window ...56

Fig. 50. The schematic of folded-cascode operational amplifier with PMOS input ...56

Fig. 51. The architecture of the loop gain analysis...57

Fig. 52. Stability simulation result of the close loop analysis ...57

Fig. 53. The schematic of the folded-cascode transconductance operational amplifier...58

Fig. 54. Frequency analysis of the error amplifier ...59

Fig. 55. Frequency response of the current mode buck converter...59

Fig. 56. The scheme of the compensation network ...60

Fig. 57. Frequency domain analysis of compensation network ...61

Fig. 58. The schematic of the integrated sensing circuit with power stage ...62

Fig. 59. Simulation for the current sensing circuit ...63

Fig. 60. Clock and sawtooth generator ...64

Fig. 61. The simulation result of the clock and sawtooth generator...65

Fig. 62. The schematic of percent duty and quadratic ramp generator...65

Fig. 63. The simulation waveforms of quadratic ramp and 10% control pulse...66

Fig. 64. The schematic of the voltage adder...67

Fig. 65. The simulation waveforms of the voltage adder ...67

Fig. 66. The schematic of the zero-current detector ...68

Fig. 67. Simulation waveforms of the zero current detector ...69

Fig. 68. The schematic of the pulse-width generator ...69

Fig. 69. The schematic of the non-overlapping circuit...70

Fig. 70. Simulation waveform of the non-overlapping circuit ...71

Fig. 71. The architecture of current mode buck converter with PFM controller...71

Fig. 72. The schematic of the current fitting curve generator ...73

Fig. 73. The simulation waveform of adaptive voltage selection generator...73

Fig. 74. Simulation waveform of inductor current and Vc signal in supply voltage variation 75 Fig. 75. Simulation waveforms of Vsense, Vslope_comp and Vsum in supply voltage variation ...76

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Fig. 77. Simulation waveforms of output voltage and inductor current ripple ...77

Fig. 78. Whole chip PWM mode simulation: Load transient response (VIN=3.3V) ...77

Fig. 79. Load transient response in PWM mode (falling step)...78

Fig. 80. Load transient response in PWM mode (rising step) ...78

Fig. 81. The simulation waveforms in PFM mode ...80

Fig. 82. Full chip simulation: Transition from PWM to PFM mode (falling step load) ...82

Fig. 83. Full chip simulation: Transition from PFM to PWM mode (rising step load)...82

Fig. 84. System efficiency with different supply voltage in PFM mode ...83

Fig. 85. The relationships of supply voltage, loading current and PFM_S voltage ...84

Fig. 86. Current fitting diagram of PFM_S voltage and loading current ...85

Fig. 87. The schematic of the adaptive mode-transition controller ...85

Fig. 88. Efficiency improvement in mode transition region with HSC controller ...86

Fig. 89. Whole chip layout diagram of proposed slope compensation circuit ...87

Fig. 90. Core circuit layout diagram of proposed slope compensation circuit ...87

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Table Caption

Table 1. Three architecture of switching regulators ...6

Table 2. Comparative table of power supply circuits. ...7

Table 3 CCM-DCM mode boundaries for buck, boost, and buck-boost converters ...27

Table 4. The electrical characteristics...52

Table 5. The simulation results of the bandgap voltage reference circuit. ...55

Table 6. The compensation parameters of the compensated network. ...60

Table 7. The parameters of load transient response in PWM mode ...79

Table 8. The characteristics of different loading in PFM mode ...80

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Chapter 1

Introduction

1.1

Background of Regulators

Today’s portable and battery powered products such as cellular phones, personal digital assistants (PDA), tablet PC, etc are increasingly demanded more and more. System’s operation time is a factor to enhance the worth of the electronic devices in consumer’s market. The longer operation time had higher attraction and the best competitiveness but it had many limitations and difficulties to increase the capacity of stored energy device liked as battery equipments. As a result, how to extend the system operation time is a critical issue that engineers mostly concerned. Moreover, for specific electronic system, there are different supply voltages to make required performance liked VRM techniques. Therefore, power management system provides solutions to overcome the above confusions.

Power management ICs with high conversion efficiency are used to these applications for maximizing the operation time of the portable devices. Furthermore, it is essential for the designers to decrease the size and weight of the power module for the products. In order to accomplish low-cost, high-efficiency and high performance, there are many different kinds of power management architectures could be used. Those power management systems, such as boost converter, buck converter, charge pump, and low drop-out (LDO) linear regulator, operates with step-down, step-up or inverting voltage. For example, the block diagram of personal digital assistant system is shown in Fig. 1. The core system includes processor/memory, user interface and power management ICs.

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1.2

Classification of Power Supply Circuit

Power management circuits can classify into three different techniques as function works: linear regulators, switching capacitor circuits (charge pumps), and switching regulators. After the following subsections, these techniques are briefly introduced and described.

1.2.1

Linear Regulators

The linear regulator generally used in low load current condition. It had simple architecture and no switching ripple with respect to the other types of power management IC’s [1]-[4]. The LDO also requires smaller layout area, footprints and low drop-out voltage to provide high performance and high efficiency.

The linear regulator used a pass device between the input supply voltage and the Fig. 1. The block diagrams of personal digital assistant (PDA) with power management ICs

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regulated output voltage. An error amplifier controls the gate voltage of the pass transistor with respect to a reference voltage. These devices are constructed in a negative feedback configuration to maintain the output voltage irrespective of load current and input voltage variations. As illustrated in Fig. 2. It shows the schematic of a linear regulator that operates linearly to maintain the output voltage according to the reference voltage.

1.2.2

Switching Capacitor Circuits

The switching capacitor circuits, also called as charge pumps, that is usually used to obtain a dc voltage higher or inverting than the supply voltage in low load current applications [5]-[8]. The charge pump circuit uses capacitors as energy storage devices and MOSFET as switches. The control circuit is switched in complementary or differential phases such that the required multiple output voltage were maintained.

Fig. 3 illustrated a closed loop switching capacitor voltage doubler circuit. The voltage control oscillator receives the signal from Error amplifier and generates the oscillation frequency that corresponds to difference voltage between feedback node via the divided resistors and the Vref voltage. The switching phase Φ1 is closed during the first interval of

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switching period, connecting to the fly capacitor Cf between the input voltage VINand ground.

In this period, the energy is stored by the fly capacitor Cf and the voltage across the fly

capacitor equals Vin.

During the second interval of switching period, the switching phase Φ2 turned on and the fly capacitor has been connected between Vin and Vo. The output voltage equals twice of

Vin because of the voltage across fly capacitor is Vin. In order to maintain the output voltage,

there are many ways to modulate the voltage of switching capacitor circuits such as Dickson, Makowski, TPVD and MPVD charge pumps.

The switching capacitor circuits are useful in many different applications such as low-voltage circuits, dynamic random access memory circuits, electrically erasable programmable read-only memory (EEPROM), transceivers and so on.

1.2.3

Switching Regulators

Switching regulators are widely used in power supply systems because it has many excellent advantages such as high power efficiency, high conversion ratio and programmable [9]-[12]. As showed in Fig. 4. The simple architecture of buck converter with two switches that one (S1) is connected between input node and power stage, the other one (S2) is connected

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between ground and power stage. The power stage is like as low pass filter.

The regulators transfer energy to output node in periodic pulse waveform by turning on/off the semiconductor switches S1 and S2, alternately.

The pulse signal often formed as Fig. 5. When the S1 is closed, the Vs(t) equals the input

voltage Vin. Alternately, when the S2 is closed, the Vs(t) equals the ground voltage - zero. The

periodic pulse waveform is connected with a low pass filter that consisted with an inductor and a capacitor. Recall from Fourier analysis that the dc component of a periodic waveform is equal to its average value. Hence, the dc value of Vs(t) is

0

1

( )

s T s s in s

V

V t dt

DV

T

=

=

(1)

Fig. 4. The simple architecture of buck converter

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Therefore, the switching regulators can classify into three topologies as functional works. Listed in Table 1, are buck, boost and flyback converters.

The first regulator called as buck converter because its property that step down the input voltage with respect to output node. The conversion ration M(D) is written as M D( )=D. The second regulator called as boost converter because its property that step up the input voltage with respect to output node. The conversion ration M(D) is written as ( ) 1

1

M D

D

=

− . The last regulator called as flyback converter also named buck-boost converter because its property that step up or down the input voltage with respect to output node. The conversion ratio M(D) is written as ( ) 1 D M D D − = − .

Table 1. Three architecture of switching regulators

Architecture Conversion Curve

Buck ( ) M D =D ( ) M D Boost 1 ( ) 1 M D D = − ( ) M D Flyback + - Load Vin Vo Co L Control S1 S2 ( ) M D ( ) 1 D M D D − = −

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There are many advantages of switching regulators to compare with the linear regulators and charge pumps. Switching regulator had high current efficiency because it used power MOSFET as switches and inductor, capacitors as energy stored elements. When the switched transistor operated in the cutoff region, it had no power dissipation. When the switched transistor operated in triode region, it was nearly a short circuit with little voltage drop across it, and had little power dissipation. Hence, almost power dissipation was spent in output node; high power efficiency could be achieved numerically in the range 80% to 90%.

Switching regulator also had disadvantages. There were more complexity in circuit design than the linear regulators and also required discrete components such as inductor and capacitors. Furthermore, the transition response time and output noise were larger than the linear regulators.

A comparison table between linear regulators, charge pumps and switching regulators were listed in Table 2. In Table 2, we can realize that switching regulators are the best choices for power supplies driving portable application because of their high efficiency and high power capability.

Table 2. Comparative table of power supply circuits.

Linear

Regulators

Charge

Pumps

Switching

Regulators

Efficiency Low Medium High

Power Capability Medium Medium High

Footprint area Compact Moderate Large

Cost Low Medium High

Complexity Low Medium High

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1.3

Thesis Organization

In the following chapters, the concepts of DC/DC buck converter with current-mode controller were organized in chapter 2. In chapter 3, we proposed the high-efficiency slope compensation (HSC) circuit used to eliminate the sub-harmonic oscillation phenomenon that is different from conventional compensation technique. In this chapter, the diagram accompany the mathematical derivation will be explained in detail. The analysis and designs of the sub-circuit implementation and the HSPICE simulation results were shown in chapter 4. Chapter 5 shows the optimal efficiency transition changing from PWM to PFM mode. The conclusions and results were included in chapter 5.

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Chapter 2

Definition and Operation Principle of

Current Mode Buck Converters

2.1

General Specifications

DC-DC converter of current-mode controller has been developed a long time. It had many specifications and performances that required recognizing. Current-mode controller of voltage regulator is difficult to analyze because of its multi-loop structure that consisted of voltage feedback loop as well as current feedback loop. There are many differences between voltage mode and current mode controller. In the following sections, we will model and simplify with intuitive method and mathematical derivations of the current-mode controller.

The following subsections include significant specifications such as load regulation, line regulation, transient response, loss and power efficiency were described in detail. Moreover, there are many kinds of operation modes like as CCM and DCM mode also included in this chapter.

Finally, in many applications, the current mode control technique almost had excellent performance with respect to the voltage mode controller. Hence, we will emphasize the current mode controller rather than the voltage mode one.

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2.1.1

Load Regulation

Load regulation is a measurement result that estimates the ratio of output voltage variation over load current changes. The equation (2) is written as below. A small load regulation value means that the converter has more immunity from output resistance variation. The design issue about minimizing the load regulation is increasing the system loop gain. Therefore, the load regulation could be improved.

Load Regulation out ( / )

out V mV mA I ∆ = ∆ (2)

2.1.2

Line Regulation

Line regulation is a measurement result that estimates the ratio of output voltage variation over input voltage changes. The equation (3) is written as below. It can account for the immunity from input noise. A small line regulation value has more robustness against to supply noise.

Line Regulation out ( / )

in V mV mV V ∆ = ∆ (3)

2.1.3

Transient Response

The transient response is an important measurement result that estimates the performance of converters. A good transient response implies that a small voltage drop and faster settling time on output node when output loading changes with step function. Therefore, the following describes the characteristics of transient response. It analyzed with output capacitor, equivalent series resistor of capacitor, transient time and so on.

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System bandwidth is a function of transient response that implies a wide bandwidth having faster transient response and small voltage drop. It can separate into two fields about frequency domain and time domain analysis. In frequency domain, literature about [13]-[16], used to position the pole and zero location when transient was occurred. In transient period, it moved the domain pole to higher frequency to get the higher unit gain bandwidth (UGB). In the same words, the higher unit gain bandwidth had faster transient response.

In time domain analysis, the system diagram of buck regulator with dynamic load response shows in Fig. 6. It shows that there are feedback resistor R1 R2, output capacitor Cout

and equivalent series resistor of capacitor RESR. Fig. 7 shows the transient waveform of output

voltage with load current variation. When the transient response was occurred namely load current from light to heavy, the transient period of t1 had low current drawn from high side

transistor. Owing to the system bandwidth restricted the speed of feedback response; the system is too late to extent the duty cycle that caused insufficient inductor current to provide for output node. Therefore, the output capacitor plays the role of current source to sustain the output current requirement. As a result, the voltage drop Vdrop can be formulated as:

1 , out

drop ESR ESR out ESR

out I t V V V I R C ∆ ⋅ = + = ∆ ⋅ (4)

(23)

The period t1 almost determined by the system bandwidth. At this transient period, the

voltage drop Vdrop equal the variation of charges on capacitor adds the VESR. The VESR

represents the quantity of output current variation to multiply the equivalent series resistance of capacitor. The period of t2 is dependent on the time requirement of the high side transistor

to charge the output capacitor to regulated voltage. The summation of t1 and t2 is known as

“Recovery Time”. In opposition side, the voltage peak Vpeak occurs at the load current from

heavy to light. When the transient response was acted, the transient period of t3 had large

current supplied from high side transistor. System bandwidth also restricted the speed of feedback response; the system is too late to reduce the duty cycle that caused much inductor current into output node. As a result, the voltage peak Vpeak will jump to high and formulated

as below.

At this transient period, the voltage drop Vdrop equals the variation of charges on

capacitor adds the VESR.

During the period t4, the redundant charges stored on output capacitor are discharged

through feedback resistor and the output voltage goes back to regulated level gradually.

3 , out

peak ESR ESR out ESR

out I t V V V I R C ∆ ⋅ = + = ∆ ⋅ (5)

(24)

2.1.4

Losses and Efficiency

2.1.4.1. Conduction Loss

Power loss of regulators is the combination of the switching loss and the MOSFET’s conduction loss in equation (6). The conduction loss also can classify into high-side transistor loss and low-side transistor loss.

Calculating the high-side conduction loss is straightforward that the conduction loss is just the I R2 loss timing the MOSFET’s duty cycle as below:

Where RDS ON( ) is at the maximum operation MOSFET junction temperature (TJ MAX( ))

Low-side loss are also comprised of conduction loss and switching loss. Conduction loss for low-side is given by:

2.1.4.2. Switching Loss

The switching interval begins when the high-side MOSFET driver turns on and begins to supply current power MOSFET’s gate to charge its input capacitance. There is no switching

MOSFET SW COND P =P +P (6) 2 ( ) OUT COND OUT DS ON IN V P I R V = ⋅ ⋅ (7) 2 ( ) (1 ) OUT COND OUT DS ON IN V P I R V = ⋅ ⋅ − (8)

(25)

loss until VGS reaches the MOSFET’s VTH therefore power loss equal zero.

When VGS reaches VTH, the input capacitance (CISS) is being charged and ID (the

MOSFET’s drain current) is rising linearly until it reaches the current IL which is presumed to

be Iout. During this period (t1) the MOSFET is sustaining the entire input voltage across it, the

energy in MOSFET during t1 is:

Now, we enter t2. At this point, Iout is flowing through high-side MOSFET, and the VDS begin

to fall. All of the gate current will be going to recharge CGD. CGD is similar to the “Miller”

capacitance of transistor, so t2 could be thought of as “Miller time”. During this time the

current is constant (at Iout) and the voltage is falling fairly linearly from VIN to 0, therefore:

The switching loss for any given edge is just the power that occurs in each switching interval, multiplied by the duty cycle of the switching interval:

Fig. 8. Transient waveform of VDS and ID curve in switching losses on power MOSFET

1 1 ( 2 ) in out t V I P = ⋅t ⋅ (9) 2 2 ( 2 ) in out t V I P =t ⋅ ⋅ (10) 1 2 ( ) ( ) 2 in out SW S V I P = ⋅ ⋅ t +tF (11)

(26)

2.1.4.3. Static Loss

The static loss also called as quiescent loss that was consumed by controllers of switching regulators. The smaller quiescent loss had higher efficiency.

The other power losses that don’t be mentioned above obeyed the rules ofI R2 .

2.1.4.4. Efficiency

The efficiency of switching regulator is defined as the ratio of the output power consumption and input power supplies, formed as below:

The input power supplies consist of the output consumption (PO), quiescent loss (PQ),

switching loss (PSW), conduction loss (PCOND) and other losses (PElse) in parasitic elements. A

high efficiency results in a high performance extending the battery life.

Q in Q P =VI (12) 100% O O ff in O Q SW COND Else P P E P P P P P P = = × + + + + (13)

(27)

2.2

DC Model for Current Mode Buck

Converter in CCM Analysis

The block diagram of DC-DC buck converter with current programmable controller is shown in Fig. 9. The power stage connected to high-side and low-side transistors called as power MOSFET. The gate signal of power MOSFET is drove by driver stage that the drive signal is generated by non-overlap and pulse generator circuit with pulse-width modulation (PWM) or pulse-frequency modulation (PFM) method. The control circuit also contained voltage-reference generator, sawtooth generator, voltage adder and current sensor that used to current programmable circuit only. The control sequence with pulse-width modulation (PWM) is described as follows.

In the first interval of switching period TS, the clock signal forced the high-side transistor

to turn on and the low-side transistor to turn off. At this interval, the inductor current ramped up and sensed by the current sensing circuit. The sensed signal Vsense is added with ramp

signal Vramp to avoid the sub-harmonic oscillation phenomenon in current mode controller.

When the sum of signal Vsense and Vramp exceed the error amplifier’s signal VC, the comparator

(COMP) turns from low to high and changes into the second interval of switching period. In the second interval, the power PMOS turns off and power NMOS turns on. The feedback voltage is forced the same as reference voltage that caused the output voltage is regulated in specified level. Moreover, there are two control loops feeding current signal and voltage signal by current feedback loop and voltage feedback loop, respectively. The current feedback loop constructed by current sense circuit and the voltage feedback loop constructed by error amplifier. In dynamic control, the output voltage variation affects the VC signal generated by

(28)

Fig. 9. The block diagram of current mode buck converter

The current programmed controller is unstable when converter operates above 50% duty cycle without compensation that shows in Fig. 10. The unstable problem called as sub-harmonic oscillation phenomena. In other words, the perturbed quantity of inductor current was large more and more during a few periods. The phenomena also occurred in other topologies such as boost and buck-boost converters. To avoid this stability problem, the control scheme is usually modified by adding an artificial ramp to the sensed current in the following descriptions.

The steady-state and perturbed waveform of inductor current are illustrated in Fig. 11. We can explain the phenomena of steady-state waveform and perturbed waveform with derived formula. The steady-state waveform of inductor current with m1 slope ramps up in

(29)

first interval and ramps down with m2 slope in second interval. When the perturbed waveform

of inductor current occurred with ˆdTs, the current difference was introduced in m dT1⋅ ˆ s [17][18].

The slope of inductor current equals:

According to Fig. 11, we can derive:

In steady-state, the above equation iL(0)=i TL( )s and shows as:

From Fig. 11, we can use the steady-state waveform to express the current difference iˆ (0)L

ˆ ( )L s

i T as the slope multiplied by the interval length, Hence:

c i ˆ S dT ˆ (D+d T) S DTS L I ˆ (0) L L I +i ˆ (0)L i ˆ ( )L s i T

Fig. 11. The perturbation waveform of inductor current

1 , 2 in out out V V V m m L L − = = (14) 2 1 2 ( ) ( ) (0) L s L s s L s s i T =i DTm D T′ =i +m DTm D T′ (15) ' 2 1 2 ' 1 0 m DTs m D Ts , then : m D m D = − = (16) 1ˆ 2ˆ ˆ (0) , ( )ˆ L s L s s i = −m dT i T =m dT (17)

(30)

Elimination of the intermediate variable ˆd from equation (17) leads to:

A similar analysis can be performed during the next switching period, show that:

After n switching periods, the perturbation becomes:

Note that, as n tends to infinity, the perturbation i nTˆ (L s) tends to zero provided that the

characteristic value –D/D’ has magnitude less than one. Conversely, the perturbation i nTˆ (L s)

becomes large in magnitude when the characteristic value α D D'

= − has magnitude greater than one:

Hence, for the stable operation of the current mode controller, we need D/D’<1 or D<0.5. The stable situation with compensation ramp is presented in Fig.12. When the converter operates with D<0.5, the perturbation inductor current will lead to be stable. Conversely, the perturbation inductor current will lead to be unstable to cause the sub-harmonic oscillation if converter operates with D>0.5 and no compensation.

2 ' 1 ˆ( ) ˆ (0) ˆ (0) L s L L m D i T i i m D   = ⋅ − = ⋅ −     (18) 2 ' ' ˆ(2 ) ˆ ( ) ˆ (0) L s L s L D D i T i T i D D     = ⋅ − = ⋅ −     (19) ' ' ˆ ( ) ˆ (( 1) ) ˆ(0) n L s L s L D D i nT i n T i D D     = − ⋅ ⋅ − = ⋅ −     (20) ' ˆ (L s) 0 D 1 i nT when D → − < ' ˆ (L s) D 1 i nT when D → ∞ − > (21)

(31)

The sub-harmonic oscillation is a well-known problem of current-mode controller. However, the converter can be stable at all duty cycles by adding the compensated ramp to the sensed inductor current as shown in Fig. 12. This compensated ramp has the qualitative effect of reducing the gain of the current sensing feedback loop to solve the unwanted oscillation problem in current-mode controller of dc-dc converters.

Fig. 12. Current-mode control signal with the compensation ramp and inductor current

The compensation theorem is represented in Fig. 13, the perturbation iˆ (0)L and i Tˆ ( )L s

can express in terms of the m1, m2, maand the −dTˆ s as follows:

c i ˆ S dT ˆ (D+d T) S DTS L I 0 ˆ (0) L L I +i ˆ (0)L i ˆ ( )L s i T ( ) c a ii t

(32)

Elimination of −dTˆ s yields:

A similar analysis can be used to the nth period, leading to:

For larger n periods, the perturbation magnitude i nTˆ (L s) tends to equations (26).

Therefore, for stability of current mode controller in CCM, it needs to choose the slope of the artificial ramp ma such that the characteristic value α has magnitude less than one. Conversely, the perturbation i nTˆ (L s) becomes larger when the characteristic value α has magnitude greater than one:

One common choice of the compensation ramp slop is

(

1

)

ˆ ˆ (0)L s a i = −dTm +m (22)

(

2

)

ˆ ˆ ( )L s s a i T = −dTmm (23) 2 1 ˆ ( ) ˆ (0) a L s L a m m i T i m m  −  = ⋅ −  +   (24) 2 2 1 1 ˆ ( ) ˆ (( 1) ) ˆ (0) ˆ (0) n n a a L s L s L L a a m m m m i nT i n T i i m m m m α  −   −  = − ⋅ ⋅ − = ⋅ −  = ⋅ + +     (25) ˆ (L s) 0 1 i nTwhen α < ˆ (L s) 1 i nT → ∞ when α > (26) 2 2 1 m ma = (27)

(33)

This compensation ramp results in the characteristic valueα to become zero for all duty cycle of the converter. Therefore, i Tˆ ( )L s is leading to zero for anyiˆ (0)L .

Another common choice of ma is:

The above characteristic causes the value α to become zero for all duty. As a result,

ˆ ( )L s

i T is zero for any iˆ (0)L that the controller doesn’t saturate. This behavior is known as

deadbeat control when the system corrects all errors after one switching period. And the compensated inductor current shows in Fig. 14.

2

a

m =m (28)

(34)

2.3

DC Model for Current Mode Buck

Converter in DCM Analysis

When the switches of dc-dc converter are implemented by using current-unidirectional semiconductor, there would be discontinuous conduction mode (DCM) introduced. The discontinuous conduction mode arises when the switching ripple of inductor current is large enough to cause the polarity of the applied switching current to reverse, such that the reversed current occurred. The DCM is commonly observed in dc-dc converters and rectifiers.

Discontinuous conduction mode typically occurs with large inductor current ripple at light loading and contains current-unidirectional switches. Since it is usually required that converters operate with their loads removed, DCM is frequently encountered. Moreover, some converters are purposely designed to operate in DCM mode for all loads.

A simple asynchronous buck converter shows in Fig. 15. The inductor current waveformIL, diode current waveform ID and the power MOS current

1 Q

I of switching

regulators are sketched in Fig. 16. The inductor current contains a dc component IL(avg) with an

amplitude of switching ripple iL.

(35)

When the load resistance RL is increased, the dc load current IL(avg) also decreased. As the

dc component of inductor current IL(avg) decreased, the ripple magnitude will still remain

unchanged. If we continue to increase RL, eventually the boundary is reached

2⋅ ∆iL

Fig. 16. The current waveform of inductor, diode and power MOS(IQ1)

( ) o L avg L V I R = (29) ' 2 2 in o in s L s V V V DD T i DT L L − = =  (30) ( ) L avg L I =i 2⋅ ∆iL L i 

(36)

whereIL avg( ) =iL, illustrated in Fig. 17. It can be seen that the inductor current IL and diode

current are both zero at the end of the switching period. Indeed, the load current is positive and nonzero.

When we continue to increase the load resistance RL, the diode current cannot be

negative; because of the diode in reverse-biased before the end of the switching period. As illustrated in Fig. 18, there are three subintervals during each switching period. During the first subintervalD T1 s, the transistor Q1 conducts and the diode conducts during the second

subintervalD T2 s. At the end of second subinterval, the diode current reaches zero, and the remainder of the switching period neither the transistor nor the diode conduct. The converter operates in discontinuous conduction mode.

1 s D T D T2 s D T3 s 2⋅ ∆iL ( ) L avg L I <i

Fig. 18. Inductor current are CCM and DCM operation at heavy and light loads

Formulation (31) suggests a way to fine the boundary between the continuous and discontinuous conduction modes. It can be seen that, for buck converter, the diode current is positive over the entire interval DTs < <t Ts provided thatIL avg( ) >iL. Hence, the conditions for operation in the continuous and discontinuous conduction modes are:

Where IL(avg) and iL are found assuming that the converter operates in continuous

( ) 0 without reversed current

L avg L

I −i >

( ) 0 with reversed current

L avg L

I −i <

(37)

conduction mode. Insertion of Eqs (29) and (30) into Eq. (31) yields the following condition for operation in discontinuous conduction mode:

Simplification leads to:

This can also be expressed in:

The dimensionless parameter K is a tendency measure of a converter to operate in discontinuous conduction mode. Large values of K lead to continuous mode operation, while small values lead to the discontinuous mode for different parameters. The critical value

( )

crit

K D is a function of duty cycle, and equals to D' for the buck converter.

The critical value Kcrit( )D versus duty cycle is plotted in Fig. 19. For the figure shown, it can be seen that the converter operated in DCM at low duty cycle, and CCM at high duty cycle. The Fig. 20 shows the switching converter in CCM mode with heavier loads. Namely, the load resistance RL is reduced, such that K is larger. If K is greater than one, then the

converter operates in continuous conduction mode for all duty cycles.

' 2 in s in L DV DD T V R < L (32) ' 2 L s L D R T < (33) ( ) crit K <K D for DCM ' 2 , crit( ) s L where K K D D RT = = (34) crit K <K K >Kcrit DCM CCM 1 crit K = −D 2 L s L K R T =

(38)

It’s simple to express the mode boundary in terms of the load resistance RL, rather than

the parameter K. Equation (34) can be rearranged to expose the dependent of the mode boundary with the load resistance:

crit K >K CCM 1 crit K D = − 2 L s L K R T =

Fig. 20. Switch converter operates in CCM mode for all duty

The conclusion can be formulated as below:

A similar mode boundary analysis can be performed for other converters. The boost and buck-boost converters are analyzed in the same manner. The results are listed in Table 3, for basic dc-dc converters.

Table 3 CCM-DCM mode boundaries for buck, boost, and buck-boost converters Converter Kcrit( )D

0 1

max( crit)

D K

≤ ≤ Rcrit( )D 0min (≤ ≤D 1 Rcrit)

Buck 1 D− 1 2 (1 ) s L D T − 2 s L T Boost D⋅ −(1 D)2 4 27 2 (1 ) s L D⋅ −D T 27 2 s L T Buck-Boost (1−D)2 1 2 (1 ) s L D T − 2 s L T ( ) ( ) crit crit R R D for CCM R R D for DCM < > ' 2 s L where R D T = (35) ( ) ( ) ( ) ( ) crit crit crit crit K K D or R R D for CCM K K D or R R D for DCM > < < > (36)

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Chapter 3

Derivation and Circuit Implementation

of High-Efficiency Slope Compensation

Technique

So far, we know that the current programmable controlled converter requires the slope compensation technique to eliminate the sub-harmonic oscillation phenomenon. Hence, the use of artificial ramp adding to the sensed inductor current is a useful and popular method in control circuits. As shown in Fig. 21, the Current-Sensor circuit connects to the Vx node that

located between High-side PMOS and Low-side NMOS and introduces Vsense signal. The Slope

Compensator circuit introduces Vslope_comp signal periodically. The both signals Vsense and

Vslope_comp go through the voltage-to-current (V-I) circuits to introduce Isense and Islope_comp

(40)

signal, respectively. The both signals Isense and Islope_comp flow into the resistor Rsum and

generate the Vsum signal. The signal Vsum will define the duty cycle of switching converter.

This paper introduced the operation modes with pulse width modulation (PWM) and pulse frequency modulation (PFM) in heavy load and light load condition, respectively [19][20]. However, there is a significant problem that how to decide the suitable transition time from PWM to PFM mode. Therefore, in conventional mode-transition method, shown in Fig. 22, there is a Mode Detector & PFM Controller circuit that consists of Zero-Current Detector,

ZCD Counter, Mode Selector and PFM Controller.

When the converter operates in light loading and the inductor current ripple is larger than the average load current, it’s occurred reversal flowing. The Vx voltage touched the zero

voltage to generate the one-shot signal (ZCD signal) in the output of Zero-Current Detector. The ZCD signal accessed into the ZCD Counter to identify, whether the converter changes into PFM mode or not. Then, the signal accesses into Mode Selector circuit to decide the operation mode and able or disable the PFM Controller immediately.

Unfortunately, the VX signal has poor noise immunity and is easy to be coupled by

turning on/off of power MOSFETs. Especially, this scenario is deteriorated in high switching

(41)

randomly transits between PWM and PFM modes. Therefore, this paper presents a method using the output voltage (VC) of error amplifier as a detection signal rather than the VX voltage

in Fig. 23. The output voltage of error amplifier can be input independent parameter by means of the proposed HSC controller. The signal VC only depends on load current condition.Thus,

the new detection signal VC with robust immunity to noise contains load current information

to identify the operation mode immediately without using the Zero-Current Detector. Thus, in the following descriptions, we will introduce the control issues of proposed high-efficiency slope compensation circuit and circuit implementations.

3.1

Concern Issues of Proposed Slope

Compensation Technique

High-efficiency slope compensation technique, shown in Fig. 24, as the supply voltage (VIN) changes from high to low, the duty cycle (D) changes from low to high. Thus, the output

voltage (VC) of error amplifier will raise a voltage difference (∆V). If we use the VC voltage as

(42)

a detection signal to identify the operation mode, the voltage difference (∆V) makes the load current identification with wrong state. Figure shows that the duty cycle increases as the supply voltage decreases, the raising voltage difference (the red dash line) touches the boundary of operation mode (VPFM_S) and turns on the PFM mode operation. For example,

200mA of load current is the boundary of mode transition. Due to the voltage difference rising, the load current drops to 150mA to change mode. It implies that the PFM mode is delay to turn on. Oppositely, the duty cycle decreases as the supply voltage increases, the falling voltage difference (the blue dash line) touches the boundary of operation mode (VPFM_S) and

turns on the PFM mode operation. It implies that the PFM mode is early to turn on. Owing to the supply voltage variation, the output voltage (VC) of error amplifier would be disturbed by

a voltage difference (∆V). Therefore, the next section will introduce the proposed high-efficiency slope compensator to overcome the above problems.

Moreover, the simple architecture of current mode buck converter is shown in Fig. 25. The sensed voltage from current sensing circuit and the compensated ramp from sawtooth generator flow into the V-I Pair circuit and introduce the summation signal Vsum. The Vsum

signal and the Vc signal, which comes from error amplifier; connect to the comparator CMP to

generate the Reset signal. The both signal CLK and Reset feed through the Pulse-Generator circuit to define the PWM duty cycle of switching period. When the Vsum signal varied with

(43)

duty cycle, the Vc signal will also follow the Vsum signal to define equivalent duty width as the

same previous switching period because of duty cycle is only dependent on Vin and Vout

voltages.

According to theory of the Vc signal varies with the Vsum signal, we can use the Vsum

signal to control the Vc signal on our way. As the Vc signal is changed by output load current

variation only, it had current information of heavy or light loadings. Thus, we can use the Vc

signal to identify, what is the suitable opportunity for changing the operation mode. Hence, we have to design the Vsum signal independently with supply voltage and dependents on load

current variations. Therefore, the Vsum signal is controlled by the load current variation

specifically. We used the Vc signal to decide the suitable transition time from pulse width

modulation (PWM) into pulse frequency modulation (PFM) mode.

Driver Driver Pg Ng Vreset Vsum R S Q QB VCLK PWM Duty COMP EA Vout RL CL RF1 RF2 FB Vin Lx P_MOS N_MOS VC Deadtime Control Reference IL ∑ + + Vsense Vslope_comp Reset CLK Q (Duty) Vc Vc Vsum when ILoad Vsum' ∆V

(44)

3.2

Design Theorem of Proposed Slope

Compensation Technique

According to theory of the Vc signal varies with the Vsum signal, we have to design the

Vsum signal independent of input voltage variation and only dependent on load current changes.

Thus, in this section, we will derive the mathematical formulas by changing supply voltages from high to low with fixing the output voltage. In other words, the output voltage is identical all the time regardless of input voltage variation.

In Fig. 26, the Isense and Iramp signals is introduced by current-sense and Ramp-Generator

circuits through the voltage-to-current (V-I) circuits, respectively. The both signals Isense and

Iramp flow into the resistor Rsum and generate the summation result Vsum signal, shown in

equation (37).

The Vsum signal consists of the Iramp current adding the Isense current and both are

Fig. 26. The slope compensation diagram of current mode buck converter

(

_ ( ) ( )

)

sum slope comp S sense S sum

(45)

multiplied by Rsum resistor. Therefore, we will analysis the Vsum signal to separate into the Iramp

current and the Isense current individually. To identify what factors affected the quantities of the

Iramp and Isense current.

As depicted in the Fig. 27 below, the waveform is the inductor current with ramp up and ramp down slopes in switching period called as m1 and m2. The equations of m1 and m2

expressed as (38), (39).

The slope m1 ramps up in DTs period and slope m2 ramps down in Ts-DTs period. Hence,

we can derive the iL(DTs) that consists of the IL(avg) and half of ∆IL(PP) to express the

relationships between IL(avg) and ∆IL(PP) in equation (40). The signal iL(DTs) means the

waveform function of inductor current.

The IL(avg) means the average value of inductor current. We can realize that the average

value of inductor current is reverse proportional to the output resistor RL, shown in equation

1 in out V V m L − = (38) 2 out V m L = (39) S DT ( ) L s i T (0) L i ( ) L PP

I



( ) L S i DT

Fig. 27. Inductor current in DC and AC analysis

1

( ) 2 ( )

( )

L S L avg L pp

(46)

(41).

And the ∆IL(PP) can express as slope m1 to multiply the first interval of switching period

DTs or the slope m2 to multiply the second interval of switching period (1-D)Ts, shown in

equation (42) and (43).

Therefore, the iL(DTs) is the summation of Eqs (41) and (42) leading to:

We can recognize that the iL(DTs) signal with constant parameters of Vout, L, fs is

dependent on the variables of duty cycle (D) and output resistor (RL). In other words, the

iL(DTs) signal is reverse proportional to the duty cycle and output resistor RL as input voltage

variation and output load current changes, respectively. Because the resistor RL is reverse

proportional to the load current, the iL(DTs) signal is proportional to the load current changes.

Hence, there are two parameters of output resistor (RL) and duty cycle (D) to change the

iL(DTs) signal of inductor current.

The Fig. 28 shows the current sensing circuit that almost used to current programmable controller. The circuit sensed the inductor current in the first interval of switching period. The sensed current of inductor is scaled down by a factor K to generate the signal Isense. The Isense

signal flows into the resistor Rsense to introduce the voltage Vsense that is the output signal of

current sensing circuit.

( ) out L avg L V I R = (41) ( ) 1 in out L PP s s V V I m DT DT L − = ⋅ = ⋅  (42) ( ) 2 (1 ) out (1 ) L PP s s V I m D T D T L = − ⋅ − = ⋅ −  (43) 1 ( ) [ , , constant ] 2 out L S out out S L S V D i DT V V L f are R L f − = + ⋅ (44)

(47)

Fig. 28. Current sensing circuit

In Eqs (45), the signal IS(DTS) is the iL(DTs) divided by a K factor to scale down the

quantities of inductor current.

The sensed current flowed into the resistor to generate the voltage Vsense(DTS) in Eqs (46).

Arranging the equation, the Vsense(DTS) equals the Rsense to divide by a factor K and multiplied

by iL(DTs).

In equation (47), we use the symbol Rs to express the Rsense over factor K called as

current sensing equivalent resistor or sensing gain.

Recommendation of current sensing equivalent resistor Rs is in the range 0.5 ~ 1 ohm.

This paper assumed the equivalent resistor to equal one ohm for simplification the circuit design. Hence, the Vsense(DTS) voltage equals the i DTL( S) function.

( ) ( ) L S S S i DT I DT K = (45) ( ) ( ) sense ( ) sense S S S sense L S R V DT I DT R i DT K = ⋅ = ⋅ (46) ( ) ( ) ( ) 1 , [ 1 ] sense S S L S L S S V DT =Ri DT =i DT ⋅ Ω let R = Ω (47)

(48)

So far, we had derived the inductor current varied with duty cycle and output loadings. Therefore, the continued conceptions will derive the sawtooth ramp information dependent on duty cycle variations.

The sawtooth ramp (Vramp) with clock pulse (VCLK) is depicted as below in Fig. 29. The

clock signal changes to high level when the sawtooth signal ramps down from VH to VL. On

the other hand, the, the clock signal changes to low level when the sawtooth signal ramps up from VL to VH.

10% Duty

Vram

p

Fig. 29. Sawtooth waveform with clock pulse

In the analysis of sawtooth ramp, the microcosmic waveform is illustrated in Fig. 30. The sawtooth signal ramps up and down between the VH and VL voltages. The upper and lower

boundary (VH, VL) define the sawtooth ramp region from zero percent duty to one hundred

percent duty of switching period. As the duty beginning, the sawtooth ramps up from 0% to

( , ) ( , )

X Y D V

(49)

90% duty. When the ramp signal touched the upper boundary VH, it ramps down from 90%

duty to 100% duty to accomplish complete switching cycle. However, the afterward 10% ramp is useless for system stability, we will derive the relationships of the sawtooth signal and duty cycle in the first interval of switching cycle. Then, the linear algebra is a useful manner to prove the relations.

In the figure shows, the x-axis means duty cycle and the y-axis means voltage. We can use the equation to derive the following in Eqs (48).

To arrange the above equation, Y signal expressed as below that is dependent on X variable.

Replacement the X variable with duty cycle (D) and Y variable with ramp signal (Vramp)

showed in equation (50). 90% 0% L H L Y V V V X − − = − (48) 0.9 H L L V V Y = − ⋅X +V (49) [ , constant ] 0.9 H L ramp L H L V V V = − ⋅D V+ V V are (50)

數據

Fig. 3. The schematic of a close loop switching capacitor voltage doubler
Fig. 3. The schematic of a close loop switching capacitor voltage doubler p.15
Fig. 6 System diagram of buck converter with dynamic load response
Fig. 6 System diagram of buck converter with dynamic load response p.22
Fig. 10. Inductor current at stable and unstable oscillation in current-mode converter
Fig. 10. Inductor current at stable and unstable oscillation in current-mode converter p.28
Fig. 16. The current waveform of inductor, diode and power MOS(I Q1 )
Fig. 16. The current waveform of inductor, diode and power MOS(I Q1 ) p.35
Fig. 18. Inductor current are CCM and DCM operation at heavy and light loads
Fig. 18. Inductor current are CCM and DCM operation at heavy and light loads p.36
Table 3 CCM-DCM mode boundaries for buck, boost, and buck-boost converters  Converter  K crit ( )D max( 0 ≤ ≤D 1 K crit ) R crit ( )D 0 min (≤ ≤D1 R crit )

Table 3

CCM-DCM mode boundaries for buck, boost, and buck-boost converters Converter K crit ( )D max( 0 ≤ ≤D 1 K crit ) R crit ( )D 0 min (≤ ≤D1 R crit ) p.38
Fig. 20. Switch converter operates in CCM mode for all duty
Fig. 20. Switch converter operates in CCM mode for all duty p.38
Fig. 24. Duty cycle variation due to supply voltage variation and mode transition diagram
Fig. 24. Duty cycle variation due to supply voltage variation and mode transition diagram p.42
Fig. 25. Simple architecture of current mode buck controller in different loads
Fig. 25. Simple architecture of current mode buck controller in different loads p.43
Fig. 38. The combination voltage of both signal V sense  and V slope_comp
Fig. 38. The combination voltage of both signal V sense and V slope_comp p.55
Fig. 39. Matlab diagram of V sense , V slope_comp  and V sum  signals
Fig. 39. Matlab diagram of V sense , V slope_comp and V sum signals p.56
Fig. 45. The architecture of current mode buck converter with PWM controller
Fig. 45. The architecture of current mode buck converter with PWM controller p.62
Fig. 50. The schematic of folded-cascode operational amplifier with PMOS input
Fig. 50. The schematic of folded-cascode operational amplifier with PMOS input p.67
Fig. 58. The schematic of the integrated sensing circuit with power stage
Fig. 58. The schematic of the integrated sensing circuit with power stage p.73
Fig. 62. The schematic of percent duty and quadratic ramp generator Fig. 61. The simulation result of the clock and sawtooth generator
Fig. 62. The schematic of percent duty and quadratic ramp generator Fig. 61. The simulation result of the clock and sawtooth generator p.76
Fig. 63. The simulation waveforms of quadratic ramp and 10% control pulse
Fig. 63. The simulation waveforms of quadratic ramp and 10% control pulse p.77
Fig. 71. The architecture of current mode buck converter with PFM controller
Fig. 71. The architecture of current mode buck converter with PFM controller p.82
Fig. 74. Simulation waveform of inductor current and Vc signal in supply voltage variation
Fig. 74. Simulation waveform of inductor current and Vc signal in supply voltage variation p.86
Fig. 75. Simulation waveforms of V sense , V slope_comp  and V sum  in supply voltage variation
Fig. 75. Simulation waveforms of V sense , V slope_comp and V sum in supply voltage variation p.87
Fig. 77. Simulation waveforms of output voltage and inductor current ripple
Fig. 77. Simulation waveforms of output voltage and inductor current ripple p.88
Table 7. The parameters of load transient response in PWM mode

Table 7.

The parameters of load transient response in PWM mode p.90
Fig. 81. The simulation waveforms in PFM mode  Table 8. The characteristics of different loading in PFM mode
Fig. 81. The simulation waveforms in PFM mode Table 8. The characteristics of different loading in PFM mode p.91
Fig. 83. Full chip simulation: Transition from PFM to PWM mode (rising step load)
Fig. 83. Full chip simulation: Transition from PFM to PWM mode (rising step load) p.93
Fig. 82. Full chip simulation: Transition from PWM to PFM mode (falling step load)
Fig. 82. Full chip simulation: Transition from PWM to PFM mode (falling step load) p.93
Fig. 84. System efficiency with different supply voltage in PFM mode
Fig. 84. System efficiency with different supply voltage in PFM mode p.94
Fig. 85. The relationships of supply voltage, loading current and PFM_S voltage
Fig. 85. The relationships of supply voltage, loading current and PFM_S voltage p.95
Fig. 86. Current fitting diagram of PFM_S voltage and loading current
Fig. 86. Current fitting diagram of PFM_S voltage and loading current p.96
Fig. 88. Efficiency improvement in mode transition region with HSC controller
Fig. 88. Efficiency improvement in mode transition region with HSC controller p.97
Fig. 89. Whole chip layout diagram of proposed slope compensation circuit
Fig. 89. Whole chip layout diagram of proposed slope compensation circuit p.98
Fig. 90. Core circuit layout diagram of proposed slope compensation circuit
Fig. 90. Core circuit layout diagram of proposed slope compensation circuit p.98

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