Design Theorem of Proposed Slope Compensation Technique

According to theory of the Vc signal varies with the Vsum signal, we have to design the

V

_sum signal independent of input voltage variation and only dependent on load current changes.

Thus, in this section, we will derive the mathematical formulas by changing supply voltages from high to low with fixing the output voltage. In other words, the output voltage is identical all the time regardless of input voltage variation.

In Fig. 26, the I_sense and I_ramp signals is introduced by current-sense and Ramp-Generator circuits through the voltage-to-current (V-I) circuits, respectively. The both signals Isense and

I

_ramp flow into the resistor R_sum and generate the summation result V_sum signal, shown in equation (37).

The Vsum signal consists of the Iramp current adding the Isense current and both are Fig. 26. The slope compensation diagram of current mode buck converter

(

_

( ) ( ) )

sum slope comp S sense S sum

V = I DT + I DT ⋅ R

(37)

multiplied by Rsum resistor. Therefore, we will analysis the Vsum signal to separate into the Iramp

current and the I_sense current individually. To identify what factors affected the quantities of the

I

ramp and Isense current.

As depicted in the Fig. 27 below, the waveform is the inductor current with ramp up and ramp down slopes in switching period called as m1 and m2. The equations of m1 and m2

The IL(avg)

means the average value of inductor current. We can realize that the average

value of inductor current is reverse proportional to the output resistor R_L, shown in equation

1

V

in

V

out

Fig. 27. Inductor current in DC and AC analysis

1

( ) 2 ( )

( )

L S L avg L pp

i DT

=

I

+ ∆

I

(40)

(41).

And the ∆I_L(PP) can express as slope m₁ to multiply the first interval of switching period

DTs or the slope m

2 to multiply the second interval of switching period (1-D)Ts, shown in equation (42) and (43).

Therefore, the iL(DTs) is the summation of Eqs (41) and (42) leading to:

We can recognize that the iL(DTs) signal with constant parameters of Vout, L, fs is dependent on the variables of duty cycle (D) and output resistor (R_L). In other words, the

i

L(DTs) signal is reverse proportional to the duty cycle and output resistor RL as input voltage variation and output load current changes, respectively. Because the resistor R_L is reverse proportional to the load current, the iL(DTs) signal is proportional to the load current changes.

Hence, there are two parameters of output resistor (R_L) and duty cycle (D) to change the

i

L(DTs) signal of inductor current.

The Fig. 28 shows the current sensing circuit that almost used to current programmable controller. The circuit sensed the inductor current in the first interval of switching period. The sensed current of inductor is scaled down by a factor K to generate the signal I_sense. The I_sense signal flows into the resistor Rsense to introduce the voltage Vsense that is the output signal of current sensing circuit.

Fig. 28. Current sensing circuit

In Eqs (45), the signal IS

(DT

S

)

is the iL(DTs) divided by a K factor to scale down the quantities of inductor current.

The sensed current flowed into the resistor to generate the voltage Vsense

(DT

S

) in Eqs (46).

Arranging the equation, the V_sense

(DT

_S

) equals the R

_sense to divide by a factor K and multiplied by iL(DTs).

In equation (47), we use the symbol R_s to express the R_sense over factor K called as current sensing equivalent resistor or sensing gain.

Recommendation of current sensing equivalent resistor Rs is in the range 0.5 ~ 1 ohm.

This paper assumed the equivalent resistor to equal one ohm for simplification the circuit design. Hence, the V_sense

(DT

_S

) voltage equals the i DT

_L( _S) function.

( )

( )

^{L S}

S S

I DT i DT

= K

(45)

( ) ( )

^sense

( )

sense S S S sense L S

V DT I DT R R i DT

= ⋅ = K ⋅

(46)

( ) ( ) ( ) 1 , [ 1 ]

sense S S L S L S S

V DT

=

R

⋅

i DT

=

i DT

⋅ Ω

let R

= Ω (47)

So far, we had derived the inductor current varied with duty cycle and output loadings.

Therefore, the continued conceptions will derive the sawtooth ramp information dependent on duty cycle variations.

The sawtooth ramp (V_ramp) with clock pulse (V_CLK) is depicted as below in Fig. 29. The clock signal changes to high level when the sawtooth signal ramps down from VH to VL. On the other hand, the, the clock signal changes to low level when the sawtooth signal ramps up from VL to VH.

10% Duty

V

^ram

p

Fig. 29. Sawtooth waveform with clock pulse

In the analysis of sawtooth ramp, the microcosmic waveform is illustrated in Fig. 30. The sawtooth signal ramps up and down between the VH and VL voltages. The upper and lower boundary (V_H, V_L) define the sawtooth ramp region from zero percent duty to one hundred percent duty of switching period. As the duty beginning, the sawtooth ramps up from 0% to

( , ) ( , )

X Y D V

Fig. 30. The microcosmic waveform of sawtooth ramp

90% duty. When the ramp signal touched the upper boundary VH, it ramps down from 90%

duty to 100% duty to accomplish complete switching cycle. However, the afterward 10%

ramp is useless for system stability, we will derive the relationships of the sawtooth signal and duty cycle in the first interval of switching cycle. Then, the linear algebra is a useful manner to prove the relations.

In the figure shows, the x-axis means duty cycle and the y-axis means voltage. We can use the equation to derive the following in Eqs (48).

To arrange the above equation, Y signal expressed as below that is dependent on X variable.

Replacement the X variable with duty cycle (D) and Y variable with ramp signal (V_ramp) showed in equation (50).

Fig. 31. Duty cycle with percent duty control

Moreover, this paper proposed a significant ten percent control pulse that is produced before the ending of duty width [21][22][23]. In other words, the pulse signal occurred before ending the system duty is 10%. For example, when the system operates at 70% duty cycle, the pulse signal operates at logic low from 60% to 70% duty width of switching cycle. The concept is illustrated in Fig. 31. The PWM_PG is the signal that controlled the high-side MOSFET and the width of logic high is the system duty cycle. The shaped region of V_S signal is ten percent width of switching cycles. Thus, we use the produced signal VS to the next stage circuit called as slope controller to generator the quadratic ramp (Vquadratic_ramp) in 10% region.

The simple diagram with Iramp current source, two MOS switches and a charged capacitor is showed in Fig. 32. The ramp current is controlled by the 10% signal of V_S pulses. When the

V

S signal is low, the Iramp current flowed into the capacitor as the MP1 is turned on. Oppositely, the V_S signal is high, the charge drained out of the capacitor as the MN₁ is turned on. During the charging and discharging switches, the circuit generates the output signal of Vquadratic_ramp

voltage periodically. The Vquadratic_ramp voltage will be used to replace the original sawtooth signal of conventional slope compensation circuit. The proposed Vquadratic_ramp voltage is effective to maintain the V_C voltage regardless of power supply variations. Therefore, the following descriptions will derive the proposed theorem in procedures.

Fig. 32. The simple diagram of the slope controller

Fig. 33. The Iramp current is charging only with 10% pulse

The Fig. 33 shows the Iramp current to charge the capacitor with 10% charging time of switching period. Because of the I_ramp current is proportional to the duty cycle, the different time is corresponding to different quantities of Iramp signal. We can recognize that the Iramp_1

current corresponds to D₁ at the beginning of charging, and he I_{ramp_2} current corresponds to

D

2 at the end of 10% pulse. Then, we use the formula that derived in equation (49) to represent the different ramp voltage on different duty in equation (51) and (52).

The different ramp voltages (Vramp_1 & Vramp_2) on different duty were transformed into current signals (I_{ramp_1} & I_{ramp_2}) with assumed resistor R_x in equation (53).

According to the formula of the capacitor charging in equation (54), the charged voltage

_1 1

is the current multiplying by the time period and dividing by capacitor value.

We got the result of V_{slope_comp} signal that is the integration of the shaped area in Fig. 33 and in equation (55).

Elimination the variable D₁ and D₂ for simplification, the above equation is replaced into

D

2

=D and D

1

=D

2

-0.1 in equation (56) as below.

The V_{slope_comp} signal is a linear equation to the duty cycle D and plots in Fig. 34. In addition, the Vslope_comp signal is the link of peak value of each quadratic ramp (Vquadratic_ramp).

_

Fig. 34. The Vslope_comp function is a linear equation with respect to duty cycle

For example, there are two quadratic ramps (Ramp₁, Ramp₂) in different duty cycle. The peak values of the different quadratic ramps are the quadratic function (Vslope_comp) to substitute into the corresponding duties. The Vquadratic_ramp signal is a quadratic equation to the duty cycle D. But the charging period is 10% of switching cycle, the waveform of

V

quadratic_ramp signal in Fig. 34 is nearly like as linear equation.

Fig. 35. The schematic of voltage adder

In the current programmable controller, we have to combine the both signal V_sense and

V

quadratic_ramp together to suppress the sub-harmonic oscillation. As the Fig. 35 shown, the pairs of voltage-to-current circuit are consisted of operational amplifiers to form a voltage adder.

Rather than the conventional sawtooth ramp, the proposed signal Vquadratic_ramp is applied to the negative node of OP₁. The combination of both signals is expressed in equation (57) as below.

Substituting equations (44) and (56) into (57), we got the following formula in equation (58) and the parameters of V_H, V_L, capacitor C, inductor L, frequency f_s, output voltage V_out, R_x and output resistor RL are constant values. According to the above analysis, the Vsense is reverse proportional to the duty cycle and the V_{slope_comp}

(DT

_S

) is proportional to the duty cycle.

_

We can represent the combinations of equation (44) with positive slope and the equation (56) with negative slope to form the equation (59). The voltage-to-current circuit in Fig. 35 provides a function of scaling. The symbol

α

and β represent the R_sum over R_S1 and the

R

_sum over R_S2, respectively in equation (60).

The equation (61) shows the Vsum signal is the combination of the positive slope adding the negative slope multiplying the scaling

α

and β , respectively. Therefore, the use of changing the scaling quantities is an effective method to eliminate the slopes of positive and negative voltage each other.

So far, we made analyses and derived the equations of the high-efficiency slope compensation technique. The technique is a useful way to control the Vsum signal independent of supply voltage variation. As the result, the V_c signal is only dependent on the output

Fig. 36. The Vsense function is reverse proportional to the duty cycle

1 2

Finally, we synthesize the concepts to make the function plots of each equations derived before. In Fig. 36 shown, the V_sense waveform is reverse proportional to the duty cycle as the same as the equation derived in equation (44).

_

Fig. 37. The V_{slope_comp} function is proportional to the duty cycle

In Fig. 37 shown, the V_{slope_comp} waveform is proportional to the duty cycle as the same as the equation derived in equation (56).

[ V

_H

, V C f

_L

, ,

_S

, R

_X

, V

_out

, R

_L

, are constant] L

Fig. 38. The combination voltage of both signal V_sense and V_{slope_comp}

The combination signal Vsum is horizontal to imply that we could vary the symbol

α

and

β

to balance the difference of slope showed Fig. 38. In order to verify the analysis is correct and useful for the current programmable controller, this paper simulates these equations with MATLAB computer program. As illustrated in Fig. 39, the blue line indicates the V_{slope_comp} signal proportional to the duty cycle and the green line indicates the V_sense signal reverse proportional to the duty cycle.

V

_sum

(I

_L

) V

_sense

(DT

_S

)

V

slope_comp

(DT

S

)

Vslope_comp

Fig. 39. Matlab diagram of Vsense, Vslope_comp and Vsum signals

As a result, the Vsum signal of the red line is horizontally independent of the duty cycle.

Therefore, the method that eliminates the positive and negative slope is effective to suppress the duty variation. As long as the Vsum signal is controlled on our way, we could use the Vc

signal to identify the situation of output loading. In other words, the voltage level of V_c signal reflect the quantities of load current information. Hence, we could use the Vc signal comparing with the pre-defined voltage to switch the operation modes.

Moreover, a significant issue should be concerned is the choice of parameters

α

and

β

. In current mode controllers, the compensation slope is used to suppress the unstable state of oscillation. If the compensation slope exceeds the suitable quantities, the current mode controller will be operated like a voltage mode converter that called as deadbeat control mentioned in chapter two. On the other hand, if the compensation slope is insufficient, it’s still occurred unstable oscillation. The concept is illustrated in Fig. 40. The slope of sensed inductor current in second period and the proposed quadratic ramp is represented as S(I2

) and

In the figure shows, we can use the parameters

α

and

β

to modify the slope of compensation ramp S(Vquadratic_ramp

) and sensed current S(I

₂

)·R

_s. Owing to the stability issue, the slope of compensation ramp must be grater than half times of S(I2

)·R

s and be smaller than one times of S(I₂

)·R

_s.

Fig. 40. Slope compensation values in reasonable range

As mentioned before, the symbol

α

and

β

is presented as:

The stability issue is expressed below in equation (63). The parameters

α

and

β

is an effective way to control the system for stable. Hence, in this paper, we choice

α

is twice as

β

.

3.3 Circuit Implementation of Proposed

在文檔中 具高效能斜率補償器及與輸入電源無關之負載電流識別機制的電流模式直流/直流降壓電源轉換器 (頁 44-58)